[igt-dev] [PATCH i-g-t 07/15] intel_gpu_top: Determine number of tiles

[igt-dev] [PATCH i-g-t 07/15] intel_gpu_top: Determine number of tiles

[Umesh Nerlige Ramappa]

Find out how many tiles are present in the platforms for multi-tile support.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tools/intel_gpu_top.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 3d21f25bd..695f57526 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -117,6 +117,8 @@ struct engines {
 	bool discrete;
 	char *device;
 
+	int num_gts;
+
 	/* Do not edit below this line.
 	 * This structure is reallocated every time a new engine is
 	 * found and size is increased by sizeof (engine).
@@ -533,6 +535,25 @@ static void imc_reads_open(struct pmu_counter *pmu, struct engines *engines)
 	imc_open(pmu, "data_reads", engines);
 }
 
+static int get_num_gts(uint64_t type)
+{
+	int fd, cnt;
+
+	errno = 0;
+	for (cnt = 0; cnt < MAX_GTS; cnt++) {
+		fd = igt_perf_open(type, __I915_PMU_REQUESTED_FREQUENCY(cnt));
+		if (fd < 0)
+			break;
+
+		close(fd);
+	}
+	assert(!errno || errno == ENOENT);
+	assert(cnt > 0);
+	errno = 0;
+
+	return cnt;
+}
+
 static int pmu_init(struct engines *engines)
 {
 	unsigned int i;
@@ -541,6 +562,7 @@ static int pmu_init(struct engines *engines)
 
 	engines->fd = -1;
 	engines->num_counters = 0;
+	engines->num_gts = get_num_gts(type);
 
 	engines->irq.config = I915_PMU_INTERRUPTS;
 	fd = _open_pmu(type, engines->num_counters, &engines->irq, engines->fd);
-- 
2.34.1

[igt-dev] [PATCH i-g-t 00/15] PMU: multi-tile support

[Umesh Nerlige Ramappa]

Enable IGT PMU support for multi-tile platforms.
Add multi-tile support for intel_gpu_top.

v2: (Tvrtko)
- Instead of adding gtN suffix to item, add it to parent group
- Show split gt values only if -p option is specified
- Display aggregate value as default without -p option
- Break down patches into reviewable units

v3: (Ashutosh, Tvrtko)
- Reformat GT info in INTERACTIVE mode
- Use i915_for_each_gt
- Move uapi to i915_drm_local.h
- Use gem_list_engines() and drop unnecessary code

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Riana Tauro (1):
  perf_pmu: Use correct pmu config for multi-tile

Tvrtko Ursulin (3):
  perf_pmu: Support multi-tile in rc6 subtest
  perf_pmu: Two new rc6 subtests
  perf_pmu: Support multi-tile in frequency subtest

Umesh Nerlige Ramappa (11):
  perf_pmu: Quiesce GPU if measuring idle busyness without spinner
  intel_gpu_top: Add an array of freq and rc6 counters
  intel_gpu_top: Determine number of tiles
  intel_gpu_top: Capture freq and rc6 counters from each gt
  intel_gpu_top: Switch pmu_counter to use aggregated values
  intel_gpu_top: Add definitions for gt-specific items and groups
  intel_gpu_top: Bump up size of groups to accomodate multi-gt
  intel_gpu_top: Increase visibility for class_view
  intel_gpu_top: Show gt specific values if requested
  intel_gpu_top: Reduce one level of indent
  intel_gpu_top: Add gt specific values to header in interactive mode

 lib/i915/i915_drm_local.h |  15 ++
 tests/i915/perf_pmu.c     | 307 +++++++++++++++++++++++++++-----------
 tools/intel_gpu_top.c     | 238 ++++++++++++++++++++++++-----
 3 files changed, 432 insertions(+), 128 deletions(-)

-- 
2.36.1

[igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Teach test how to wake up a particular tile and make it iterate all of
them using dynamic subtests.

v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h
v3: (Ashutosh)
- Use i915_for_each_gt
- Move uapi to i915_drm_local.h

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 lib/i915/i915_drm_local.h | 15 +++++++++++++++
 tests/i915/perf_pmu.c     | 34 +++++++++++++++++++++++-----------
 2 files changed, 38 insertions(+), 11 deletions(-)

diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index af0176500..bb2ebef38 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -26,6 +26,21 @@ extern "C" {
 #define DRM_I915_PERF_PROP_OA_ENGINE_CLASS	9
 #define DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE	10
 
+/*
+ * Top 4 bits of every non-engine counter are GT id.
+ */
+#define __I915_PMU_GT_SHIFT (60)
+
+#define ___I915_PMU_OTHER(gt, x) \
+	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
+	((__u64)(gt) << __I915_PMU_GT_SHIFT))
+
+#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
+#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
+#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
+#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
+#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index c5f083bbd..86607be4d 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
 	return suspended;
 }
 
+static int open_forcewake_handle(int fd, unsigned int gt)
+{
+	if (getenv("IGT_NO_FORCEWAKE"))
+		return -1;
+
+	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
+}
+
 static void
-test_rc6(int gem_fd, unsigned int flags)
+test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 {
 	int64_t duration_ns = 2e9;
 	uint64_t idle, busy, prev, ts[2];
@@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
 
 	gem_quiescent_gpu(gem_fd);
 
-	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
+	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
 
 	if (flags & TEST_RUNTIME_PM) {
 		drmModeRes *res;
@@ -1784,7 +1792,7 @@ test_rc6(int gem_fd, unsigned int flags)
 	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
 
 	/* Wake up device and check no RC6. */
-	fw = igt_open_forcewake_handle(gem_fd);
+	fw = open_forcewake_handle(gem_fd, gt);
 	igt_assert(fw >= 0);
 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
 
@@ -2179,7 +2187,7 @@ igt_main
 	const struct intel_execution_engine2 *e;
 	unsigned int num_engines = 0;
 	const intel_ctx_t *ctx = NULL;
-	int fd = -1;
+	int gt, tmp, fd = -1;
 
 	/**
 	 * All PMU should be accompanied by a test.
@@ -2396,17 +2404,21 @@ igt_main
 	/**
 	 * Test RC6 residency reporting.
 	 */
-	igt_subtest("rc6")
-		test_rc6(fd, 0);
+	igt_subtest_with_dynamic("rc6") {
+		i915_for_each_gt(fd, tmp, gt) {
+			igt_dynamic_f("gt%u", gt)
+				test_rc6(fd, gt, 0);
 
-	igt_subtest("rc6-runtime-pm")
-		test_rc6(fd, TEST_RUNTIME_PM);
+			igt_dynamic_f("runtime-pm-gt%u", gt)
+				test_rc6(fd, gt, TEST_RUNTIME_PM);
 
-	igt_subtest("rc6-runtime-pm-long")
-		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
+			igt_dynamic_f("runtime-pm-long-gt%u", gt)
+				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
+		}
+	}
 
 	igt_subtest("rc6-suspend")
-		test_rc6(fd, TEST_S3);
+		test_rc6(fd, 0, TEST_S3);
 
 	/**
 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
-- 
2.36.1

[igt-dev] [PATCH i-g-t 02/15] perf_pmu: Two new rc6 subtests

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

1.
Keep one tile awake and check rc6 counters on all tiles.

2.
Keep all tiles awake and check rc6 counters on all.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 149 +++++++++++++++++++++++++++++++-----------
 1 file changed, 111 insertions(+), 38 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 86607be4d..44e59aaf7 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -173,6 +173,8 @@ static unsigned int measured_usleep(unsigned int usec)
 #define FLAG_LONG (16)
 #define FLAG_HANG (32)
 #define TEST_S3 (64)
+#define TEST_OTHER (128)
+#define TEST_ALL   (256)
 
 static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
 			       const struct intel_execution_engine2 *e)
@@ -1676,20 +1678,23 @@ test_frequency_idle(int gem_fd)
 		     "Actual frequency should be 0 while parked!\n");
 }
 
-static bool wait_for_rc6(int fd, int timeout)
+static bool wait_for_rc6(int fd, int timeout, unsigned int pmus, unsigned int idx)
 {
 	struct timespec tv = {};
+	uint64_t val[pmus];
 	uint64_t start, now;
 
 	/* First wait for roughly an RC6 Evaluation Interval */
 	usleep(160 * 1000);
 
 	/* Then poll for RC6 to start ticking */
-	now = pmu_read_single(fd);
+	pmu_read_multi(fd, pmus, val);
+	now = val[idx];
 	do {
 		start = now;
 		usleep(5000);
-		now = pmu_read_single(fd);
+		pmu_read_multi(fd, pmus, val);
+		now = val[idx];
 		if (now - start > 1e6)
 			return true;
 	} while (igt_seconds_elapsed(&tv) <= timeout);
@@ -1716,16 +1721,38 @@ static int open_forcewake_handle(int fd, unsigned int gt)
 }
 
 static void
-test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
+test_rc6(int gem_fd, unsigned int gt, unsigned int num_gt, unsigned int flags)
 {
 	int64_t duration_ns = 2e9;
-	uint64_t idle, busy, prev, ts[2];
+	uint64_t idle[16], busy[16], prev[16], ts[2];
+	int fd[num_gt], fw[num_gt], gt_, pmus = 0, test_idx = -1;
 	unsigned long slept;
-	int fd, fw;
+
+	igt_require(!(flags & TEST_OTHER) ||
+		    ((flags & TEST_OTHER) && num_gt > 1));
+
+	igt_require(!(flags & TEST_ALL) ||
+		    ((flags & TEST_ALL) && num_gt > 1));
 
 	gem_quiescent_gpu(gem_fd);
 
-	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
+	fd[0] = -1;
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ != gt && !(flags & TEST_OTHER))
+			continue;
+
+		if (gt_ == gt) {
+			igt_assert(test_idx == -1);
+			test_idx = pmus;
+		}
+
+		fd[pmus] = perf_i915_open_group(gem_fd,
+						__I915_PMU_RC6_RESIDENCY(gt_),
+						fd[0]);
+		igt_skip_on(fd[pmus] < 0 && errno == ENODEV);
+		pmus++;
+	}
+	igt_assert(test_idx >= 0);
 
 	if (flags & TEST_RUNTIME_PM) {
 		drmModeRes *res;
@@ -1746,21 +1773,26 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 		 * drifted to far in advance of real RC6.
 		 */
 		if (flags & FLAG_LONG) {
-			pmu_read_single(fd);
+			pmu_read_multi(fd[0], pmus, idle);
 			sleep(5);
-			pmu_read_single(fd);
+			pmu_read_multi(fd[0], pmus, idle);
 		}
 	}
 
-	igt_require(wait_for_rc6(fd, 1));
+	igt_require(wait_for_rc6(fd[0], 1, pmus, test_idx));
 
 	/* While idle check full RC6. */
-	prev = __pmu_read_single(fd, &ts[0]);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
 	slept = measured_usleep(duration_ns / 1000);
-	idle = __pmu_read_single(fd, &ts[1]);
-
-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
+
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		assert_within_epsilon(idle[gt_] - prev[gt_],
+				      ts[1] - ts[0],
+				      tolerance);
+	}
 
 	if (flags & TEST_S3) {
 		/*
@@ -1773,40 +1805,70 @@ test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
 		 * However, in practice it appears we are not entering rc6
 		 * immediately after resume... A bug?
 		 */
-		prev = __pmu_read_single(fd, &ts[0]);
+		ts[0] = pmu_read_multi(fd[0], pmus, prev);
 		igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
 					      SUSPEND_TEST_NONE);
-		idle = __pmu_read_single(fd, &ts[1]);
-		igt_debug("suspend=%"PRIu64", rc6=%"PRIu64"\n",
-			  ts[1] - ts[0], idle -prev);
-		//assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+		ts[1] = pmu_read_multi(fd[0], pmus, idle);
+		for (gt_ = 0; gt_ < pmus; gt_++) {
+			igt_debug("gt%u: rc6=%"PRIu64", suspend=%"PRIu64"\n",
+				  gt_, idle[gt_] - prev[gt_], ts[1] - ts[0]);
+			// assert_within_epsilon(idle[gt_] - prev[gt_],
+			//		      ts[1] - ts[0], tolerance);
+		}
 	}
 
-	igt_assert(wait_for_rc6(fd, 5));
+	igt_assert(wait_for_rc6(fd[0], 5, pmus, test_idx));
 
-	prev = __pmu_read_single(fd, &ts[0]);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
 	slept = measured_usleep(duration_ns / 1000);
-	idle = __pmu_read_single(fd, &ts[1]);
-
-	igt_debug("slept=%lu perf=%"PRIu64"\n", slept, ts[1] - ts[0]);
-	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
+	ts[1] = pmu_read_multi(fd[0], pmus, idle);
+
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: idle rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, idle[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		assert_within_epsilon(idle[gt_] - prev[gt_],
+				      ts[1] - ts[0],
+				      tolerance);
+	}
 
 	/* Wake up device and check no RC6. */
-	fw = open_forcewake_handle(gem_fd, gt);
-	igt_assert(fw >= 0);
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ != gt && !(flags & TEST_ALL))
+			continue;
+
+		fw[gt_] = open_forcewake_handle(gem_fd, gt_);
+		igt_assert(fw[gt_] >= 0);
+	}
+
 	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
 
-	prev = pmu_read_single(fd);
-	usleep(duration_ns / 1000);
-	busy = pmu_read_single(fd);
+	ts[0] = pmu_read_multi(fd[0], pmus, prev);
+	slept = measured_usleep(duration_ns / 1000);
+	ts[1] = pmu_read_multi(fd[0], pmus, busy);
 
-	close(fw);
-	close(fd);
+	for (gt_ = 0; gt_ < num_gt; gt_++) {
+		if (gt_ == gt || (flags & TEST_ALL))
+			close(fw[gt_]);
+	}
+
+	for (gt_ = 0; gt_ < pmus; gt_++)
+		close(fd[gt_]);
 
 	if (flags & TEST_RUNTIME_PM)
 		igt_restore_runtime_pm();
 
-	assert_within_epsilon(busy - prev, 0.0, tolerance);
+	for (gt_ = 0; gt_ < pmus; gt_++) {
+		igt_debug("gt%u: busy rc6=%"PRIu64", slept=%lu, perf=%"PRIu64"\n",
+			  gt_, busy[gt_] - prev[gt_], slept, ts[1] - ts[0]);
+		if (gt_ == test_idx || (flags & TEST_ALL))
+			assert_within_epsilon(busy[gt_] - prev[gt_],
+					      0.0,
+					      tolerance);
+		else
+			assert_within_epsilon(busy[gt_] - prev[gt_],
+					      ts[1] - ts[0],
+					      tolerance);
+	}
 }
 
 static void
@@ -2188,6 +2250,7 @@ igt_main
 	unsigned int num_engines = 0;
 	const intel_ctx_t *ctx = NULL;
 	int gt, tmp, fd = -1;
+	int num_gt = 0;
 
 	/**
 	 * All PMU should be accompanied by a test.
@@ -2206,6 +2269,9 @@ igt_main
 		for_each_ctx_engine(fd, ctx, e)
 			num_engines++;
 		igt_require(num_engines);
+
+		i915_for_each_gt(fd, tmp, gt)
+			num_gt++;
 	}
 
 	igt_describe("Verify i915 pmu dir exists and read all events");
@@ -2407,18 +2473,25 @@ igt_main
 	igt_subtest_with_dynamic("rc6") {
 		i915_for_each_gt(fd, tmp, gt) {
 			igt_dynamic_f("gt%u", gt)
-				test_rc6(fd, gt, 0);
+				test_rc6(fd, gt, num_gt, 0);
 
 			igt_dynamic_f("runtime-pm-gt%u", gt)
-				test_rc6(fd, gt, TEST_RUNTIME_PM);
+				test_rc6(fd, gt, num_gt, TEST_RUNTIME_PM);
 
 			igt_dynamic_f("runtime-pm-long-gt%u", gt)
-				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
+				test_rc6(fd, gt, num_gt,
+					 TEST_RUNTIME_PM | FLAG_LONG);
+
+			igt_dynamic_f("other-idle-gt%u", gt)
+				test_rc6(fd, gt, num_gt, TEST_OTHER);
 		}
 	}
 
 	igt_subtest("rc6-suspend")
-		test_rc6(fd, 0, TEST_S3);
+		test_rc6(fd, 0, num_gt, TEST_S3);
+
+	igt_subtest("rc6-all-gts")
+		test_rc6(fd, 0, num_gt, TEST_ALL | TEST_OTHER);
 
 	/**
 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
-- 
2.36.1

[igt-dev] [PATCH i-g-t 03/15] perf_pmu: Support multi-tile in frequency subtest

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Simple conversion to run the frequency tests per each tile, as dynamic
subtests, picking the correct engine to stimulate each.

v2: Added new intel_ctx_t implementation for frequency subtest.
v3: Replace distance query with mtl specific static mapping
v4: Break as soon as you find one engine in gt
v5: Use gem_list_engines() and drop unnecessary code (Ashutosh)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Arjun Melkaveri <arjun.melkaveri@intel.com> (v2)
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 128 ++++++++++++++++++++++++++++--------------
 1 file changed, 86 insertions(+), 42 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 44e59aaf7..155fc5f48 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -238,19 +238,6 @@ static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
 	return __spin_sync(fd, ahnd, ctx, e);
 }
 
-static igt_spin_t *spin_sync_flags(int fd, uint64_t ahnd,
-				   const intel_ctx_t *ctx, unsigned int flags)
-{
-	struct intel_execution_engine2 e = { };
-
-	e.class = gem_execbuf_flags_to_engine_class(flags);
-	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
-		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
-	e.flags = flags;
-
-	return spin_sync(fd, ahnd, ctx, &e);
-}
-
 static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
 {
 	if (!spin)
@@ -1539,8 +1526,58 @@ test_interrupts_sync(int gem_fd)
 	igt_assert_lte(target, busy);
 }
 
+static struct i915_engine_class_instance
+find_dword_engine(int i915, const unsigned int gt)
+{
+	struct i915_engine_class_instance *engines, ci = { -1, -1 };
+	unsigned int i, count;
+
+	engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
+	igt_assert(engines);
+
+	for (i = 0; i < count; i++) {
+		if (!gem_class_can_store_dword(i915, engines[i].engine_class))
+			continue;
+
+		ci = engines[i];
+		break;
+	}
+
+	free(engines);
+
+	return ci;
+}
+
+static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
+				const intel_ctx_t **ctx)
+{
+	struct i915_engine_class_instance ci = { -1, -1 };
+	struct intel_execution_engine2 e = { };
+
+	ci = find_dword_engine(i915, gt);
+
+	igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
+
+	if (gem_has_contexts(i915)) {
+		e.class = ci.engine_class;
+		e.instance = ci.engine_instance;
+		e.flags = 0;
+		*ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
+	} else {
+		igt_require(gt == 0); /* Impossible anyway. */
+		e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
+		e.instance = 0;
+		e.flags = I915_EXEC_DEFAULT;
+		*ctx = intel_ctx_0(i915);
+	}
+
+	igt_debug("Using engine %u:%u\n", e.class, e.instance);
+
+	return spin_sync(i915, ahnd, *ctx, &e);
+}
+
 static void
-test_frequency(int gem_fd)
+test_frequency(int gem_fd, unsigned int gt)
 {
 	uint32_t min_freq, max_freq, boost_freq;
 	uint64_t val[2], start[2], slept;
@@ -1548,13 +1585,14 @@ test_frequency(int gem_fd)
 	igt_spin_t *spin;
 	int fd[2], sysfs;
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, 0);
+	const intel_ctx_t *ctx;
 
-	sysfs = igt_sysfs_open(gem_fd);
+	sysfs = igt_sysfs_gt_open(gem_fd, gt);
 	igt_require(sysfs >= 0);
 
-	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
-	max_freq = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
-	boost_freq = igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz");
+	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
+	max_freq = igt_sysfs_get_u32(sysfs, "rps_RP0_freq_mhz");
+	boost_freq = igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz");
 	igt_info("Frequency: min=%u, max=%u, boost=%u MHz\n",
 		 min_freq, max_freq, boost_freq);
 	igt_require(min_freq > 0 && max_freq > 0 && boost_freq > 0);
@@ -1567,15 +1605,15 @@ test_frequency(int gem_fd)
 	/*
 	 * Set GPU to min frequency and read PMU counters.
 	 */
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == min_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == min_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", min_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == min_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", min_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == min_freq);
 
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
-	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
+	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
 
 	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1584,6 +1622,7 @@ test_frequency(int gem_fd)
 	min[0] = 1e9*(val[0] - start[0]) / slept;
 	min[1] = 1e9*(val[1] - start[1]) / slept;
 
+	intel_ctx_destroy(gem_fd, ctx);
 	igt_spin_free(gem_fd, spin);
 	gem_quiescent_gpu(gem_fd); /* Don't leak busy bo into the next phase */
 
@@ -1592,16 +1631,16 @@ test_frequency(int gem_fd)
 	/*
 	 * Set GPU to max frequency and read PMU counters.
 	 */
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == max_freq);
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", boost_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == boost_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", max_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == max_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", boost_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == boost_freq);
 
-	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max_freq));
-	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
+	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", max_freq));
+	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == max_freq);
 
 	gem_quiescent_gpu(gem_fd);
-	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
+	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
 
 	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1610,16 +1649,17 @@ test_frequency(int gem_fd)
 	max[0] = 1e9*(val[0] - start[0]) / slept;
 	max[1] = 1e9*(val[1] - start[1]) / slept;
 
+	intel_ctx_destroy(gem_fd, ctx);
 	igt_spin_free(gem_fd, spin);
 	gem_quiescent_gpu(gem_fd);
 
 	/*
 	 * Restore min/max.
 	 */
-	igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq);
-	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
+	igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq);
+	if (igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") != min_freq)
 		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
-			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
+			 min_freq, igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz"));
 	close(fd[0]);
 	close(fd[1]);
 	put_ahnd(ahnd);
@@ -1638,17 +1678,17 @@ test_frequency(int gem_fd)
 }
 
 static void
-test_frequency_idle(int gem_fd)
+test_frequency_idle(int gem_fd, unsigned int gt)
 {
 	uint32_t min_freq;
 	uint64_t val[2], start[2], slept;
 	double idle[2];
 	int fd[2], sysfs;
 
-	sysfs = igt_sysfs_open(gem_fd);
+	sysfs = igt_sysfs_gt_open(gem_fd, gt);
 	igt_require(sysfs >= 0);
 
-	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
+	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
 	close(sysfs);
 
 	/* While parked, our convention is to report the GPU at 0Hz */
@@ -2453,10 +2493,14 @@ igt_main
 	/**
 	 * Test GPU frequency.
 	 */
-	igt_subtest("frequency")
-		test_frequency(fd);
-	igt_subtest("frequency-idle")
-		test_frequency_idle(fd);
+	igt_subtest_with_dynamic("frequency") {
+		i915_for_each_gt(fd, tmp, gt) {
+			igt_dynamic_f("gt%u", gt)
+				test_frequency(fd, gt);
+			igt_dynamic_f("idle-gt%u", gt)
+				test_frequency_idle(fd, gt);
+		}
+	}
 
 	/**
 	 * Test interrupt count reporting.
-- 
2.36.1

[igt-dev] [PATCH i-g-t 04/15] perf_pmu: Quiesce GPU if measuring idle busyness without spinner

[Umesh Nerlige Ramappa]

The assumption in some tests is that the engines are not busy if no
spinners are being run. This is not true in some cases where we see
that the render is busy at the start of the test. Quiesce GPU to wait
for such work to complete before checking for idle busyness.

v2: Move gem_quiescent_gpu to beginning of test (Tvrtko)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/perf_pmu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 155fc5f48..38bdee650 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -279,6 +279,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
 	int fd;
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
@@ -639,6 +640,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
 	int fd[2];
 	uint64_t ahnd = get_reloc_ahnd(gem_fd, ctx->id);
 
+	gem_quiescent_gpu(gem_fd);
 	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
 			   -1);
 	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
-- 
2.36.1

[igt-dev] [PATCH i-g-t 05/15] perf_pmu: Use correct pmu config for multi-tile

[Umesh Nerlige Ramappa]

From: Riana Tauro <riana.tauro@intel.com>

Use the correct perf_pmu config for actual and requested frequency in
multi-tile frequency test.

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/perf_pmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 38bdee650..4f4a616eb 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -1601,8 +1601,8 @@ test_frequency(int gem_fd, unsigned int gt)
 	igt_require(max_freq > min_freq);
 	igt_require(boost_freq > min_freq);
 
-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
 
 	/*
 	 * Set GPU to min frequency and read PMU counters.
@@ -1695,8 +1695,8 @@ test_frequency_idle(int gem_fd, unsigned int gt)
 
 	/* While parked, our convention is to report the GPU at 0Hz */
 
-	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
+	fd[0] = open_group(gem_fd, __I915_PMU_REQUESTED_FREQUENCY(gt), -1);
+	fd[1] = open_group(gem_fd, __I915_PMU_ACTUAL_FREQUENCY(gt), fd[0]);
 
 	gem_quiescent_gpu(gem_fd); /* Be idle! */
 	measured_usleep(2000); /* Wait for timers to cease */
-- 
2.36.1

[igt-dev] [PATCH i-g-t 06/15] intel_gpu_top: Add an array of freq and rc6 counters

[Umesh Nerlige Ramappa]

Since rc6 and frequency events are specific to a tile in multi-tile platforms,
prepare support for multi-tile by storing these events in an array.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index b6827b3de..3d21f25bd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -87,6 +87,7 @@ struct engine_class {
 	unsigned int num_engines;
 };
 
+#define MAX_GTS 4
 struct engines {
 	unsigned int num_engines;
 	unsigned int num_classes;
@@ -106,9 +107,12 @@ struct engines {
 	unsigned int num_imc;
 
 	struct pmu_counter freq_req;
+	struct pmu_counter freq_req_gt[MAX_GTS];
 	struct pmu_counter freq_act;
+	struct pmu_counter freq_act_gt[MAX_GTS];
 	struct pmu_counter irq;
 	struct pmu_counter rc6;
+	struct pmu_counter rc6_gt[MAX_GTS];
 
 	bool discrete;
 	char *device;
-- 
2.36.1

[igt-dev] [PATCH i-g-t 07/15] intel_gpu_top: Determine number of tiles

[Umesh Nerlige Ramappa]

Find out how many tiles are present in the platforms for multi-tile support.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 3d21f25bd..695f57526 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -117,6 +117,8 @@ struct engines {
 	bool discrete;
 	char *device;
 
+	int num_gts;
+
 	/* Do not edit below this line.
 	 * This structure is reallocated every time a new engine is
 	 * found and size is increased by sizeof (engine).
@@ -533,6 +535,25 @@ static void imc_reads_open(struct pmu_counter *pmu, struct engines *engines)
 	imc_open(pmu, "data_reads", engines);
 }
 
+static int get_num_gts(uint64_t type)
+{
+	int fd, cnt;
+
+	errno = 0;
+	for (cnt = 0; cnt < MAX_GTS; cnt++) {
+		fd = igt_perf_open(type, __I915_PMU_REQUESTED_FREQUENCY(cnt));
+		if (fd < 0)
+			break;
+
+		close(fd);
+	}
+	assert(!errno || errno == ENOENT);
+	assert(cnt > 0);
+	errno = 0;
+
+	return cnt;
+}
+
 static int pmu_init(struct engines *engines)
 {
 	unsigned int i;
@@ -541,6 +562,7 @@ static int pmu_init(struct engines *engines)
 
 	engines->fd = -1;
 	engines->num_counters = 0;
+	engines->num_gts = get_num_gts(type);
 
 	engines->irq.config = I915_PMU_INTERRUPTS;
 	fd = _open_pmu(type, engines->num_counters, &engines->irq, engines->fd);
-- 
2.36.1

[igt-dev] [PATCH i-g-t 08/15] intel_gpu_top: Capture freq and rc6 counters from each gt

[Umesh Nerlige Ramappa]

Loop through available gts and store the frequency and rc6 counters.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 695f57526..b0c177329 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -578,6 +578,17 @@ static int pmu_init(struct engines *engines)
 	engines->rc6.config = I915_PMU_RC6_RESIDENCY;
 	_open_pmu(type, engines->num_counters, &engines->rc6, engines->fd);
 
+	for (i = 0; i < engines->num_gts; i++) {
+		engines->freq_req_gt[i].config = __I915_PMU_REQUESTED_FREQUENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->freq_req_gt[i], engines->fd);
+
+		engines->freq_act_gt[i].config = __I915_PMU_ACTUAL_FREQUENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->freq_act_gt[i], engines->fd);
+
+		engines->rc6_gt[i].config = __I915_PMU_RC6_RESIDENCY(i);
+		_open_pmu(type, engines->num_counters, &engines->rc6_gt[i], engines->fd);
+	}
+
 	for (i = 0; i < engines->num_engines; i++) {
 		struct engine *engine = engine_ptr(engines, i);
 		struct {
@@ -679,6 +690,12 @@ static void pmu_sample(struct engines *engines)
 	engines->ts.prev = engines->ts.cur;
 	engines->ts.cur = pmu_read_multi(engines->fd, num_val, val);
 
+	for (i = 0; i < engines->num_gts; i++) {
+		update_sample(&engines->freq_req_gt[i], val);
+		update_sample(&engines->freq_act_gt[i], val);
+		update_sample(&engines->rc6_gt[i], val);
+	}
+
 	update_sample(&engines->freq_req, val);
 	update_sample(&engines->freq_act, val);
 	update_sample(&engines->irq, val);
-- 
2.36.1

[igt-dev] [PATCH i-g-t 09/15] intel_gpu_top: Switch pmu_counter to use aggregated values

[Umesh Nerlige Ramappa]

Aggregate gt specific values for freq and rc6 counters.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 49 +++++++++++++++++++++++++++++++++----------
 1 file changed, 38 insertions(+), 11 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index b0c177329..d995c39b9 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -554,6 +554,26 @@ static int get_num_gts(uint64_t type)
 	return cnt;
 }
 
+static void init_aggregate_counters(struct engines *engines)
+{
+	struct pmu_counter *pmu;
+
+	pmu = &engines->freq_req;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_REQUESTED_FREQUENCY;
+	pmu->present = true;
+
+	pmu = &engines->freq_act;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_ACTUAL_FREQUENCY;
+	pmu->present = true;
+
+	pmu = &engines->rc6;
+	pmu->type = igt_perf_type_id(engines->device);
+	pmu->config = I915_PMU_RC6_RESIDENCY;
+	pmu->present = true;
+}
+
 static int pmu_init(struct engines *engines)
 {
 	unsigned int i;
@@ -569,14 +589,7 @@ static int pmu_init(struct engines *engines)
 	if (fd < 0)
 		return -1;
 
-	engines->freq_req.config = I915_PMU_REQUESTED_FREQUENCY;
-	_open_pmu(type, engines->num_counters, &engines->freq_req, engines->fd);
-
-	engines->freq_act.config = I915_PMU_ACTUAL_FREQUENCY;
-	_open_pmu(type, engines->num_counters, &engines->freq_act, engines->fd);
-
-	engines->rc6.config = I915_PMU_RC6_RESIDENCY;
-	_open_pmu(type, engines->num_counters, &engines->rc6, engines->fd);
+	init_aggregate_counters(engines);
 
 	for (i = 0; i < engines->num_gts; i++) {
 		engines->freq_req_gt[i].config = __I915_PMU_REQUESTED_FREQUENCY(i);
@@ -692,14 +705,28 @@ static void pmu_sample(struct engines *engines)
 
 	for (i = 0; i < engines->num_gts; i++) {
 		update_sample(&engines->freq_req_gt[i], val);
+		engines->freq_req.val.cur += engines->freq_req_gt[i].val.cur;
+		engines->freq_req.val.prev += engines->freq_req_gt[i].val.prev;
+
 		update_sample(&engines->freq_act_gt[i], val);
+		engines->freq_act.val.cur += engines->freq_act_gt[i].val.cur;
+		engines->freq_act.val.prev += engines->freq_act_gt[i].val.prev;
+
 		update_sample(&engines->rc6_gt[i], val);
+		engines->rc6.val.cur += engines->rc6_gt[i].val.cur;
+		engines->rc6.val.prev += engines->rc6_gt[i].val.prev;
 	}
 
-	update_sample(&engines->freq_req, val);
-	update_sample(&engines->freq_act, val);
+	engines->freq_req.val.cur /= engines->num_gts;
+	engines->freq_req.val.prev /= engines->num_gts;
+
+	engines->freq_act.val.cur /= engines->num_gts;
+	engines->freq_act.val.prev /= engines->num_gts;
+
+	engines->rc6.val.cur /= engines->num_gts;
+	engines->rc6.val.prev /= engines->num_gts;
+
 	update_sample(&engines->irq, val);
-	update_sample(&engines->rc6, val);
 
 	for (i = 0; i < engines->num_engines; i++) {
 		struct engine *engine = engine_ptr(engines, i);
-- 
2.36.1

[igt-dev] [PATCH i-g-t 10/15] intel_gpu_top: Add definitions for gt-specific items and groups

[Umesh Nerlige Ramappa]

Prepare to pass a modified groups array to print_groups by defining
separate items and groups for each gt.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 44 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index d995c39b9..63ce9fade 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1854,6 +1854,30 @@ print_header(const struct igt_device_card *card,
 		.display_name = "Freq MHz",
 		.items = freq_items,
 	};
+	struct cnt_item freq_items_gt[] = {
+		{ &engines->freq_req_gt[0], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[0], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[1], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[1], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[2], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[2], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+		{ &engines->freq_req_gt[3], 6, 0, 1.0, t, 1, "requested", "req" },
+		{ &engines->freq_act_gt[3], 6, 0, 1.0, t, 1, "actual", "act" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "MHz" },
+		{ },
+	};
+	struct cnt_group freq_group_gt[MAX_GTS] = {
+		{ .name = "frequency-gt0", .display_name = "Freq GT0 MHz", .items = &freq_items_gt[0] },
+		{ .name = "frequency-gt1", .display_name = "Freq GT1 MHz", .items = &freq_items_gt[4] },
+		{ .name = "frequency-gt2", .display_name = "Freq GT2 MHz", .items = &freq_items_gt[8] },
+		{ .name = "frequency-gt3", .display_name = "Freq GT3 MHz", .items = &freq_items_gt[12] },
+	};
 	struct cnt_item irq_items[] = {
 		{ &engines->irq, 8, 0, 1.0, t, 1, "count", "/s" },
 		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "irq/s" },
@@ -1874,6 +1898,26 @@ print_header(const struct igt_device_card *card,
 		.display_name = "RC6",
 		.items = rc6_items,
 	};
+	struct cnt_item rc6_items_gt[] = {
+		{ &engines->rc6_gt[0], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[1], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[2], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+		{ &engines->rc6_gt[3], 8, 0, 1e9, t, 100, "value", "%" },
+		{ NULL, 0, 0, 0.0, 0.0, 0.0, "unit", "%" },
+		{ },
+	};
+	struct cnt_group rc6_group_gt[MAX_GTS] = {
+		{ .name = "rc6-gt0", .display_name = "RC6 GT0", .items = &rc6_items_gt[0] },
+		{ .name = "rc6-gt1", .display_name = "RC6 GT1", .items = &rc6_items_gt[3] },
+		{ .name = "rc6-gt2", .display_name = "RC6 GT2", .items = &rc6_items_gt[6] },
+		{ .name = "rc6-gt3", .display_name = "RC6 GT3", .items = &rc6_items_gt[9] },
+	};
 	struct cnt_item power_items[] = {
 		{ &engines->r_gpu, 4, 2, 1.0, t, engines->r_gpu.scale, "GPU", "gpu" },
 		{ &engines->r_pkg, 4, 2, 1.0, t, engines->r_pkg.scale, "Package", "pkg" },
-- 
2.36.1

[igt-dev] [PATCH i-g-t 11/15] intel_gpu_top: Bump up size of groups to accomodate multi-gt

[Umesh Nerlige Ramappa]

Create more space in groups to add gt specific freq and rc6 groups.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 63ce9fade..87d869802 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1929,7 +1929,13 @@ print_header(const struct igt_device_card *card,
 		.display_name = "Power W",
 		.items = power_items,
 	};
-	struct cnt_group *groups[] = {
+	/*
+	 * Array size calculation:
+	 * One group each for period, irq, power, NULL = 4
+	 * One group per gt for freq = MAX_GTS
+	 * One group per gt for rc6  = MAX_GTS
+	 */
+	struct cnt_group *groups[4 + MAX_GTS + MAX_GTS] = {
 		&period_group,
 		&freq_group,
 		&irq_group,
-- 
2.36.1

[igt-dev] [PATCH i-g-t 12/15] intel_gpu_top: Increase visibility for class_view

[Umesh Nerlige Ramappa]

Some future changes may access class_view before it's declared, so move
it to top

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 87d869802..4d0aeee16 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -129,6 +129,7 @@ struct engines {
 };
 
 static struct termios termios_orig;
+static bool class_view;
 
 __attribute__((format(scanf,3,4)))
 static int igt_sysfs_scanf(int dir, const char *attr, const char *fmt, ...)
@@ -2054,8 +2055,6 @@ print_imc(struct engines *engines, double t, int lines, int con_w, int con_h)
 	return lines;
 }
 
-static bool class_view;
-
 static int
 print_engines_header(struct engines *engines, double t,
 		     int lines, int con_w, int con_h)
-- 
2.36.1

[igt-dev] [PATCH i-g-t 13/15] intel_gpu_top: Show gt specific values if requested

[Umesh Nerlige Ramappa]

On multi-gt platforms, the aggregate values are displayed as default. If
user passes -p (physical) option for these platforms, show gt specific
counter values.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 4d0aeee16..8bcca67a6 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1944,6 +1944,26 @@ print_header(const struct igt_device_card *card,
 		&power_group,
 		NULL
 	};
+	int i;
+
+	/*
+	 * If we have multi-gt and the user has specified -p options, show gt
+	 * specific values.
+	 */
+	if (!class_view && engines->num_gts > 1) {
+		int j = 0;
+
+		groups[j++] = &period_group;
+		for (i = 0; i < engines->num_gts; i++)
+			groups[j++] = &freq_group_gt[i];
+
+		groups[j++] = &irq_group;
+		for (i = 0; i < engines->num_gts; i++)
+			groups[j++] = &rc6_group_gt[i];
+
+		groups[j++] = &power_group;
+		groups[j++] = NULL;
+	}
 
 	if (output_mode != JSON)
 		memmove(&groups[0], &groups[1],
-- 
2.36.1

[igt-dev] [PATCH i-g-t 14/15] intel_gpu_top: Reduce one level of indent

[Umesh Nerlige Ramappa]

Prepare to display gt specific items in INTERACTIVE mode with the -p
option. An additional for loop will push code more towards right, so
reduce one level of indent.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 74 ++++++++++++++++++++++---------------------
 1 file changed, 38 insertions(+), 36 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 8bcca67a6..0acc81e9e 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1944,7 +1944,7 @@ print_header(const struct igt_device_card *card,
 		&power_group,
 		NULL
 	};
-	int i;
+	int rem, i;
 
 	/*
 	 * If we have multi-gt and the user has specified -p options, show gt
@@ -1971,51 +1971,53 @@ print_header(const struct igt_device_card *card,
 
 	*consumed = print_groups(groups);
 
-	if (output_mode == INTERACTIVE) {
-		int rem = con_w;
+	if (output_mode != INTERACTIVE)
+		return lines;
 
-		printf("\033[H\033[J");
+	/* INTERACTIVE MODE */
+	rem = con_w;
 
-		lines = print_header_token(NULL, lines, con_w, con_h, &rem,
-					   "intel-gpu-top:");
+	printf("\033[H\033[J");
 
-		lines = print_header_token(" ", lines, con_w, con_h, &rem,
-					   "%s", codename);
+	lines = print_header_token(NULL, lines, con_w, con_h, &rem,
+				   "intel-gpu-top:");
 
-		lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
-					   "%s", card->card);
+	lines = print_header_token(" ", lines, con_w, con_h, &rem,
+				   "%s", codename);
 
-		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
-					   "%s/%s MHz",
-					   freq_items[1].buf,
-					   freq_items[0].buf);
+	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
+				   "%s", card->card);
 
-		lines = print_header_token("; ", lines, con_w, con_h, &rem,
-					   "%s%% RC6",
-					   rc6_items[0].buf);
+	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
+				   "%s/%s MHz",
+				   freq_items[1].buf,
+				   freq_items[0].buf);
 
-		if (engines->r_gpu.present) {
-			lines = print_header_token("; ", lines, con_w, con_h,
-						   &rem,
-						   "%s/%s W",
-						   power_items[0].buf,
-						   power_items[1].buf);
-		}
+	lines = print_header_token("; ", lines, con_w, con_h, &rem,
+				   "%s%% RC6",
+				   rc6_items[0].buf);
 
-		lines = print_header_token("; ", lines, con_w, con_h, &rem,
-					   "%s irqs/s",
-					   irq_items[0].buf);
+	if (engines->r_gpu.present) {
+		lines = print_header_token("; ", lines, con_w, con_h,
+					   &rem,
+					   "%s/%s W",
+					   power_items[0].buf,
+					   power_items[1].buf);
+	}
 
-		if (lines++ < con_h)
-			printf("\n");
+	lines = print_header_token("; ", lines, con_w, con_h, &rem,
+				   "%s irqs/s",
+				   irq_items[0].buf);
 
-		if (lines++ < con_h) {
-			if (header_msg) {
-				printf(" >>> %s\n", header_msg);
-				header_msg = NULL;
-			} else {
-				printf("\n");
-			}
+	if (lines++ < con_h)
+		printf("\n");
+
+	if (lines++ < con_h) {
+		if (header_msg) {
+			printf(" >>> %s\n", header_msg);
+			header_msg = NULL;
+		} else {
+			printf("\n");
 		}
 	}
 
-- 
2.36.1

[igt-dev] [PATCH i-g-t 15/15] intel_gpu_top: Add gt specific values to header in interactive mode

[Umesh Nerlige Ramappa]

If -p options is specified in INTERACTIVE mode, show the gt specific
values.

v2: Reformat GT info for INTERACTIVE mode (Tvrtko)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tools/intel_gpu_top.c | 33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 0acc81e9e..ddaf128c0 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -1988,14 +1988,31 @@ print_header(const struct igt_device_card *card,
 	lines = print_header_token(" @ ", lines, con_w, con_h, &rem,
 				   "%s", card->card);
 
-	lines = print_header_token(" - ", lines, con_w, con_h, &rem,
-				   "%s/%s MHz",
-				   freq_items[1].buf,
-				   freq_items[0].buf);
-
-	lines = print_header_token("; ", lines, con_w, con_h, &rem,
-				   "%s%% RC6",
-				   rc6_items[0].buf);
+	if (class_view || engines->num_gts == 1) {
+		lines = print_header_token(" - ", lines, con_w, con_h, &rem,
+					   "%s/%s MHz",
+					   freq_items[1].buf,
+					   freq_items[0].buf);
+
+		lines = print_header_token("; ", lines, con_w, con_h, &rem,
+					   "%s%% RC6",
+					   rc6_items[0].buf);
+	} else {
+		for (i = 0; i < engines->num_gts; i++) {
+			const char *cont = !i ? " - ": "; ";
+
+			lines = print_header_token(cont, lines, con_w, con_h, &rem,
+						   "%s/%s MHz GT%d",
+						   freq_items_gt[i * 4 + 1].buf,
+						   freq_items_gt[i * 4 + 0].buf,
+						   i);
+
+			lines = print_header_token("; ", lines, con_w, con_h, &rem,
+						   "%s%% RC6 GT%d",
+						   rc6_items_gt[i * 3].buf,
+						   i);
+		}
+	}
 
 	if (engines->r_gpu.present) {
 		lines = print_header_token("; ", lines, con_w, con_h,
-- 
2.36.1

Re: [igt-dev] [PATCH i-g-t 01/15] perf_pmu: Support multi-tile in rc6 subtest

[Dixit, Ashutosh]

On Fri, 12 May 2023 19:22:20 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Teach test how to wake up a particular tile and make it iterate all of
> them using dynamic subtests.
>
> v2: Finalize SHIFT to 60. Drop FIXME from i915_drm.h
> v3: (Ashutosh)
> - Use i915_for_each_gt
> - Move uapi to i915_drm_local.h

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
x
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  lib/i915/i915_drm_local.h | 15 +++++++++++++++
>  tests/i915/perf_pmu.c     | 34 +++++++++++++++++++++++-----------
>  2 files changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
> index af0176500..bb2ebef38 100644
> --- a/lib/i915/i915_drm_local.h
> +++ b/lib/i915/i915_drm_local.h
> @@ -26,6 +26,21 @@ extern "C" {
>  #define DRM_I915_PERF_PROP_OA_ENGINE_CLASS	9
>  #define DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE	10
>
> +/*
> + * Top 4 bits of every non-engine counter are GT id.
> + */
> +#define __I915_PMU_GT_SHIFT (60)
> +
> +#define ___I915_PMU_OTHER(gt, x) \
> +	(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
> +	((__u64)(gt) << __I915_PMU_GT_SHIFT))
> +
> +#define __I915_PMU_ACTUAL_FREQUENCY(gt)		___I915_PMU_OTHER(gt, 0)
> +#define __I915_PMU_REQUESTED_FREQUENCY(gt)	___I915_PMU_OTHER(gt, 1)
> +#define __I915_PMU_INTERRUPTS(gt)		___I915_PMU_OTHER(gt, 2)
> +#define __I915_PMU_RC6_RESIDENCY(gt)		___I915_PMU_OTHER(gt, 3)
> +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)	___I915_PMU_OTHER(gt, 4)
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index c5f083bbd..86607be4d 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -1707,8 +1707,16 @@ static bool wait_for_suspended(int gem_fd)
>	return suspended;
>  }
>
> +static int open_forcewake_handle(int fd, unsigned int gt)
> +{
> +	if (getenv("IGT_NO_FORCEWAKE"))
> +		return -1;
> +
> +	return igt_debugfs_gt_open(fd, gt, "forcewake_user", O_WRONLY);
> +}
> +
>  static void
> -test_rc6(int gem_fd, unsigned int flags)
> +test_rc6(int gem_fd, unsigned int gt, unsigned int flags)
>  {
>	int64_t duration_ns = 2e9;
>	uint64_t idle, busy, prev, ts[2];
> @@ -1717,7 +1725,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
>	gem_quiescent_gpu(gem_fd);
>
> -	fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
> +	fd = open_pmu(gem_fd, __I915_PMU_RC6_RESIDENCY(gt));
>
>	if (flags & TEST_RUNTIME_PM) {
>		drmModeRes *res;
> @@ -1784,7 +1792,7 @@ test_rc6(int gem_fd, unsigned int flags)
>	assert_within_epsilon(idle - prev, ts[1] - ts[0], tolerance);
>
>	/* Wake up device and check no RC6. */
> -	fw = igt_open_forcewake_handle(gem_fd);
> +	fw = open_forcewake_handle(gem_fd, gt);
>	igt_assert(fw >= 0);
>	usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
>
> @@ -2179,7 +2187,7 @@ igt_main
>	const struct intel_execution_engine2 *e;
>	unsigned int num_engines = 0;
>	const intel_ctx_t *ctx = NULL;
> -	int fd = -1;
> +	int gt, tmp, fd = -1;
>
>	/**
>	 * All PMU should be accompanied by a test.
> @@ -2396,17 +2404,21 @@ igt_main
>	/**
>	 * Test RC6 residency reporting.
>	 */
> -	igt_subtest("rc6")
> -		test_rc6(fd, 0);
> +	igt_subtest_with_dynamic("rc6") {
> +		i915_for_each_gt(fd, tmp, gt) {
> +			igt_dynamic_f("gt%u", gt)
> +				test_rc6(fd, gt, 0);
>
> -	igt_subtest("rc6-runtime-pm")
> -		test_rc6(fd, TEST_RUNTIME_PM);
> +			igt_dynamic_f("runtime-pm-gt%u", gt)
> +				test_rc6(fd, gt, TEST_RUNTIME_PM);
>
> -	igt_subtest("rc6-runtime-pm-long")
> -		test_rc6(fd, TEST_RUNTIME_PM | FLAG_LONG);
> +			igt_dynamic_f("runtime-pm-long-gt%u", gt)
> +				test_rc6(fd, gt, TEST_RUNTIME_PM | FLAG_LONG);
> +		}
> +	}
>
>	igt_subtest("rc6-suspend")
> -		test_rc6(fd, TEST_S3);
> +		test_rc6(fd, 0, TEST_S3);
>
>	/**
>	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
> --
> 2.36.1
>

Re: [igt-dev] [PATCH i-g-t 03/15] perf_pmu: Support multi-tile in frequency subtest

[Dixit, Ashutosh]

On Fri, 12 May 2023 19:22:22 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Simple conversion to run the frequency tests per each tile, as dynamic
> subtests, picking the correct engine to stimulate each.
>
> v2: Added new intel_ctx_t implementation for frequency subtest.
> v3: Replace distance query with mtl specific static mapping
> v4: Break as soon as you find one engine in gt
> v5: Use gem_list_engines() and drop unnecessary code (Ashutosh)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Arjun Melkaveri <arjun.melkaveri@intel.com> (v2)
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/perf_pmu.c | 128 ++++++++++++++++++++++++++++--------------
>  1 file changed, 86 insertions(+), 42 deletions(-)
>
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index 44e59aaf7..155fc5f48 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -238,19 +238,6 @@ static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>	return __spin_sync(fd, ahnd, ctx, e);
>  }
>
> -static igt_spin_t *spin_sync_flags(int fd, uint64_t ahnd,
> -				   const intel_ctx_t *ctx, unsigned int flags)
> -{
> -	struct intel_execution_engine2 e = { };
> -
> -	e.class = gem_execbuf_flags_to_engine_class(flags);
> -	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
> -		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
> -	e.flags = flags;
> -
> -	return spin_sync(fd, ahnd, ctx, &e);
> -}
> -
>  static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>  {
>	if (!spin)
> @@ -1539,8 +1526,58 @@ test_interrupts_sync(int gem_fd)
>	igt_assert_lte(target, busy);
>  }
>
> +static struct i915_engine_class_instance
> +find_dword_engine(int i915, const unsigned int gt)
> +{
> +	struct i915_engine_class_instance *engines, ci = { -1, -1 };
> +	unsigned int i, count;
> +
> +	engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
> +	igt_assert(engines);
> +
> +	for (i = 0; i < count; i++) {
> +		if (!gem_class_can_store_dword(i915, engines[i].engine_class))
> +			continue;
> +
> +		ci = engines[i];
> +		break;
> +	}
> +
> +	free(engines);
> +
> +	return ci;
> +}
> +
> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> +				const intel_ctx_t **ctx)
> +{
> +	struct i915_engine_class_instance ci = { -1, -1 };
> +	struct intel_execution_engine2 e = { };
> +
> +	ci = find_dword_engine(i915, gt);
> +
> +	igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
> +
> +	if (gem_has_contexts(i915)) {
> +		e.class = ci.engine_class;
> +		e.instance = ci.engine_instance;
> +		e.flags = 0;
> +		*ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
> +	} else {
> +		igt_require(gt == 0); /* Impossible anyway. */
> +		e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
> +		e.instance = 0;
> +		e.flags = I915_EXEC_DEFAULT;
> +		*ctx = intel_ctx_0(i915);
> +	}
> +
> +	igt_debug("Using engine %u:%u\n", e.class, e.instance);
> +
> +	return spin_sync(i915, ahnd, *ctx, &e);
> +}
> +
>  static void
> -test_frequency(int gem_fd)
> +test_frequency(int gem_fd, unsigned int gt)
>  {
>	uint32_t min_freq, max_freq, boost_freq;
>	uint64_t val[2], start[2], slept;
> @@ -1548,13 +1585,14 @@ test_frequency(int gem_fd)
>	igt_spin_t *spin;
>	int fd[2], sysfs;
>	uint64_t ahnd = get_reloc_ahnd(gem_fd, 0);
> +	const intel_ctx_t *ctx;
>
> -	sysfs = igt_sysfs_open(gem_fd);
> +	sysfs = igt_sysfs_gt_open(gem_fd, gt);
>	igt_require(sysfs >= 0);
>
> -	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
> -	max_freq = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
> -	boost_freq = igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz");
> +	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
> +	max_freq = igt_sysfs_get_u32(sysfs, "rps_RP0_freq_mhz");
> +	boost_freq = igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz");
>	igt_info("Frequency: min=%u, max=%u, boost=%u MHz\n",
>		 min_freq, max_freq, boost_freq);
>	igt_require(min_freq > 0 && max_freq > 0 && boost_freq > 0);
> @@ -1567,15 +1605,15 @@ test_frequency(int gem_fd)
>	/*
>	 * Set GPU to min frequency and read PMU counters.
>	 */
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == min_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == min_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", min_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == min_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", min_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == min_freq);
>
>	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
> -	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
> +	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
>
>	slept = pmu_read_multi(fd[0], 2, start);
>	measured_usleep(batch_duration_ns / 1000);
> @@ -1584,6 +1622,7 @@ test_frequency(int gem_fd)
>	min[0] = 1e9*(val[0] - start[0]) / slept;
>	min[1] = 1e9*(val[1] - start[1]) / slept;
>
> +	intel_ctx_destroy(gem_fd, ctx);
>	igt_spin_free(gem_fd, spin);
>	gem_quiescent_gpu(gem_fd); /* Don't leak busy bo into the next phase */
>
> @@ -1592,16 +1631,16 @@ test_frequency(int gem_fd)
>	/*
>	 * Set GPU to max frequency and read PMU counters.
>	 */
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == max_freq);
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", boost_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == boost_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_max_freq_mhz", max_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_max_freq_mhz") == max_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_boost_freq_mhz", boost_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_boost_freq_mhz") == boost_freq);
>
> -	igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max_freq));
> -	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
> +	igt_require(igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", max_freq));
> +	igt_require(igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") == max_freq);
>
>	gem_quiescent_gpu(gem_fd);
> -	spin = spin_sync_flags(gem_fd, ahnd, 0, I915_EXEC_DEFAULT);
> +	spin = spin_sync_gt(gem_fd, ahnd, gt, &ctx);
>
>	slept = pmu_read_multi(fd[0], 2, start);
>	measured_usleep(batch_duration_ns / 1000);
> @@ -1610,16 +1649,17 @@ test_frequency(int gem_fd)
>	max[0] = 1e9*(val[0] - start[0]) / slept;
>	max[1] = 1e9*(val[1] - start[1]) / slept;
>
> +	intel_ctx_destroy(gem_fd, ctx);
>	igt_spin_free(gem_fd, spin);
>	gem_quiescent_gpu(gem_fd);
>
>	/*
>	 * Restore min/max.
>	 */
> -	igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq);
> -	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
> +	igt_sysfs_set_u32(sysfs, "rps_min_freq_mhz", min_freq);
> +	if (igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz") != min_freq)
>		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
> -			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
> +			 min_freq, igt_sysfs_get_u32(sysfs, "rps_min_freq_mhz"));
>	close(fd[0]);
>	close(fd[1]);
>	put_ahnd(ahnd);
> @@ -1638,17 +1678,17 @@ test_frequency(int gem_fd)
>  }
>
>  static void
> -test_frequency_idle(int gem_fd)
> +test_frequency_idle(int gem_fd, unsigned int gt)
>  {
>	uint32_t min_freq;
>	uint64_t val[2], start[2], slept;
>	double idle[2];
>	int fd[2], sysfs;
>
> -	sysfs = igt_sysfs_open(gem_fd);
> +	sysfs = igt_sysfs_gt_open(gem_fd, gt);
>	igt_require(sysfs >= 0);
>
> -	min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
> +	min_freq = igt_sysfs_get_u32(sysfs, "rps_RPn_freq_mhz");
>	close(sysfs);
>
>	/* While parked, our convention is to report the GPU at 0Hz */
> @@ -2453,10 +2493,14 @@ igt_main
>	/**
>	 * Test GPU frequency.
>	 */
> -	igt_subtest("frequency")
> -		test_frequency(fd);
> -	igt_subtest("frequency-idle")
> -		test_frequency_idle(fd);
> +	igt_subtest_with_dynamic("frequency") {
> +		i915_for_each_gt(fd, tmp, gt) {
> +			igt_dynamic_f("gt%u", gt)
> +				test_frequency(fd, gt);
> +			igt_dynamic_f("idle-gt%u", gt)
> +				test_frequency_idle(fd, gt);
> +		}
> +	}
>
>	/**
>	 * Test interrupt count reporting.
> --
> 2.36.1
>

[igt-dev] ✗ Fi.CI.BAT: failure for PMU: multi-tile support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4222 bytes --]

== Series Details ==

Series: PMU: multi-tile support (rev2)
URL   : https://patchwork.freedesktop.org/series/117406/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> IGTPW_8954
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_8954 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_8954, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/index.html

Participating hosts (38 -> 37)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8954:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-adls-5:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-adls-5/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/bat-adls-5/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in IGTPW_8954 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_backlight@basic-brightness@edp-1:
    - bat-rplp-1:         NOTRUN -> [ABORT][3] ([i915#7077])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
    - bat-dg2-8:          [PASS][4] -> [FAIL][5] ([i915#7932])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][6] ([i915#5334]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  
#### Warnings ####

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rplp-1:         [ABORT][8] ([i915#4579] / [i915#8260]) -> [SKIP][9] ([i915#3555] / [i915#4579])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
  [i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
  [i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7286 -> IGTPW_8954

  CI-20190529: 20190529
  CI_DRM_13143: 222ff19f23b0bd6aca0b52001d69699f78f5a206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8954: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/index.html
  IGT_7286: a482779488f11c432d7ddcb1980691ab1603f356 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@perf_pmu@rc6-all-gts
-igt@kms_fb_coherency@memset-crc
-igt@perf_pmu@frequency-idle
-igt@perf_pmu@rc6-runtime-pm
-igt@perf_pmu@rc6-runtime-pm-long

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8954/index.html

[-- Attachment #2: Type: text/html, Size: 4823 bytes --]

[igt-dev] ✗ Fi.CI.BUILD: failure for PMU: multi-tile support (rev3)

[Patchwork]

== Series Details ==

Series: PMU: multi-tile support (rev3)
URL   : https://patchwork.freedesktop.org/series/117406/
State : failure

== Summary ==

Applying: perf_pmu: Support multi-tile in rc6 subtest
Applying: perf_pmu: Two new rc6 subtests
Applying: perf_pmu: Support multi-tile in frequency subtest
Applying: perf_pmu: Quiesce GPU if measuring idle busyness without spinner
Applying: perf_pmu: Use correct pmu config for multi-tile
Applying: intel_gpu_top: Add an array of freq and rc6 counters
Using index info to reconstruct a base tree...
M	tools/intel_gpu_top.c
Falling back to patching base and 3-way merge...
Auto-merging tools/intel_gpu_top.c
CONFLICT (content): Merge conflict in tools/intel_gpu_top.c
Patch failed at 0006 intel_gpu_top: Add an array of freq and rc6 counters
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".