[igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands

[igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:

1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
  lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
  intel/xe_copy_basic: Add copy basic test to exercise blt commands

 lib/intel_blt.c             | 195 +++++++++++++++++++++++++++++++++
 lib/intel_blt.h             |  39 +++++++
 lib/intel_reg.h             |   4 +
 tests/intel/xe_copy_basic.c | 208 ++++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 5 files changed, 447 insertions(+)
 create mode 100644 tests/intel/xe_copy_basic.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Adding wrapper for mem-set and mem-copy instructions to prepare
batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
emit_blt_mem_copy, emit,blt_set_mem)

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/intel_blt.c | 195 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h |  39 ++++++++++
 lib/intel_reg.h |   4 +
 3 files changed, 238 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index b55fa9b52..cea97c9f3 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -13,12 +13,14 @@
 #include "igt.h"
 #include "igt_syncobj.h"
 #include "intel_blt.h"
+#include "intel_mocs.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
 
 #define BITRANGE(start, end) (end - start + 1)
 #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
+#define MEM_COPY_MOCS_SHIFT                     25
 
 /* Blitter tiling definitions sanity checks */
 static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
@@ -778,6 +780,14 @@ void blt_copy_init(int fd, struct blt_copy_data *blt)
 	blt->driver = get_intel_driver(fd);
 }
 
+void blt_mem_init(int fd, struct blt_mem_data *mem)
+{
+	memset(mem, 0, sizeof(*mem));
+
+	mem->fd = fd;
+	mem->driver = get_intel_driver(fd);
+}
+
 /**
  * emit_blt_block_copy:
  * @fd: drm fd
@@ -1412,6 +1422,174 @@ int blt_fast_copy(int fd,
 	return ret;
 }
 
+static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, uint32_t col_size)
+{
+	uint64_t dst_offset, src_offset, alignment;
+	int i;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+	uint32_t *batch;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+
+	i = 0;
+	batch[i++] = MEM_COPY_CMD | (1 << 19);
+	batch[i++] = mem->src.width - 1;
+	batch[i++] = mem->src.height - 1;
+	batch[i++] = mem->src.pitch - 1;
+	batch[i++] = mem->dst.pitch - 1;
+	batch[i++] = src_offset;
+	batch[i++] = src_offset << 32;
+	batch[i++] = dst_offset;
+	batch[i++] = dst_offset << 32;
+	batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
+	batch[i++] = MI_BATCH_BUFFER_END;
+	batch[i++] = MI_NOOP;
+
+	munmap(batch, mem->bb.size);
+}
+
+/**
+ * blt_mem_copy:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-copy.
+ *
+ * Function does mem blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e,
+		 uint64_t ahnd,
+		 const struct blt_mem_data *mem,
+		 uint32_t col_size)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_copy(fd, ahnd, mem, col_size);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(src_offset);
+		obj[2].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->src.handle;
+		obj[2].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 3;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->src.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
+static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
+			     uint8_t fill_data)
+{
+	uint64_t dst_offset, alignment;
+	int b;
+	uint32_t *batch;
+	uint32_t value;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	value = (uint32_t)fill_data << 24;
+
+	b = 0;
+	batch[b++] = MEM_SET_CMD;
+	batch[b++] = mem->dst.width - 1;
+	batch[b++] = mem->dst.height;
+	batch[b++] = mem->dst.pitch;
+	batch[b++] = dst_offset;
+	batch[b++] = dst_offset << 32;
+	batch[b++] = value | mem->dst.mocs;
+	batch[b++] = MI_BATCH_BUFFER_END;
+	batch[b++] = MI_NOOP;
+
+	munmap(batch, mem->bb.size);
+}
+
+/**
+ * blt_mem_set:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-set.
+ *
+ * Function does mem set blit in described @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+		const struct intel_execution_engine2 *e,
+		uint64_t ahnd,
+		const struct blt_mem_data *mem,
+		uint8_t fill_data)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[2] = {};
+	uint64_t dst_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_set(fd, ahnd, mem, fill_data);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 2;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset)
@@ -1494,6 +1672,23 @@ void blt_set_object(struct blt_copy_object *obj,
 	obj->compression_type = compression_type;
 }
 
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs, enum blt_memop_type type,
+			enum blt_compression compression)
+{
+	obj->handle = handle;
+	obj->region = region;
+	obj->size = size;
+	obj->mocs = mocs;
+	obj->type = type;
+	obj->compression = compression;
+	obj->width = width;
+	obj->height = height;
+	obj->pitch = pitch;
+}
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index d9c8883c7..d4038e9ef 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -93,6 +93,19 @@ struct blt_copy_object {
 	uint32_t plane_offset;
 };
 
+struct blt_mem_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs;
+	enum blt_memop_type type;
+	enum blt_compression compression;
+	uint32_t width;
+	uint32_t height;
+	uint32_t pitch;
+	uint32_t *ptr;
+};
+
 struct blt_copy_batch {
 	uint32_t handle;
 	uint32_t region;
@@ -112,6 +125,14 @@ struct blt_copy_data {
 	bool print_bb;
 };
 
+struct blt_mem_data {
+	int fd;
+	enum intel_driver driver;
+	struct blt_mem_object src;
+	struct blt_mem_object dst;
+	struct blt_copy_batch bb;
+};
+
 enum blt_surface_type {
 	SURFACE_TYPE_1D,
 	SURFACE_TYPE_2D,
@@ -190,6 +211,7 @@ bool blt_uses_extended_block_copy(int fd);
 const char *blt_tiling_name(enum blt_tiling_type tiling);
 
 void blt_copy_init(int fd, struct blt_copy_data *blt);
+void blt_mem_init(int fd, struct blt_mem_data *mem);
 
 uint64_t emit_blt_block_copy(int fd,
 			     uint64_t ahnd,
@@ -231,6 +253,16 @@ int blt_fast_copy(int fd,
 		  uint64_t ahnd,
 		  const struct blt_copy_data *blt);
 
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+			 const struct intel_execution_engine2 *e,
+			 uint64_t ahnd,
+			 const struct blt_mem_data *mem,
+			 uint32_t col_size);
+
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+			const struct intel_execution_engine2 *e, uint64_t ahnd,
+			const struct blt_mem_data *mem, uint8_t fill_data);
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset);
@@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
 		    uint8_t mocs, enum blt_tiling_type tiling,
 		    enum blt_compression compression,
 		    enum blt_compression_type compression_type);
+
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs, enum blt_memop_type type,
+			enum blt_compression compression);
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 3bf3676dc..eb65da911 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2586,6 +2586,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
 #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
 
+/* RAW memory commands */
+#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
+#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
+
 #define CTXT_NO_RESTORE			(1)
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Zbigniew Kempczyński]

On Tue, Oct 03, 2023 at 01:03:43PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Adding wrapper for mem-set and mem-copy instructions to prepare
> batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
> emit_blt_mem_copy, emit,blt_set_mem)
                         ^--- s/,/_/
> 
> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  lib/intel_blt.c | 195 ++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/intel_blt.h |  39 ++++++++++
>  lib/intel_reg.h |   4 +
>  3 files changed, 238 insertions(+)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index b55fa9b52..cea97c9f3 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -13,12 +13,14 @@
>  #include "igt.h"
>  #include "igt_syncobj.h"
>  #include "intel_blt.h"
> +#include "intel_mocs.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
>  
>  #define BITRANGE(start, end) (end - start + 1)
>  #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
> +#define MEM_COPY_MOCS_SHIFT                     25
>  
>  /* Blitter tiling definitions sanity checks */
>  static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
> @@ -778,6 +780,14 @@ void blt_copy_init(int fd, struct blt_copy_data *blt)
>  	blt->driver = get_intel_driver(fd);
>  }
>  
> +void blt_mem_init(int fd, struct blt_mem_data *mem)
> +{
> +	memset(mem, 0, sizeof(*mem));
> +
> +	mem->fd = fd;
> +	mem->driver = get_intel_driver(fd);
> +}
> +

Move this to place where mem-copy/set functions reside.
And as this is public function document it.

>  /**
>   * emit_blt_block_copy:
>   * @fd: drm fd
> @@ -1412,6 +1422,174 @@ int blt_fast_copy(int fd,
>  	return ret;
>  }
>  
> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem, uint32_t col_size)

What col_size is for?

> +{
> +	uint64_t dst_offset, src_offset, alignment;
> +	int i;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;

Mocs are part of blt_mem_object.

> +	uint32_t *batch;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +
> +	i = 0;
> +	batch[i++] = MEM_COPY_CMD | (1 << 19);

Bit 19 is reserved. What about 17-18 - linear and matrix copy?
Use type field from the object to establish the operation.

> +	batch[i++] = mem->src.width - 1;
> +	batch[i++] = mem->src.height - 1;
> +	batch[i++] = mem->src.pitch - 1;
> +	batch[i++] = mem->dst.pitch - 1;
> +	batch[i++] = src_offset;
> +	batch[i++] = src_offset << 32;
> +	batch[i++] = dst_offset;
> +	batch[i++] = dst_offset << 32;
> +	batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
> +	batch[i++] = MI_BATCH_BUFFER_END;
> +	batch[i++] = MI_NOOP;

Batch is mmaped so zeroed, MI_NOOP is not necessary.

> +
> +	munmap(batch, mem->bb.size);
> +}
> +
> +/**
> + * blt_mem_copy:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-copy.
> + *
> + * Function does mem blit between @src and @dst described in @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +		 const struct intel_execution_engine2 *e,
> +		 uint64_t ahnd,
> +		 const struct blt_mem_data *mem,
> +		 uint32_t col_size)

Same here with col_size. It is unused.

> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_copy(fd, ahnd, mem, col_size);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(src_offset);
> +		obj[2].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->src.handle;
> +		obj[2].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 3;
> +		execbuf.buffers_ptr = to_user_pointer(obj);
> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->src.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
> +			     uint8_t fill_data)
> +{
> +	uint64_t dst_offset, alignment;
> +	int b;
> +	uint32_t *batch;
> +	uint32_t value;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +	value = (uint32_t)fill_data << 24;
> +
> +	b = 0;
> +	batch[b++] = MEM_SET_CMD;
> +	batch[b++] = mem->dst.width - 1;
> +	batch[b++] = mem->dst.height;
> +	batch[b++] = mem->dst.pitch;

Height and pitch are also U18-1.

> +	batch[b++] = dst_offset;
> +	batch[b++] = dst_offset << 32;
> +	batch[b++] = value | mem->dst.mocs;
> +	batch[b++] = MI_BATCH_BUFFER_END;
> +	batch[b++] = MI_NOOP;

Batch is mmaped so zeroed, MI_NOOP is not necessary.

> +
> +	munmap(batch, mem->bb.size);
> +}
> +
> +/**
> + * blt_mem_set:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-set.
> + *
> + * Function does mem set blit in described @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +		const struct intel_execution_engine2 *e,
> +		uint64_t ahnd,
> +		const struct blt_mem_data *mem,
> +		uint8_t fill_data)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[2] = {};
> +	uint64_t dst_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 2;
> +		execbuf.buffers_ptr = to_user_pointer(obj);
> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset)
> @@ -1494,6 +1672,23 @@ void blt_set_object(struct blt_copy_object *obj,
>  	obj->compression_type = compression_type;
>  }
>  
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs, enum blt_memop_type type,
> +			enum blt_compression compression)
> +{
> +	obj->handle = handle;
> +	obj->region = region;
> +	obj->size = size;
> +	obj->mocs = mocs;
> +	obj->type = type;

So you have most important information about object here (M_LINEAR
or M_MATRIX). Use this in above instructions where you're emitting
batch. I mean depending on this field you should use appropriate
width/height/pitch.

> +	obj->compression = compression;
> +	obj->width = width;
> +	obj->height = height;
> +	obj->pitch = pitch;
> +}
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index d9c8883c7..d4038e9ef 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -93,6 +93,19 @@ struct blt_copy_object {
>  	uint32_t plane_offset;
>  };
>  
> +struct blt_mem_object {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +	uint8_t mocs;
> +	enum blt_memop_type type;
> +	enum blt_compression compression;
> +	uint32_t width;
> +	uint32_t height;
> +	uint32_t pitch;
> +	uint32_t *ptr;
> +};
> +

I think above fields are fine.

>  struct blt_copy_batch {
>  	uint32_t handle;
>  	uint32_t region;
> @@ -112,6 +125,14 @@ struct blt_copy_data {
>  	bool print_bb;

As you've added print_bb implement dumping instruction similar
to block-copy/fast-copy/ctrl-surf-copy if user will set it to true.

--
Zbigniew

>  };
>  
> +struct blt_mem_data {
> +	int fd;
> +	enum intel_driver driver;
> +	struct blt_mem_object src;
> +	struct blt_mem_object dst;
> +	struct blt_copy_batch bb;
> +};
> +
>  enum blt_surface_type {
>  	SURFACE_TYPE_1D,
>  	SURFACE_TYPE_2D,
> @@ -190,6 +211,7 @@ bool blt_uses_extended_block_copy(int fd);
>  const char *blt_tiling_name(enum blt_tiling_type tiling);
>  
>  void blt_copy_init(int fd, struct blt_copy_data *blt);
> +void blt_mem_init(int fd, struct blt_mem_data *mem);
>  
>  uint64_t emit_blt_block_copy(int fd,
>  			     uint64_t ahnd,
> @@ -231,6 +253,16 @@ int blt_fast_copy(int fd,
>  		  uint64_t ahnd,
>  		  const struct blt_copy_data *blt);
>  
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +			 const struct intel_execution_engine2 *e,
> +			 uint64_t ahnd,
> +			 const struct blt_mem_data *mem,
> +			 uint32_t col_size);
> +
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +			const struct intel_execution_engine2 *e, uint64_t ahnd,
> +			const struct blt_mem_data *mem, uint8_t fill_data);
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset);
> @@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
>  		    uint8_t mocs, enum blt_tiling_type tiling,
>  		    enum blt_compression compression,
>  		    enum blt_compression_type compression_type);
> +
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs, enum blt_memop_type type,
> +			enum blt_compression compression);
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index 3bf3676dc..eb65da911 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2586,6 +2586,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>  
> +/* RAW memory commands */
> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
> +
>  #define CTXT_NO_RESTORE			(1)
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> -- 
> 2.39.1
> 

Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>Sent: Friday, October 6, 2023 1:19 PM
>To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Stolarek, Karolina
><karolina.stolarek@intel.com>
>Subject: Re: [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch
>buffers and submit exec
>
>On Tue, Oct 03, 2023 at 01:03:43PM +0530, sai.gowtham.ch@intel.com wrote:
>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>
>> Adding wrapper for mem-set and mem-copy instructions to prepare batch
>> buffers and submit exec, (blt_mem_copy, blt_mem_set,
>> emit_blt_mem_copy, emit,blt_set_mem)
>                         ^--- s/,/_/
>>
>> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> ---
>>  lib/intel_blt.c | 195
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>  lib/intel_blt.h |  39 ++++++++++
>>  lib/intel_reg.h |   4 +
>>  3 files changed, 238 insertions(+)
>>
>> diff --git a/lib/intel_blt.c b/lib/intel_blt.c index
>> b55fa9b52..cea97c9f3 100644
>> --- a/lib/intel_blt.c
>> +++ b/lib/intel_blt.c
>> @@ -13,12 +13,14 @@
>>  #include "igt.h"
>>  #include "igt_syncobj.h"
>>  #include "intel_blt.h"
>> +#include "intel_mocs.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_util.h"
>>
>>  #define BITRANGE(start, end) (end - start + 1)  #define
>> GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
>> +#define MEM_COPY_MOCS_SHIFT                     25
>>
>>  /* Blitter tiling definitions sanity checks */
>> static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have
>> to match"); @@ -778,6 +780,14 @@ void blt_copy_init(int fd, struct
>blt_copy_data *blt)
>>  	blt->driver = get_intel_driver(fd);
>>  }
>>
>> +void blt_mem_init(int fd, struct blt_mem_data *mem) {
>> +	memset(mem, 0, sizeof(*mem));
>> +
>> +	mem->fd = fd;
>> +	mem->driver = get_intel_driver(fd);
>> +}
>> +
>
>Move this to place where mem-copy/set functions reside.
>And as this is public function document it.
>
>>  /**
>>   * emit_blt_block_copy:
>>   * @fd: drm fd
>> @@ -1412,6 +1422,174 @@ int blt_fast_copy(int fd,
>>  	return ret;
>>  }
>>
>> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct
>> +blt_mem_data *mem, uint32_t col_size)
>
>What col_size is for?
>
>> +{
>> +	uint64_t dst_offset, src_offset, alignment;
>> +	int i;
>> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
>> +	uint8_t dst_mocs = src_mocs;
>
>Mocs are part of blt_mem_object.
>
>> +	uint32_t *batch;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +
>> +	i = 0;
>> +	batch[i++] = MEM_COPY_CMD | (1 << 19);
>
>Bit 19 is reserved. What about 17-18 - linear and matrix copy?
>Use type field from the object to establish the operation.

Do you mean there should be a check if user want to run Liner or matrix copy based on that bit has to be set ?
However MEM copy doesn't support Matrix copy, do we still need this check ?
>
>> +	batch[i++] = mem->src.width - 1;
>> +	batch[i++] = mem->src.height - 1;
>> +	batch[i++] = mem->src.pitch - 1;
>> +	batch[i++] = mem->dst.pitch - 1;
>> +	batch[i++] = src_offset;
>> +	batch[i++] = src_offset << 32;
>> +	batch[i++] = dst_offset;
>> +	batch[i++] = dst_offset << 32;
>> +	batch[i++] = src_mocs << MEM_COPY_MOCS_SHIFT | dst_mocs;
>> +	batch[i++] = MI_BATCH_BUFFER_END;
>> +	batch[i++] = MI_NOOP;
>
>Batch is mmaped so zeroed, MI_NOOP is not necessary.
Will correct that.
>
>> +
>> +	munmap(batch, mem->bb.size);
>> +}
>> +
>> +/**
>> + * blt_mem_copy:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-copy.
>> + *
>> + * Function does mem blit between @src and @dst described in @blt
>object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +		 const struct intel_execution_engine2 *e,
>> +		 uint64_t ahnd,
>> +		 const struct blt_mem_data *mem,
>> +		 uint32_t col_size)
>
>Same here with col_size. It is unused.
Sure Will correct that.
>
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[3] = {};
>> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_copy(fd, ahnd, mem, col_size);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(src_offset);
>> +		obj[2].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->src.handle;
>> +		obj[2].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[2].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 3;
>> +		execbuf.buffers_ptr = to_user_pointer(obj);
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->src.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct
>blt_mem_data *mem,
>> +			     uint8_t fill_data)
>> +{
>> +	uint64_t dst_offset, alignment;
>> +	int b;
>> +	uint32_t *batch;
>> +	uint32_t value;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +	value = (uint32_t)fill_data << 24;
>> +
>> +	b = 0;
>> +	batch[b++] = MEM_SET_CMD;
>> +	batch[b++] = mem->dst.width - 1;
>> +	batch[b++] = mem->dst.height;
>> +	batch[b++] = mem->dst.pitch;
>
>Height and pitch are also U18-1.
>
>> +	batch[b++] = dst_offset;
>> +	batch[b++] = dst_offset << 32;
>> +	batch[b++] = value | mem->dst.mocs;
>> +	batch[b++] = MI_BATCH_BUFFER_END;
>> +	batch[b++] = MI_NOOP;
>
>Batch is mmaped so zeroed, MI_NOOP is not necessary.
>
>> +
>> +	munmap(batch, mem->bb.size);
>> +}
>> +
>> +/**
>> + * blt_mem_set:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-set.
>> + *
>> + * Function does mem set blit in described @blt object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +		const struct intel_execution_engine2 *e,
>> +		uint64_t ahnd,
>> +		const struct blt_mem_data *mem,
>> +		uint8_t fill_data)
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[2] = {};
>> +	uint64_t dst_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 2;
>> +		execbuf.buffers_ptr = to_user_pointer(obj);
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset) @@ -1494,6 +1672,23
>@@ void
>> blt_set_object(struct blt_copy_object *obj,
>>  	obj->compression_type = compression_type;  }
>>
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs, enum blt_memop_type type,
>> +			enum blt_compression compression)
>> +{
>> +	obj->handle = handle;
>> +	obj->region = region;
>> +	obj->size = size;
>> +	obj->mocs = mocs;
>> +	obj->type = type;
>
>So you have most important information about object here (M_LINEAR or
>M_MATRIX). Use this in above instructions where you're emitting batch. I
>mean depending on this field you should use appropriate width/height/pitch.
Got it will add that support.
>
>> +	obj->compression = compression;
>> +	obj->width = width;
>> +	obj->height = height;
>> +	obj->pitch = pitch;
>> +}
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_blt.h b/lib/intel_blt.h index d9c8883c7..d4038e9ef 100644
>> --- a/lib/intel_blt.h
>> +++ b/lib/intel_blt.h
>> @@ -93,6 +93,19 @@ struct blt_copy_object {
>>  	uint32_t plane_offset;
>>  };
>>
>> +struct blt_mem_object {
>> +	uint32_t handle;
>> +	uint32_t region;
>> +	uint64_t size;
>> +	uint8_t mocs;
>> +	enum blt_memop_type type;
>> +	enum blt_compression compression;
>> +	uint32_t width;
>> +	uint32_t height;
>> +	uint32_t pitch;
>> +	uint32_t *ptr;
>> +};
>> +
>
>I think above fields are fine.
>
>>  struct blt_copy_batch {
>>  	uint32_t handle;
>>  	uint32_t region;
>> @@ -112,6 +125,14 @@ struct blt_copy_data {
>>  	bool print_bb;
>
>As you've added print_bb implement dumping instruction similar to block-
>copy/fast-copy/ctrl-surf-copy if user will set it to true.
>
>--
>Zbigniew

----
Sai Gowtham Ch
>
>>  };
>>
>> +struct blt_mem_data {
>> +	int fd;
>> +	enum intel_driver driver;
>> +	struct blt_mem_object src;
>> +	struct blt_mem_object dst;
>> +	struct blt_copy_batch bb;
>> +};
>> +
>>  enum blt_surface_type {
>>  	SURFACE_TYPE_1D,
>>  	SURFACE_TYPE_2D,
>> @@ -190,6 +211,7 @@ bool blt_uses_extended_block_copy(int fd);  const
>> char *blt_tiling_name(enum blt_tiling_type tiling);
>>
>>  void blt_copy_init(int fd, struct blt_copy_data *blt);
>> +void blt_mem_init(int fd, struct blt_mem_data *mem);
>>
>>  uint64_t emit_blt_block_copy(int fd,
>>  			     uint64_t ahnd,
>> @@ -231,6 +253,16 @@ int blt_fast_copy(int fd,
>>  		  uint64_t ahnd,
>>  		  const struct blt_copy_data *blt);
>>
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +			 const struct intel_execution_engine2 *e,
>> +			 uint64_t ahnd,
>> +			 const struct blt_mem_data *mem,
>> +			 uint32_t col_size);
>> +
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +			const struct intel_execution_engine2 *e, uint64_t
>ahnd,
>> +			const struct blt_mem_data *mem, uint8_t fill_data);
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset); @@ -250,6 +282,13 @@
>void
>> blt_set_object(struct blt_copy_object *obj,
>>  		    uint8_t mocs, enum blt_tiling_type tiling,
>>  		    enum blt_compression compression,
>>  		    enum blt_compression_type compression_type);
>> +
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs, enum blt_memop_type type,
>> +			enum blt_compression compression);
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_reg.h b/lib/intel_reg.h index 3bf3676dc..eb65da911 100644
>> --- a/lib/intel_reg.h
>> +++ b/lib/intel_reg.h
>> @@ -2586,6 +2586,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
>THE SOFTWARE.
>>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>>
>> +/* RAW memory commands */
>> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
>> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
>> +
>>  #define CTXT_NO_RESTORE			(1)
>>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>> --
>> 2.39.1
>>

[igt-dev] [PATCH i-g-t 2/2] intel/xe_copy_basic: Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test to exercise copy commands like mem-copy and mem-set.

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_copy_basic.c | 208 ++++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 2 files changed, 209 insertions(+)
 create mode 100644 tests/intel/xe_copy_basic.c

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
new file mode 100644
index 000000000..9aed6e43c
--- /dev/null
+++ b/tests/intel/xe_copy_basic.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ *
+ * Authors:
+ *      Sai Gowtham Ch <sai.gowtham.ch@intel.com>
+ */
+
+#include "igt.h"
+#include "lib/igt_syncobj.h"
+#include "intel_blt.h"
+#include "lib/intel_cmds_info.h"
+#include "lib/intel_mocs.h"
+#include "lib/intel_reg.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
+
+#define MEM_FILL 0x8b
+
+/**
+ * TEST: Test to validate copy commands on xe
+ * Category: Software building block
+ * Sub-category: Copy
+ * Functionality: blitter
+ */
+
+/**
+ * SUBTEST: mem-copy-%s
+ * Description: Test validates MEM_COPY command, it takes various
+ *              parameters needed for the filling batch buffer for MEM_COPY command
+ *              with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ * @0x369: 0x369
+ * @0x3fff: 0x3fff
+ * @0xfd: 0xfd
+ * @0xffff: 0xffff
+ */
+static void
+igt_mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle,
+	     const intel_ctx_t *ctx, uint32_t row_size, uint32_t size,
+	     uint32_t col_size, uint32_t region)
+{
+	struct blt_mem_data mem = {};
+	uint64_t bb_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
+						  INTEL_ALLOCATOR_SIMPLE,
+						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+	uint32_t bb;
+	int result;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+
+	bb = xe_bo_create_flags(fd, 0, bb_size, region);
+
+	blt_mem_init(fd, &mem);
+	blt_set_mem_object(&mem.src, src_handle, row_size, 0, size, col_size,
+			   region, src_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, col_size,
+			   region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	mem.src.ptr = xe_bo_map(fd, src_handle, row_size);
+	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
+
+	blt_set_batch(&mem.bb, bb, bb_size, region);
+	igt_assert(mem.src.size == mem.dst.size);
+
+	blt_mem_copy(fd, ctx, NULL, ahnd, &mem, col_size);
+	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
+	igt_assert_f(!result, "source and destination differ\n");
+
+	intel_allocator_bind(ahnd, 0, 0);
+	munmap(mem.src.ptr, row_size);
+	munmap(mem.dst.ptr, row_size);
+	gem_close(fd, bb);
+	put_ahnd(ahnd);
+}
+
+/**
+ * SUBTEST: mem-set-%s
+ * Description: Test validates MEM_SET command with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @0x369: 0x369
+ * @0x3fff: 0x3fff
+ * @0xfd: 0xfd
+ * @0xffff: 0xffff
+ */
+static void igt_mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx,
+			uint32_t row_size, uint32_t size, uint32_t height,
+			uint8_t fill_data, uint32_t region)
+{
+	struct blt_mem_data mem = {};
+	uint64_t bb_size = xe_get_default_alignment(fd);
+	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
+						  INTEL_ALLOCATOR_SIMPLE,
+						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+	uint32_t bb;
+	uint32_t result[row_size + 1];
+	uint8_t dst_mocs = intel_get_uc_mocs(fd);
+
+	bb = xe_bo_create_flags(fd, 0, bb_size, region);
+	blt_mem_init(fd, &mem);
+	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, height, region,
+			   dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
+	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
+	blt_set_batch(&mem.bb, bb, bb_size, region);
+	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
+
+	for(int i = 0; i<= row_size + 1; i ++) {
+		result[i] = mem.dst.ptr[i];
+	};
+
+	igt_assert(result[0] = fill_data);
+	igt_assert(result[row_size + 1] != fill_data);
+
+	intel_allocator_bind(ahnd, 0, 0);
+	munmap(mem.dst.ptr, row_size);
+	gem_close(fd, bb);
+	put_ahnd(ahnd);
+}
+
+static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
+{
+	struct drm_xe_engine_class_instance inst = {
+		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
+	};
+	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
+	uint32_t bo_size = ALIGN(size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
+	const intel_ctx_t *ctx;
+
+	src_handle = xe_bo_create_flags(fd, 0, bo_size, region);
+	dst_handle = xe_bo_create_flags(fd, 0, bo_size, region);
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
+	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
+
+	src_size = bo_size;
+	dst_size = bo_size;
+
+	if (cmd == MEM_COPY) {
+		igt_mem_copy(fd,
+			     src_handle,
+			     dst_handle,
+			     ctx,
+			     src_size,
+			     size,
+			     1,
+			     region);
+	} else if (cmd == MEM_SET) {
+		igt_mem_set(fd,
+			    dst_handle,
+			    ctx,
+			    dst_size,
+			    size,
+			    1,
+			    MEM_FILL,
+			    region);
+	}
+
+	gem_close(fd, src_handle);
+	gem_close(fd, dst_handle);
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+}
+
+igt_main
+{
+	int fd;
+	struct igt_collection *set, *regions;
+	uint32_t region;
+	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFF};
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		xe_device_get(fd);
+		set = xe_get_memory_region_set(fd,
+					       XE_MEM_REGION_CLASS_SYSMEM,
+					       XE_MEM_REGION_CLASS_VRAM);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(size); i++) {
+		igt_subtest_f("mem-copy-0x%lx", size[i]) {
+			igt_require(blt_has_mem_copy(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, size[i], MEM_COPY, region);
+			}
+		}
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(size); i++) {
+		igt_subtest_f("mem-set-0x%lx", size[i]) {
+			igt_require(blt_has_mem_set(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, size[i], MEM_SET, region);
+			}
+		}
+	}
+
+	igt_fixture {
+		drm_close_driver(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 974cb433b..3381fd919 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -274,6 +274,7 @@ intel_xe_progs = [
 	'xe_ccs',
 	'xe_create',
 	'xe_compute',
+	'xe_copy_basic',
 	'xe_dma_buf_sync',
 	'xe_debugfs',
 	'xe_drm_fdinfo',
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 2/2] intel/xe_copy_basic: Add copy basic test to exercise blt commands

[Zbigniew Kempczyński]

On Tue, Oct 03, 2023 at 01:03:44PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Add copy basic test to exercise copy commands like mem-copy and mem-set.
> 
> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_copy_basic.c | 208 ++++++++++++++++++++++++++++++++++++
>  tests/meson.build           |   1 +
>  2 files changed, 209 insertions(+)
>  create mode 100644 tests/intel/xe_copy_basic.c
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> new file mode 100644
> index 000000000..9aed6e43c
> --- /dev/null
> +++ b/tests/intel/xe_copy_basic.c
> @@ -0,0 +1,208 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + *
> + * Authors:
> + *      Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> + */
> +
> +#include "igt.h"
> +#include "lib/igt_syncobj.h"
> +#include "intel_blt.h"
> +#include "lib/intel_cmds_info.h"
> +#include "lib/intel_mocs.h"
> +#include "lib/intel_reg.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_util.h"
> +
> +#define MEM_FILL 0x8b
> +
> +/**
> + * TEST: Test to validate copy commands on xe
> + * Category: Software building block
> + * Sub-category: Copy
> + * Functionality: blitter
> + */
> +
> +/**
> + * SUBTEST: mem-copy-%s
> + * Description: Test validates MEM_COPY command, it takes various
> + *              parameters needed for the filling batch buffer for MEM_COPY command
> + *              with size %arg[1].
> + * Test category: functionality test
> + *
> + * arg[1]:
> + * @0x369: 0x369
> + * @0x3fff: 0x3fff
> + * @0xfd: 0xfd
> + * @0xffff: 0xffff
> + */
> +static void
> +igt_mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle,

This is test, you don't need to use igt_ prefix here. It is a little
bit confusing for me as I think with igt_ functions as global. Same
nitpick is with igt_mem_set().

> +	     const intel_ctx_t *ctx, uint32_t row_size, uint32_t size,
> +	     uint32_t col_size, uint32_t region)

Use size as real size of object, pitch, width and height as there's
confusion with all of the above.

> +{
> +	struct blt_mem_data mem = {};
> +	uint64_t bb_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
> +						  INTEL_ALLOCATOR_SIMPLE,
> +						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	uint32_t bb;
> +	int result;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
> +
> +	blt_mem_init(fd, &mem);
> +	blt_set_mem_object(&mem.src, src_handle, row_size, 0, size, col_size,
> +			   region, src_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, col_size,
> +			   region, dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	mem.src.ptr = xe_bo_map(fd, src_handle, row_size);
> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
> +
> +	blt_set_batch(&mem.bb, bb, bb_size, region);
> +	igt_assert(mem.src.size == mem.dst.size);

For linear checking width instead of whole bo size would be enough imo.

> +
> +	blt_mem_copy(fd, ctx, NULL, ahnd, &mem, col_size);

Operation should be described in mem structure, col_size is not used
and has no meaning for real operation here. At the moment you're
checking linear copy, so test name should reflect it.

> +	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
> +	igt_assert_f(!result, "source and destination differ\n");
> +
> +	intel_allocator_bind(ahnd, 0, 0);
> +	munmap(mem.src.ptr, row_size);
> +	munmap(mem.dst.ptr, row_size);
> +	gem_close(fd, bb);
> +	put_ahnd(ahnd);
> +}
> +
> +/**
> + * SUBTEST: mem-set-%s
> + * Description: Test validates MEM_SET command with size %arg[1].
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @0x369: 0x369
> + * @0x3fff: 0x3fff
> + * @0xfd: 0xfd
> + * @0xffff: 0xffff

0xffff is problematic in case of checking last element (is expected) and
this after it. Use 0xfffe.

> + */
> +static void igt_mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx,
> +			uint32_t row_size, uint32_t size, uint32_t height,
> +			uint8_t fill_data, uint32_t region)

Same issue with size, pitch, width and height.

> +{
> +	struct blt_mem_data mem = {};
> +	uint64_t bb_size = xe_get_default_alignment(fd);
> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
> +						  INTEL_ALLOCATOR_SIMPLE,
> +						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	uint32_t bb;
> +	uint32_t result[row_size + 1];

Use uint8_t *result;

> +	uint8_t dst_mocs = intel_get_uc_mocs(fd);
> +
> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
> +	blt_mem_init(fd, &mem);
> +	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, height, region,
> +			   dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
> +	blt_set_batch(&mem.bb, bb, bb_size, region);
> +	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
> +
> +	for(int i = 0; i<= row_size + 1; i ++) {

Formatting should look like
	for (int i = 0; i <= row_size + 1; i++)
but I don't want to have this loop so that's nitpick about neat formatting.

> +		result[i] = mem.dst.ptr[i];
> +	};

Don't rewrite to result, just do point to dst memory:

result = (uint8_t *)mem.dst.ptr;

You're able to directly check n-th element.

> +
> +	igt_assert(result[0] = fill_data);
> +	igt_assert(result[row_size + 1] != fill_data);

Check indices 0, width - 1 and width. Last one shouldn't contain
fill_data.

> +
> +	intel_allocator_bind(ahnd, 0, 0);
> +	munmap(mem.dst.ptr, row_size);
> +	gem_close(fd, bb);
> +	put_ahnd(ahnd);

Technically it is not properly cleaned up state (allocator still
contains src.offset and dst.offset, similar to vm). But looking
at the copy_test() function finally you're closing src and dst
and destroy exec_queue and vm so you don't hit overlapping offsets
(you setup copy operation from scratch). That's fine for me
for this case but be aware of binding constraints when allocator
is in use.

> +}
> +
> +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
> +{
> +	struct drm_xe_engine_class_instance inst = {
> +		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
> +	};
> +	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
> +	uint32_t bo_size = ALIGN(size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
> +	const intel_ctx_t *ctx;
> +
> +	src_handle = xe_bo_create_flags(fd, 0, bo_size, region);

You're unnecessary creating src_handle for mem-set op.

> +	dst_handle = xe_bo_create_flags(fd, 0, bo_size, region);
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> +	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
> +	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
> +
> +	src_size = bo_size;
> +	dst_size = bo_size;
> +
> +	if (cmd == MEM_COPY) {
> +		igt_mem_copy(fd,
> +			     src_handle,
> +			     dst_handle,
> +			     ctx,
> +			     src_size,
> +			     size,
> +			     1,
> +			     region);

That single column formatting looks weird, especially you've a lot space
to fill 80-columns line.

> +	} else if (cmd == MEM_SET) {
> +		igt_mem_set(fd,
> +			    dst_handle,
> +			    ctx,
> +			    dst_size,
> +			    size,
> +			    1,
> +			    MEM_FILL,
> +			    region);
> +	}

Same here.

> +
> +	gem_close(fd, src_handle);
> +	gem_close(fd, dst_handle);
> +	xe_exec_queue_destroy(fd, exec_queue);
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +igt_main
> +{
> +	int fd;
> +	struct igt_collection *set, *regions;
> +	uint32_t region;
> +	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFF};

I would use 0xfffe instead 0xffff to check what's about byte after
last element.

--
Zbigniew
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_XE);
> +		xe_device_get(fd);
> +		set = xe_get_memory_region_set(fd,
> +					       XE_MEM_REGION_CLASS_SYSMEM,
> +					       XE_MEM_REGION_CLASS_VRAM);
> +	}
> +
> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> +		igt_subtest_f("mem-copy-0x%lx", size[i]) {
> +			igt_require(blt_has_mem_copy(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, size[i], MEM_COPY, region);
> +			}
> +		}
> +	}
> +
> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> +		igt_subtest_f("mem-set-0x%lx", size[i]) {
> +			igt_require(blt_has_mem_set(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, size[i], MEM_SET, region);
> +			}
> +		}
> +	}
> +
> +	igt_fixture {
> +		drm_close_driver(fd);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 974cb433b..3381fd919 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -274,6 +274,7 @@ intel_xe_progs = [
>  	'xe_ccs',
>  	'xe_create',
>  	'xe_compute',
> +	'xe_copy_basic',
>  	'xe_dma_buf_sync',
>  	'xe_debugfs',
>  	'xe_drm_fdinfo',
> -- 
> 2.39.1
> 

Re: [igt-dev] [PATCH i-g-t 2/2] intel/xe_copy_basic: Add copy basic test to exercise blt commands

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>Sent: Friday, October 6, 2023 1:44 PM
>To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Stolarek, Karolina
><karolina.stolarek@intel.com>
>Subject: Re: [PATCH i-g-t 2/2] intel/xe_copy_basic: Add copy basic test to
>exercise blt commands
>
>On Tue, Oct 03, 2023 at 01:03:44PM +0530, sai.gowtham.ch@intel.com wrote:
>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>
>> Add copy basic test to exercise copy commands like mem-copy and mem-set.
>>
>> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> ---
>>  tests/intel/xe_copy_basic.c | 208
>++++++++++++++++++++++++++++++++++++
>>  tests/meson.build           |   1 +
>>  2 files changed, 209 insertions(+)
>>  create mode 100644 tests/intel/xe_copy_basic.c
>>
>> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
>> new file mode 100644 index 000000000..9aed6e43c
>> --- /dev/null
>> +++ b/tests/intel/xe_copy_basic.c
>> @@ -0,0 +1,208 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + *
>> + * Authors:
>> + *      Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> + */
>> +
>> +#include "igt.h"
>> +#include "lib/igt_syncobj.h"
>> +#include "intel_blt.h"
>> +#include "lib/intel_cmds_info.h"
>> +#include "lib/intel_mocs.h"
>> +#include "lib/intel_reg.h"
>> +#include "xe/xe_ioctl.h"
>> +#include "xe/xe_query.h"
>> +#include "xe/xe_util.h"
>> +
>> +#define MEM_FILL 0x8b
>> +
>> +/**
>> + * TEST: Test to validate copy commands on xe
>> + * Category: Software building block
>> + * Sub-category: Copy
>> + * Functionality: blitter
>> + */
>> +
>> +/**
>> + * SUBTEST: mem-copy-%s
>> + * Description: Test validates MEM_COPY command, it takes various
>> + *              parameters needed for the filling batch buffer for MEM_COPY
>command
>> + *              with size %arg[1].
>> + * Test category: functionality test
>> + *
>> + * arg[1]:
>> + * @0x369: 0x369
>> + * @0x3fff: 0x3fff
>> + * @0xfd: 0xfd
>> + * @0xffff: 0xffff
>> + */
>> +static void
>> +igt_mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle,
>
>This is test, you don't need to use igt_ prefix here. It is a little bit confusing for
>me as I think with igt_ functions as global. Same nitpick is with igt_mem_set().
>
>> +	     const intel_ctx_t *ctx, uint32_t row_size, uint32_t size,
>> +	     uint32_t col_size, uint32_t region)
>
>Use size as real size of object, pitch, width and height as there's confusion
>with all of the above.
Sure Will update that.
>
>> +{
>> +	struct blt_mem_data mem = {};
>> +	uint64_t bb_size = xe_get_default_alignment(fd);
>> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
>> +						  INTEL_ALLOCATOR_SIMPLE,
>> +
>ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> +	uint32_t bb;
>> +	int result;
>> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
>> +	uint8_t dst_mocs = src_mocs;
>> +
>> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
>> +
>> +	blt_mem_init(fd, &mem);
>> +	blt_set_mem_object(&mem.src, src_handle, row_size, 0, size, col_size,
>> +			   region, src_mocs, M_LINEAR,
>COMPRESSION_DISABLED);
>> +	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, col_size,
>> +			   region, dst_mocs, M_LINEAR,
>COMPRESSION_DISABLED);
>> +	mem.src.ptr = xe_bo_map(fd, src_handle, row_size);
>> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
>> +
>> +	blt_set_batch(&mem.bb, bb, bb_size, region);
>> +	igt_assert(mem.src.size == mem.dst.size);
>
>For linear checking width instead of whole bo size would be enough imo.
Sure.
>
>> +
>> +	blt_mem_copy(fd, ctx, NULL, ahnd, &mem, col_size);
>
>Operation should be described in mem structure, col_size is not used and has
>no meaning for real operation here. At the moment you're checking linear
>copy, so test name should reflect it.
Sure will add operation in mem structure, and use that in checking if the user wants to run the test for linear or matrix.
Should the subtest name need to be changed to something like mem-linear-copy-"size" ?
>
>> +	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
>> +	igt_assert_f(!result, "source and destination differ\n");
>> +
>> +	intel_allocator_bind(ahnd, 0, 0);
>> +	munmap(mem.src.ptr, row_size);
>> +	munmap(mem.dst.ptr, row_size);
>> +	gem_close(fd, bb);
>> +	put_ahnd(ahnd);
>> +}
>> +
>> +/**
>> + * SUBTEST: mem-set-%s
>> + * Description: Test validates MEM_SET command with size %arg[1].
>> + * Test category: functionality test
>> + *
>> + * arg[1]:
>> + *
>> + * @0x369: 0x369
>> + * @0x3fff: 0x3fff
>> + * @0xfd: 0xfd
>> + * @0xffff: 0xffff
>
>0xffff is problematic in case of checking last element (is expected) and this
>after it. Use 0xfffe.
Sure will replace it.
>
>> + */
>> +static void igt_mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx,
>> +			uint32_t row_size, uint32_t size, uint32_t height,
>> +			uint8_t fill_data, uint32_t region)
>
>Same issue with size, pitch, width and height.
>
>> +{
>> +	struct blt_mem_data mem = {};
>> +	uint64_t bb_size = xe_get_default_alignment(fd);
>> +	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
>> +						  INTEL_ALLOCATOR_SIMPLE,
>> +
>ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> +	uint32_t bb;
>> +	uint32_t result[row_size + 1];
>
>Use uint8_t *result;
>
>> +	uint8_t dst_mocs = intel_get_uc_mocs(fd);
>> +
>> +	bb = xe_bo_create_flags(fd, 0, bb_size, region);
>> +	blt_mem_init(fd, &mem);
>> +	blt_set_mem_object(&mem.dst, dst_handle, row_size, 0, size, height,
>region,
>> +			   dst_mocs, M_LINEAR, COMPRESSION_DISABLED);
>> +	mem.dst.ptr = xe_bo_map(fd, dst_handle, row_size);
>> +	blt_set_batch(&mem.bb, bb, bb_size, region);
>> +	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
>> +
>> +	for(int i = 0; i<= row_size + 1; i ++) {
>
>Formatting should look like
>	for (int i = 0; i <= row_size + 1; i++) but I don't want to have this loop
>so that's nitpick about neat formatting.
>
>> +		result[i] = mem.dst.ptr[i];
>> +	};
>
>Don't rewrite to result, just do point to dst memory:
>
>result = (uint8_t *)mem.dst.ptr;
>
>You're able to directly check n-th element.
>
This make sense will try this out.
>> +
>> +	igt_assert(result[0] = fill_data);
>> +	igt_assert(result[row_size + 1] != fill_data);
>
>Check indices 0, width - 1 and width. Last one shouldn't contain fill_data.
>
>> +
>> +	intel_allocator_bind(ahnd, 0, 0);
>> +	munmap(mem.dst.ptr, row_size);
>> +	gem_close(fd, bb);
>> +	put_ahnd(ahnd);
>
>Technically it is not properly cleaned up state (allocator still contains src.offset
>and dst.offset, similar to vm). But looking at the copy_test() function finally
>you're closing src and dst and destroy exec_queue and vm so you don't hit
>overlapping offsets (you setup copy operation from scratch). That's fine for me
>for this case but be aware of binding constraints when allocator is in use.
>
Before sending out an other patch will keep this in mind, will check if everything is cleaned properly.
>> +}
>> +
>> +static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd,
>> +uint32_t region) {
>> +	struct drm_xe_engine_class_instance inst = {
>> +		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
>> +	};
>> +	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
>> +	uint32_t bo_size = ALIGN(size + xe_cs_prefetch_size(fd),
>xe_get_default_alignment(fd));
>> +	const intel_ctx_t *ctx;
>> +
>> +	src_handle = xe_bo_create_flags(fd, 0, bo_size, region);
>
>You're unnecessary creating src_handle for mem-set op.
>
>> +	dst_handle = xe_bo_create_flags(fd, 0, bo_size, region);
>> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
>> +	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
>> +	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
>> +
>> +	src_size = bo_size;
>> +	dst_size = bo_size;
>> +
>> +	if (cmd == MEM_COPY) {
>> +		igt_mem_copy(fd,
>> +			     src_handle,
>> +			     dst_handle,
>> +			     ctx,
>> +			     src_size,
>> +			     size,
>> +			     1,
>> +			     region);
>
>That single column formatting looks weird, especially you've a lot space to fill
>80-columns line.
>
>> +	} else if (cmd == MEM_SET) {
>> +		igt_mem_set(fd,
>> +			    dst_handle,
>> +			    ctx,
>> +			    dst_size,
>> +			    size,
>> +			    1,
>> +			    MEM_FILL,
>> +			    region);
>> +	}
>
>Same here.
>
>> +
>> +	gem_close(fd, src_handle);
>> +	gem_close(fd, dst_handle);
>> +	xe_exec_queue_destroy(fd, exec_queue);
>> +	xe_vm_destroy(fd, vm);
>> +}
>> +
>> +igt_main
>> +{
>> +	int fd;
>> +	struct igt_collection *set, *regions;
>> +	uint32_t region;
>> +	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFF};
>
>I would use 0xfffe instead 0xffff to check what's about byte after last element.
>
>--
>Zbigniew

Thanks for your review comments, Will send an other patch for review.

----
Sai Gowtham Ch
>> +
>> +	igt_fixture {
>> +		fd = drm_open_driver(DRIVER_XE);
>> +		xe_device_get(fd);
>> +		set = xe_get_memory_region_set(fd,
>> +
>XE_MEM_REGION_CLASS_SYSMEM,
>> +					       XE_MEM_REGION_CLASS_VRAM);
>> +	}
>> +
>> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
>> +		igt_subtest_f("mem-copy-0x%lx", size[i]) {
>> +			igt_require(blt_has_mem_copy(fd));
>> +			for_each_variation_r(regions, 1, set) {
>> +				region = igt_collection_get_value(regions, 0);
>> +				copy_test(fd, size[i], MEM_COPY, region);
>> +			}
>> +		}
>> +	}
>> +
>> +	for (int i = 0; i < ARRAY_SIZE(size); i++) {
>> +		igt_subtest_f("mem-set-0x%lx", size[i]) {
>> +			igt_require(blt_has_mem_set(fd));
>> +			for_each_variation_r(regions, 1, set) {
>> +				region = igt_collection_get_value(regions, 0);
>> +				copy_test(fd, size[i], MEM_SET, region);
>> +			}
>> +		}
>> +	}
>> +
>> +	igt_fixture {
>> +		drm_close_driver(fd);
>> +	}
>> +}
>> diff --git a/tests/meson.build b/tests/meson.build index
>> 974cb433b..3381fd919 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -274,6 +274,7 @@ intel_xe_progs = [
>>  	'xe_ccs',
>>  	'xe_create',
>>  	'xe_compute',
>> +	'xe_copy_basic',
>>  	'xe_dma_buf_sync',
>>  	'xe_debugfs',
>>  	'xe_drm_fdinfo',
>> --
>> 2.39.1
>>

[igt-dev] ✓ CI.xeBAT: success for Add copy basic test to exercise blt commands (rev5)

[Patchwork]

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== Series Details ==

Series: Add copy basic test to exercise blt commands (rev5)
URL   : https://patchwork.freedesktop.org/series/122615/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7508_BAT -> XEIGTPW_9909_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_9909_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-dg2-oem2:       [FAIL][1] ([Intel XE#480]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7508/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9909/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480


Build changes
-------------

  * IGT: IGT_7508 -> IGTPW_9909
  * Linux: xe-404-22fcf2404f56a8e7aea6734298e0b2b265136313 -> xe-410-02ab43e36623665d8644d46162bd4ec5eeb68489

  IGTPW_9909: 9909
  IGT_7508: f366406b05ca6b3d16eaa734a91e0833bd159f54 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-404-22fcf2404f56a8e7aea6734298e0b2b265136313: 22fcf2404f56a8e7aea6734298e0b2b265136313
  xe-410-02ab43e36623665d8644d46162bd4ec5eeb68489: 02ab43e36623665d8644d46162bd4ec5eeb68489

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9909/index.html

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[igt-dev] ✓ Fi.CI.BAT: success for Add copy basic test to exercise blt commands (rev5)

[Patchwork]

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== Series Details ==

Series: Add copy basic test to exercise blt commands (rev5)
URL   : https://patchwork.freedesktop.org/series/122615/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13703 -> IGTPW_9909
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/index.html

Participating hosts (40 -> 37)
------------------------------

  Missing    (3): fi-hsw-4770 fi-snb-2520m fi-bsw-n3050 

Known issues
------------

  Here are the changes found in IGTPW_9909 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-dg2-9:          [PASS][1] -> [INCOMPLETE][2] ([i915#9275])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@requests:
    - bat-mtlp-8:         [PASS][3] -> [ABORT][4] ([i915#9414])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/bat-mtlp-8/igt@i915_selftest@live@requests.html

  
#### Possible fixes ####

  * igt@gem_busy@busy@all-engines:
    - bat-mtlp-8:         [DMESG-FAIL][5] ([i915#8962]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/bat-mtlp-8/igt@gem_busy@busy@all-engines.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/bat-mtlp-8/igt@gem_busy@busy@all-engines.html

  
  [i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7508 -> IGTPW_9909

  CI-20190529: 20190529
  CI_DRM_13703: db3606b4b70e8205895c2c57892bb7b1f2d436a4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9909: 9909
  IGT_7508: f366406b05ca6b3d16eaa734a91e0833bd159f54 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@xe_copy_basic@mem-copy-0x3fff
+igt@xe_copy_basic@mem-copy-0x369
+igt@xe_copy_basic@mem-copy-0xfd
+igt@xe_copy_basic@mem-copy-0xffff
+igt@xe_copy_basic@mem-set-0x3fff
+igt@xe_copy_basic@mem-set-0x369
+igt@xe_copy_basic@mem-set-0xfd
+igt@xe_copy_basic@mem-set-0xffff

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/index.html

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[igt-dev] ✗ Fi.CI.IGT: failure for Add copy basic test to exercise blt commands (rev5)

[Patchwork]

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== Series Details ==

Series: Add copy basic test to exercise blt commands (rev5)
URL   : https://patchwork.freedesktop.org/series/122615/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13703_full -> IGTPW_9909_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_9909_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_9909_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/index.html

Participating hosts (9 -> 10)
------------------------------

  Additional (1): shard-tglu0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_9909_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload:
    - shard-snb:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-snb5/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-snb6/igt@i915_module_load@reload.html

  
Known issues
------------

  Here are the changes found in IGTPW_9909_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-6/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][4] ([i915#6122])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@api_intel_bb@render-ccs.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu:         NOTRUN -> [SKIP][5] ([i915#7701])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-5/igt@device_reset@unbind-cold-reset-rebind.html
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          [PASS][7] -> [FAIL][8] ([i915#7742]) +1 other test fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-6/igt@drm_fdinfo@idle@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@drm_fdinfo@idle@rcs0.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][9] ([i915#8414]) +21 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@drm_fdinfo@most-busy-check-all@vcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#8414]) +11 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@drm_fdinfo@most-busy-check-all@vcs0.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][11] ([i915#7297])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-mtlp:         NOTRUN -> [SKIP][12] ([i915#6335])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-mtlp:         [PASS][13] -> [FAIL][14] ([i915#6268])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-1/igt@gem_ctx_exec@basic-nohangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@engines-hang@vcs0:
    - shard-mtlp:         [PASS][15] -> [FAIL][16] ([i915#2410])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-2/igt@gem_ctx_persistence@engines-hang@vcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-3/igt@gem_ctx_persistence@engines-hang@vcs0.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#8555])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_sseu@engines:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-7/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg1:          NOTRUN -> [SKIP][20] ([i915#280])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@reset-stress:
    - shard-dg2:          [PASS][21] -> [FAIL][22] ([i915#5784]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-3/igt@gem_eio@reset-stress.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@gem_eio@reset-stress.html

  * igt@gem_eio@suspend:
    - shard-snb:          NOTRUN -> [DMESG-WARN][23] ([i915#8841])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-snb5/igt@gem_eio@suspend.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#4771])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4812]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_capture@capture-invisible@lmem0:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#6334]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@gem_exec_capture@capture-invisible@lmem0.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu:         NOTRUN -> [SKIP][28] ([i915#6334])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-4/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#6344])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-mtlp:         [PASS][30] -> [FAIL][31] ([i915#4475])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-1/igt@gem_exec_capture@pi@vcs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          NOTRUN -> [FAIL][32] ([i915#2846])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-glk:          [PASS][33] -> [FAIL][34] ([i915#2842])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-tglu:         NOTRUN -> [FAIL][35] ([i915#2842]) +4 other tests fail
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gem_exec_fair@basic-pace-share:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#4473] / [i915#4771])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@gem_exec_fair@basic-pace-share.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-rkl:          [PASS][37] -> [FAIL][38] ([i915#2842]) +1 other test fail
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-tglu:         [PASS][39] -> [FAIL][40] ([i915#2842])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-sync:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#3539]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@gem_exec_fair@basic-sync.html

  * igt@gem_exec_fence@submit67:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#4812])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#3539] / [i915#4852]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@gem_exec_flush@basic-batch-kernel-default-wb.html

  * igt@gem_exec_flush@basic-wb-rw-default:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3539] / [i915#4852]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_exec_flush@basic-wb-rw-default.html

  * igt@gem_exec_gttfill@multigpu-basic:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#7697]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@gem_exec_gttfill@multigpu-basic.html
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#7697])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gem_exec_gttfill@multigpu-basic.html

  * igt@gem_exec_params@secure-non-master:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([fdo#112283])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@gem_exec_params@secure-non-master.html
    - shard-rkl:          NOTRUN -> [SKIP][48] ([fdo#112283])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@gem_exec_params@secure-non-master.html

  * igt@gem_exec_reloc@basic-active:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#3281]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-gtt-active:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#3281]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-active.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#3281]) +10 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg1:          NOTRUN -> [SKIP][52] ([i915#3281]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@preempt-queue-chain:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#4537] / [i915#4812]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@gem_exec_schedule@preempt-queue-chain.html

  * igt@gem_exec_schedule@preemptive-hang@vcs0:
    - shard-mtlp:         [PASS][54] -> [FAIL][55] ([i915#9051])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-4/igt@gem_exec_schedule@preemptive-hang@vcs0.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs0.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg1:          [PASS][56] -> [ABORT][57] ([i915#7975] / [i915#8213])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-19/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_exec_suspend@basic-s4-devices@smem:
    - shard-rkl:          NOTRUN -> [ABORT][58] ([i915#7975] / [i915#8213])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices@smem.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#4860]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_fenced_exec_thrash@2-spare-fences.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#4860])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][61] ([i915#4613])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-2/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-glk:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4613]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk8/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][63] -> [DMESG-WARN][64] ([i915#4936] / [i915#5493])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#4613])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@big-bo:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#4083]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@gem_mmap@big-bo.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-dg1:          NOTRUN -> [SKIP][67] ([i915#4077])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#4077]) +12 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][69] ([i915#4083]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_mmap_wc@read-write.html

  * igt@gem_mmap_wc@write-prefaulted:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#4083])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@gem_mmap_wc@write-prefaulted.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#3282])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_pread@snoop:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#3282]) +7 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@gem_pread@snoop.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][73] ([i915#2658])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk4/igt@gem_pwrite@basic-exhaustion.html
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#3282])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#4270])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4270]) +4 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][77] ([i915#4270])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#4270])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#8428])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][80] ([fdo#109271]) +102 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk9/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#4079])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#4079])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_spin_batch@spin-each:
    - shard-mtlp:         [PASS][83] -> [DMESG-FAIL][84] ([i915#8962])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-6/igt@gem_spin_batch@spin-each.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-4/igt@gem_spin_batch@spin-each.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([fdo#110542])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#3297]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-dg1:          NOTRUN -> [SKIP][87] ([i915#3297] / [i915#4880])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gen3_mixed_blits:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([fdo#109289]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@gen3_mixed_blits.html
    - shard-rkl:          NOTRUN -> [SKIP][89] ([fdo#109289])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@gen3_mixed_blits.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-tglu:         NOTRUN -> [SKIP][90] ([fdo#109289])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#2856]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@gen9_exec_parse@bb-start-param.html
    - shard-tglu:         NOTRUN -> [SKIP][92] ([i915#2527] / [i915#2856])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-6/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#2527])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@i915_hangman@gt-engine-hang@vcs0:
    - shard-mtlp:         [PASS][94] -> [FAIL][95] ([i915#7069]) +1 other test fail
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-6/igt@i915_hangman@gt-engine-hang@vcs0.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-7/igt@i915_hangman@gt-engine-hang@vcs0.html

  * igt@i915_hangman@gt-error-state-capture@vecs0:
    - shard-mtlp:         [PASS][96] -> [ABORT][97] ([i915#9414]) +1 other test abort
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-2/igt@i915_hangman@gt-error-state-capture@vecs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-3/igt@i915_hangman@gt-error-state-capture@vecs0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][98] ([i915#8617])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#8399])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][100] -> [INCOMPLETE][101] ([i915#9407])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-5/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - shard-dg1:          [PASS][102] -> [FAIL][103] ([i915#3591])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg1:          NOTRUN -> [SKIP][104] ([i915#1397])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@fences-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([i915#4077]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-7/igt@i915_pm_rpm@fences-dpms.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [PASS][106] -> [SKIP][107] ([i915#1397])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([i915#1397])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][109] -> [SKIP][110] ([i915#1397])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
    - shard-dg1:          [PASS][111] -> [SKIP][112] ([i915#1397])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-18/igt@i915_pm_rpm@modeset-non-lpsp.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@i915_pm_rpm@pc8-residency:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([fdo#109506])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@i915_pm_rpm@pc8-residency.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#6621])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][115] -> [INCOMPLETE][116] ([i915#7790])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-snb5/igt@i915_pm_rps@reset.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-idle@gt1:
    - shard-mtlp:         NOTRUN -> [SKIP][117] ([i915#8925]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@i915_pm_rps@thresholds-idle@gt1.html

  * igt@i915_pm_rps@thresholds@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#8925])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@i915_pm_rps@thresholds@gt0.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([fdo#109303])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@i915_query@query-topology-known-pci-ids.html
    - shard-rkl:          NOTRUN -> [SKIP][120] ([fdo#109303])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_query@query-topology-unsupported:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([fdo#109302])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@i915_query@query-topology-unsupported.html
    - shard-tglu:         NOTRUN -> [SKIP][122] ([fdo#109302])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-6/igt@i915_query@query-topology-unsupported.html

  * igt@i915_selftest@mock@memory_region:
    - shard-mtlp:         NOTRUN -> [DMESG-WARN][123] ([i915#9311])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@i915_selftest@mock@memory_region.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4212]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#8502]) +3 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#8502] / [i915#8709]) +11 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs.html

  * igt@kms_async_flips@crc@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][127] ([i915#8247]) +3 other tests fail
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#6228])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg1:          NOTRUN -> [SKIP][129] ([i915#404])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-tglu:         NOTRUN -> [SKIP][130] ([i915#1769] / [i915#3555])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#1769] / [i915#3555])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-mtlp:         [PASS][132] -> [FAIL][133] ([i915#5138]) +1 other test fail
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([fdo#111614])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#5286])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([fdo#111615] / [i915#5286]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#3638]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-12/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([fdo#111614]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#5190]) +11 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#4538] / [i915#5190]) +5 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([fdo#111615])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][142] ([fdo#111615]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][143] ([fdo#111615])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][144] ([i915#4538])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][145] ([i915#5354] / [i915#6095]) +6 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-2/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#3689] / [i915#5354]) +20 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-12/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#3734] / [i915#5354] / [i915#6095]) +3 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_mc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#5354] / [i915#6095]) +2 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_mtl_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_mtl_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#5354]) +48 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_mtl_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][151] ([fdo#109271] / [i915#3886]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk9/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][152] ([i915#3689] / [i915#5354] / [i915#6095]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-15/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][153] ([i915#3886] / [i915#5354] / [i915#6095]) +2 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#3689] / [i915#3886] / [i915#5354]) +7 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][155] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-3/igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#5354]) +5 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#3689] / [i915#5354] / [i915#6095]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-7/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_rc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][158] ([i915#5354] / [i915#6095]) +6 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-17/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][159] ([i915#5354] / [i915#6095]) +8 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][160] ([fdo#111827])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-9/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([fdo#111827])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2:          NOTRUN -> [SKIP][162] ([fdo#111827]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-6/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - shard-tglu:         NOTRUN -> [SKIP][163] ([i915#7828])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-dg1:          NOTRUN -> [SKIP][164] ([i915#7828]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#7828]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-rkl:          NOTRUN -> [SKIP][166] ([i915#7828]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#7828]) +6 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#3116] / [i915#3299])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@legacy@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][169] ([i915#7173]) +1 other test timeout
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#7118])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-mtlp:         NOTRUN -> [SKIP][171] ([i915#6944])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-4/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([fdo#109279] / [i915#3359])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#3359]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][174] ([i915#3555]) +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#3359]) +1 other test skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-4/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][176] ([i915#3555] / [i915#8814])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([fdo#109274] / [fdo#111767] / [i915#5354])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([fdo#109274] / [i915#5354]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
    - shard-tglu:         NOTRUN -> [SKIP][179] ([fdo#109274])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][180] -> [FAIL][181] ([i915#2346])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#4103] / [i915#4213])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][183] ([i915#9226] / [i915#9261]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#9227])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#3555]) +6 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#3555] / [i915#3840]) +2 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#3555] / [i915#3840])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#3469])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_fbcon_fbt@psr.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#3469])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-19/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-dg2:          NOTRUN -> [SKIP][190] ([fdo#109274]) +4 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([fdo#111825]) +1 other test skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-2/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([fdo#109274] / [fdo#111767])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
    - shard-tglu:         NOTRUN -> [SKIP][193] ([fdo#109274] / [fdo#111767] / [i915#3637])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][194] ([i915#3637])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-dg2:          NOTRUN -> [FAIL][195] ([fdo#103375]) +4 other tests fail
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#2587] / [i915#2672])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][197] ([i915#2587] / [i915#2672])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][198] ([i915#2672])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][199] ([i915#2672])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#2672] / [i915#3555])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][201] ([i915#2672]) +4 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-dg1:          NOTRUN -> [SKIP][202] ([fdo#109285])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          [PASS][203] -> [FAIL][204] ([i915#6880])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][205] ([i915#8708]) +12 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
    - shard-rkl:          NOTRUN -> [SKIP][206] ([fdo#111825] / [i915#1825]) +7 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-dg1:          NOTRUN -> [SKIP][207] ([fdo#111825]) +12 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][208] ([i915#5460])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][209] ([i915#3023]) +1 other test skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][210] ([i915#8708]) +1 other test skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][211] ([i915#8708]) +5 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][212] ([fdo#109280]) +5 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#3458]) +18 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([fdo#110189]) +7 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#3458]) +1 other test skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-snb:          NOTRUN -> [SKIP][216] ([fdo#109271]) +38 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-snb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-mtlp:         NOTRUN -> [SKIP][217] ([i915#1825]) +4 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@bpc-switch:
    - shard-rkl:          NOTRUN -> [SKIP][218] ([i915#3555] / [i915#8228])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-2/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555] / [i915#8228])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-swap:
    - shard-mtlp:         NOTRUN -> [SKIP][220] ([i915#3555] / [i915#8228])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@kms_hdr@static-swap.html

  * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
    - shard-mtlp:         NOTRUN -> [SKIP][221] ([fdo#109289]) +1 other test skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-dg2:          [PASS][222] -> [FAIL][223] ([fdo#103375])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][224] ([i915#8292])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][225] -> [FAIL][226] ([i915#8292])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-5/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#5235]) +7 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][228] ([i915#5235]) +15 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][229] ([i915#5235]) +15 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-17/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][230] ([i915#6524] / [i915#6805]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
    - shard-glk:          NOTRUN -> [SKIP][231] ([fdo#109271] / [i915#658])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#658]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#658]) +3 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-tglu:         NOTRUN -> [SKIP][234] ([fdo#109642] / [fdo#111068] / [i915#658])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-4/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-dg1:          NOTRUN -> [SKIP][235] ([i915#1072]) +2 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_psr@sprite_mmap_cpu:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#1072]) +2 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@kms_psr@sprite_mmap_cpu.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][237] ([i915#4235])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-mtlp:         NOTRUN -> [SKIP][238] ([i915#5289])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][239] ([i915#4235] / [i915#5190])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][240] ([i915#3555]) +1 other test skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-mtlp:         NOTRUN -> [SKIP][241] ([i915#3555] / [i915#8809])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-rkl:          NOTRUN -> [SKIP][242] ([i915#3555] / [i915#4098])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          NOTRUN -> [FAIL][243] ([IGT#2])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-b:
    - shard-rkl:          [PASS][244] -> [FAIL][245] ([i915#9196])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-c:
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#4070] / [i915#6768]) +1 other test skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
    - shard-tglu:         [PASS][247] -> [FAIL][248] ([i915#9196])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html

  * igt@kms_vblank@pipe-d-ts-continuation-idle-hang:
    - shard-rkl:          NOTRUN -> [SKIP][249] ([i915#4070] / [i915#533] / [i915#6768])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@kms_vblank@pipe-d-ts-continuation-idle-hang.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-glk:          NOTRUN -> [SKIP][250] ([fdo#109271] / [i915#2437])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk2/igt@kms_writeback@writeback-pixel-formats.html
    - shard-rkl:          NOTRUN -> [SKIP][251] ([i915#2437])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-dg2:          NOTRUN -> [SKIP][252] ([i915#2436])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-double-start@rcs0:
    - shard-mtlp:         [PASS][253] -> [FAIL][254] ([i915#4349])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-6/igt@perf_pmu@busy-double-start@rcs0.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-8/igt@perf_pmu@busy-double-start@rcs0.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-dg2:          NOTRUN -> [SKIP][255] ([i915#8850])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@perf_pmu@cpu-hotplug.html
    - shard-mtlp:         NOTRUN -> [SKIP][256] ([i915#8850])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@perf_pmu@cpu-hotplug.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [CRASH][257] ([i915#9351])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@basic-blt:
    - shard-mtlp:         NOTRUN -> [FAIL][258] ([i915#8445])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@prime_vgem@basic-blt.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg1:          NOTRUN -> [SKIP][259] ([i915#3708])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg2:          NOTRUN -> [SKIP][260] ([i915#3291] / [i915#3708]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@prime_vgem@basic-fence-read.html
    - shard-rkl:          NOTRUN -> [SKIP][261] ([fdo#109295] / [i915#3291] / [i915#3708])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          NOTRUN -> [SKIP][262] ([fdo#109295] / [i915#3708])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-2/igt@prime_vgem@fence-read-hang.html

  * igt@v3d/v3d_job_submission@array-job-submission:
    - shard-dg1:          NOTRUN -> [SKIP][263] ([i915#2575]) +2 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@v3d/v3d_job_submission@array-job-submission.html

  * igt@v3d/v3d_submit_cl@multi-and-single-sync:
    - shard-rkl:          NOTRUN -> [SKIP][264] ([fdo#109315]) +3 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@v3d/v3d_submit_cl@multi-and-single-sync.html

  * igt@v3d/v3d_submit_cl@single-out-sync:
    - shard-tglu:         NOTRUN -> [SKIP][265] ([fdo#109315] / [i915#2575]) +2 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@v3d/v3d_submit_cl@single-out-sync.html

  * igt@v3d/v3d_submit_cl@valid-multisync-submission:
    - shard-dg2:          NOTRUN -> [SKIP][266] ([i915#2575]) +10 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@v3d/v3d_submit_cl@valid-multisync-submission.html

  * igt@v3d/v3d_wait_bo@used-bo-1ns:
    - shard-mtlp:         NOTRUN -> [SKIP][267] ([i915#2575]) +1 other test skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@v3d/v3d_wait_bo@used-bo-1ns.html

  * igt@vc4/vc4_purgeable_bo@mark-purgeable:
    - shard-dg1:          NOTRUN -> [SKIP][268] ([i915#7711]) +1 other test skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-12/igt@vc4/vc4_purgeable_bo@mark-purgeable.html

  * igt@vc4/vc4_tiling@set-bad-handle:
    - shard-mtlp:         NOTRUN -> [SKIP][269] ([i915#7711])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-2/igt@vc4/vc4_tiling@set-bad-handle.html

  * igt@vc4/vc4_tiling@set-get:
    - shard-rkl:          NOTRUN -> [SKIP][270] ([i915#7711]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@vc4/vc4_tiling@set-get.html

  * igt@vc4/vc4_wait_bo@unused-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][271] ([i915#7711]) +7 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-6/igt@vc4/vc4_wait_bo@unused-bo-1ns.html

  * igt@vc4/vc4_wait_bo@used-bo:
    - shard-tglu:         NOTRUN -> [SKIP][272] ([i915#2575]) +1 other test skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-4/igt@vc4/vc4_wait_bo@used-bo.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - shard-glk:          [DMESG-WARN][273] ([i915#118]) -> [PASS][274]
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-glk8/igt@drm_fdinfo@virtual-idle.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk9/igt@drm_fdinfo@virtual-idle.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [FAIL][275] ([i915#6268]) -> [PASS][276]
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@legacy-engines-hostile@vebox:
    - shard-mtlp:         [FAIL][277] ([i915#2410]) -> [PASS][278] +2 other tests pass
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-2/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-6/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-rkl:          [FAIL][279] ([i915#2842]) -> [PASS][280] +2 other tests pass
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][281] ([i915#2842]) -> [PASS][282]
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_schedule@noreorder@ccs0:
    - shard-mtlp:         [DMESG-FAIL][283] ([i915#8962]) -> [PASS][284] +1 other test pass
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-4/igt@gem_exec_schedule@noreorder@ccs0.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-3/igt@gem_exec_schedule@noreorder@ccs0.html

  * igt@gem_exec_schedule@preemptive-hang@vcs1:
    - shard-mtlp:         [ABORT][285] ([i915#9414]) -> [PASS][286]
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-4/igt@gem_exec_schedule@preemptive-hang@vcs1.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs1.html

  * igt@gem_workarounds@suspend-resume:
    - shard-dg2:          [FAIL][287] ([fdo#103375]) -> [PASS][288]
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-5/igt@gem_workarounds@suspend-resume.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-1/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [FAIL][289] ([i915#3591]) -> [PASS][290]
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][291] ([i915#1397]) -> [PASS][292] +2 other tests pass
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-2/igt@i915_pm_rpm@dpms-lpsp.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [FAIL][293] ([fdo#103375]) -> [PASS][294]
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][295] ([i915#3743]) -> [PASS][296] +2 other tests pass
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][297] ([i915#2346]) -> [PASS][298] +1 other test pass
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2:          [FAIL][299] ([i915#6880]) -> [PASS][300] +2 other tests pass
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * {igt@kms_pm_dc@dc9-dpms}:
    - shard-tglu:         [SKIP][301] ([i915#4281]) -> [PASS][302]
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-2/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-rkl:          [INCOMPLETE][303] ([i915#8875]) -> [PASS][304]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-1/igt@kms_rotation_crc@primary-rotation-90.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@perf_pmu@busy-idle@vcs0:
    - shard-dg2:          [FAIL][305] ([i915#4349]) -> [PASS][306] +7 other tests pass
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-10/igt@perf_pmu@busy-idle@vcs0.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-3/igt@perf_pmu@busy-idle@vcs0.html
    - shard-dg1:          [FAIL][307] ([i915#4349]) -> [PASS][308] +2 other tests pass
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-19/igt@perf_pmu@busy-idle@vcs0.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-18/igt@perf_pmu@busy-idle@vcs0.html
    - shard-mtlp:         [FAIL][309] ([i915#4349]) -> [PASS][310] +3 other tests pass
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-3/igt@perf_pmu@busy-idle@vcs0.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-7/igt@perf_pmu@busy-idle@vcs0.html

  * igt@sysfs_preempt_timeout@timeout@vecs0:
    - shard-mtlp:         [ABORT][311] ([i915#8521] / [i915#8865]) -> [PASS][312] +1 other test pass
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-mtlp-7/igt@sysfs_preempt_timeout@timeout@vecs0.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-mtlp-1/igt@sysfs_preempt_timeout@timeout@vecs0.html

  
#### Warnings ####

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-dg2:          [ABORT][313] ([i915#7461]) -> [INCOMPLETE][314] ([i915#9364])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg2-3/igt@gem_create@create-ext-cpu-access-big.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - shard-tglu:         [FAIL][315] ([i915#2681] / [i915#3591]) -> [WARN][316] ([i915#2681])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs:
    - shard-snb:          [INCOMPLETE][317] ([i915#2295]) -> [SKIP][318] ([fdo#109271])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-snb1/igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-snb6/igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][319] ([fdo#110189] / [i915#3955]) -> [SKIP][320] ([i915#3955]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][321] ([fdo#109285] / [i915#4098]) -> [SKIP][322] ([fdo#109285])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][323] ([i915#4816]) -> [SKIP][324] ([i915#4070] / [i915#4816])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@cursor_plane_move:
    - shard-dg1:          [SKIP][325] ([i915#1072]) -> [SKIP][326] ([i915#1072] / [i915#4078]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-15/igt@kms_psr@cursor_plane_move.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-12/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][327] ([i915#1072] / [i915#4078]) -> [SKIP][328] ([i915#1072])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13703/shard-dg1-16/igt@kms_psr@sprite_plane_onoff.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/shard-dg1-14/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
  [i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8445]: https://gitlab.freedesktop.org/drm/intel/issues/8445
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
  [i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
  [i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
  [i915#9051]: https://gitlab.freedesktop.org/drm/intel/issues/9051
  [i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9226]: https://gitlab.freedesktop.org/drm/intel/issues/9226
  [i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
  [i915#9261]: https://gitlab.freedesktop.org/drm/intel/issues/9261
  [i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
  [i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
  [i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
  [i915#9364]: https://gitlab.freedesktop.org/drm/intel/issues/9364
  [i915#9407]: https://gitlab.freedesktop.org/drm/intel/issues/9407
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7508 -> IGTPW_9909
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_13703: db3606b4b70e8205895c2c57892bb7b1f2d436a4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9909: 9909
  IGT_7508: f366406b05ca6b3d16eaa734a91e0833bd159f54 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9909/index.html

[-- Attachment #2: Type: text/html, Size: 106480 bytes --]

[igt-dev] [PATCH i-g-t 0/2] Add copy basic test to exercise blt commands

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Add copy basic test which exercies mem-se and mem-copy commands, this
patch series involves in following changes:

1. Add copy basic test to exercise blt commands.
2. Add wrappers for batch preparation and submit exec.
3. Add copy commands MEM_SET_CMD and MEM_COPY_CMD in the lib.

Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Sai Gowtham Ch (2):
  lib/intel_blt: Add wrappers to prepare batch buffers and submit exec
  intel/xe_copy_basic: Add copy basic test to exercise blt commands

 lib/intel_blt.c             | 199 ++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h             |  39 +++++++
 lib/intel_reg.h             |   4 +
 tests/intel/xe_copy_basic.c | 195 +++++++++++++++++++++++++++++++++++
 tests/meson.build           |   1 +
 5 files changed, 438 insertions(+)
 create mode 100644 tests/intel/xe_copy_basic.c

-- 
2.39.1

[igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[sai.gowtham.ch]

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

Adding wrapper for mem-set and mem-copy instructions to prepare
batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
emit_blt_mem_copy, emit_blt_set_mem)

Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/intel_blt.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h |  39 ++++++++++
 lib/intel_reg.h |   4 +
 3 files changed, 242 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index a76c7a404..4e7357b6f 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -13,12 +13,14 @@
 #include "igt.h"
 #include "igt_syncobj.h"
 #include "intel_blt.h"
+#include "intel_mocs.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "xe/xe_util.h"
 
 #define BITRANGE(start, end) (end - start + 1)
 #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
+#define MEM_COPY_MOCS_SHIFT                     25
 
 /* Blitter tiling definitions sanity checks */
 static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
@@ -1577,6 +1579,186 @@ int blt_fast_copy(int fd,
 	return ret;
 }
 
+/**
+ * blt_mem_init:
+ * @fd: drm fd
+ * @mem: structure for initialization
+ *
+ * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_mem_init(int fd, struct blt_mem_data *mem)
+{
+	memset(mem, 0, sizeof(*mem));
+
+	mem->fd = fd;
+	mem->driver = get_intel_driver(fd);
+}
+
+static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
+{
+	uint64_t dst_offset, src_offset, alignment;
+	int i;
+	uint32_t *batch;
+	uint32_t optype;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
+
+	i = 0;
+	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
+	batch[i++] = mem->src.width - 1;
+	batch[i++] = mem->src.height - 1;
+	batch[i++] = mem->src.pitch - 1;
+	batch[i++] = mem->dst.pitch - 1;
+	batch[i++] = src_offset;
+	batch[i++] = src_offset << 32;
+	batch[i++] = dst_offset;
+	batch[i++] = dst_offset << 32;
+	batch[i++] = mem->src.mocs << MEM_COPY_MOCS_SHIFT | mem->dst.mocs;
+	batch[i++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+}
+
+/**
+ * blt_mem_copy:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-copy.
+ *
+ * Function does mem blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e,
+		 uint64_t ahnd,
+		 const struct blt_mem_data *mem)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_copy(fd, ahnd, mem);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(src_offset);
+		obj[2].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->src.handle;
+		obj[2].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 3;
+                execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->src.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
+static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
+			     uint8_t fill_data)
+{
+	uint64_t dst_offset, alignment;
+	int b;
+	uint32_t *batch;
+	uint32_t value;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+
+	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+	value = (uint32_t)fill_data << 24;
+
+	b = 0;
+	batch[b++] = MEM_SET_CMD;
+	batch[b++] = mem->dst.width - 1;
+	batch[b++] = mem->dst.height - 1;
+	batch[b++] = mem->dst.pitch - 1;
+	batch[b++] = dst_offset;
+	batch[b++] = dst_offset << 32;
+	batch[b++] = value | mem->dst.mocs;
+	batch[b++] = MI_BATCH_BUFFER_END;
+
+	munmap(batch, mem->bb.size);
+}
+/**
+ * blt_mem_set:
+ * @fd: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for mem-set.
+ *
+ * Function does mem set blit in described @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+		const struct intel_execution_engine2 *e,
+		uint64_t ahnd,
+		const struct blt_mem_data *mem,
+		uint8_t fill_data)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[2] = {};
+	uint64_t dst_offset, bb_offset, alignment;
+	int ret;
+
+	alignment = get_default_alignment(fd, mem->driver);
+	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
+	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
+
+	emit_blt_mem_set(fd, ahnd, mem, fill_data);
+
+	if (mem->driver == INTEL_DRIVER_XE) {
+		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[1].offset = CANONICAL(bb_offset);
+		obj[0].handle = mem->dst.handle;
+		obj[1].handle = mem->bb.handle;
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+						    EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		execbuf.buffer_count = 2;
+		execbuf.buffers_ptr = to_user_pointer(obj);
+		execbuf.rsvd1 = ctx ? ctx->id : 0;
+		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+		ret = __gem_execbuf(fd, &execbuf);
+		put_offset(ahnd, mem->dst.handle);
+		put_offset(ahnd, mem->bb.handle);
+	}
+
+	return ret;
+}
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset)
@@ -1659,6 +1841,23 @@ void blt_set_object(struct blt_copy_object *obj,
 	obj->compression_type = compression_type;
 }
 
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs, enum blt_memop_type type,
+			enum blt_compression compression)
+{
+	obj->handle = handle;
+	obj->region = region;
+	obj->size = size;
+	obj->mocs = mocs;
+	obj->type = type;
+	obj->compression = compression;
+	obj->width = width;
+	obj->height = height;
+	obj->pitch = pitch;
+}
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 7b4271620..d6f40680d 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -93,6 +93,19 @@ struct blt_copy_object {
 	uint32_t plane_offset;
 };
 
+struct blt_mem_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs;
+	enum blt_memop_type type;
+	enum blt_compression compression;
+	uint32_t width;
+	uint32_t height;
+	uint32_t pitch;
+	uint32_t *ptr;
+};
+
 struct blt_copy_batch {
 	uint32_t handle;
 	uint32_t region;
@@ -112,6 +125,14 @@ struct blt_copy_data {
 	bool print_bb;
 };
 
+struct blt_mem_data {
+	int fd;
+	enum intel_driver driver;
+	struct blt_mem_object src;
+	struct blt_mem_object dst;
+	struct blt_copy_batch bb;
+};
+
 enum blt_surface_type {
 	SURFACE_TYPE_1D,
 	SURFACE_TYPE_2D,
@@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
 		  uint64_t ahnd,
 		  const struct blt_copy_data *blt);
 
+void blt_mem_init(int fd, struct blt_mem_data *mem);
+
+int blt_mem_copy(int fd, const intel_ctx_t *ctx,
+			 const struct intel_execution_engine2 *e,
+			 uint64_t ahnd,
+			 const struct blt_mem_data *mem);
+
+int blt_mem_set(int fd, const intel_ctx_t *ctx,
+			const struct intel_execution_engine2 *e, uint64_t ahnd,
+			const struct blt_mem_data *mem, uint8_t fill_data);
+
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
 		  uint16_t x_offset, uint16_t y_offset);
@@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
 		    uint8_t mocs_index, enum blt_tiling_type tiling,
 		    enum blt_compression compression,
 		    enum blt_compression_type compression_type);
+
+void blt_set_mem_object(struct blt_mem_object *obj,
+			uint32_t handle, uint64_t size, uint32_t pitch,
+			uint32_t width, uint32_t height, uint32_t region,
+			uint8_t mocs, enum blt_memop_type type,
+			enum blt_compression compression);
+
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
 			uint16_t surface_width, uint16_t surface_height,
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ea463376b..a8190d683 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
 #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
 
+/* RAW memory commands */
+#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
+#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
+
 #define CTXT_NO_RESTORE			(1)
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
-- 
2.39.1

Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Zbigniew Kempczyński]

On Fri, Oct 13, 2023 at 04:07:27PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Adding wrapper for mem-set and mem-copy instructions to prepare
> batch buffers and submit exec, (blt_mem_copy, blt_mem_set,
> emit_blt_mem_copy, emit_blt_set_mem)
> 
> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  lib/intel_blt.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/intel_blt.h |  39 ++++++++++
>  lib/intel_reg.h |   4 +
>  3 files changed, 242 insertions(+)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index a76c7a404..4e7357b6f 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -13,12 +13,14 @@
>  #include "igt.h"
>  #include "igt_syncobj.h"
>  #include "intel_blt.h"
> +#include "intel_mocs.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  #include "xe/xe_util.h"
>  
>  #define BITRANGE(start, end) (end - start + 1)
>  #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
> +#define MEM_COPY_MOCS_SHIFT                     25
>  
>  /* Blitter tiling definitions sanity checks */
>  static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have to match");
> @@ -1577,6 +1579,186 @@ int blt_fast_copy(int fd,
>  	return ret;
>  }
>  
> +/**
> + * blt_mem_init:
> + * @fd: drm fd
> + * @mem: structure for initialization
> + *
> + * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
> + * INTEL_DRIVER_XE).
> + */
> +void blt_mem_init(int fd, struct blt_mem_data *mem)
> +{
> +	memset(mem, 0, sizeof(*mem));
> +
> +	mem->fd = fd;
> +	mem->driver = get_intel_driver(fd);
> +}
> +
> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
> +{
> +	uint64_t dst_offset, src_offset, alignment;
> +	int i;
> +	uint32_t *batch;
> +	uint32_t optype;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
> +
> +	i = 0;
> +	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
> +	batch[i++] = mem->src.width - 1;
> +	batch[i++] = mem->src.height - 1;
> +	batch[i++] = mem->src.pitch - 1;
> +	batch[i++] = mem->dst.pitch - 1;
> +	batch[i++] = src_offset;
> +	batch[i++] = src_offset << 32;
> +	batch[i++] = dst_offset;
> +	batch[i++] = dst_offset << 32;
> +	batch[i++] = mem->src.mocs << MEM_COPY_MOCS_SHIFT | mem->dst.mocs;
> +	batch[i++] = MI_BATCH_BUFFER_END;
> +
> +	munmap(batch, mem->bb.size);
> +}
> +
> +/**
> + * blt_mem_copy:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-copy.
> + *
> + * Function does mem blit between @src and @dst described in @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +		 const struct intel_execution_engine2 *e,
> +		 uint64_t ahnd,
> +		 const struct blt_mem_data *mem)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size, alignment);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_copy(fd, ahnd, mem);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(src_offset);
> +		obj[2].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->src.handle;
> +		obj[2].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 3;
> +                execbuf.buffers_ptr = to_user_pointer(obj);
> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->src.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
> +			     uint8_t fill_data)
> +{
> +	uint64_t dst_offset, alignment;
> +	int b;
> +	uint32_t *batch;
> +	uint32_t value;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +
> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> +	value = (uint32_t)fill_data << 24;
> +
> +	b = 0;
> +	batch[b++] = MEM_SET_CMD;
> +	batch[b++] = mem->dst.width - 1;
> +	batch[b++] = mem->dst.height - 1;
> +	batch[b++] = mem->dst.pitch - 1;
> +	batch[b++] = dst_offset;
> +	batch[b++] = dst_offset << 32;
> +	batch[b++] = value | mem->dst.mocs;
> +	batch[b++] = MI_BATCH_BUFFER_END;
> +
> +	munmap(batch, mem->bb.size);
> +}
> +/**
> + * blt_mem_set:
> + * @fd: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for mem-set.
> + *
> + * Function does mem set blit in described @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +		const struct intel_execution_engine2 *e,
> +		uint64_t ahnd,
> +		const struct blt_mem_data *mem,
> +		uint8_t fill_data)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[2] = {};
> +	uint64_t dst_offset, bb_offset, alignment;
> +	int ret;
> +
> +	alignment = get_default_alignment(fd, mem->driver);
> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, alignment);
> +
> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
> +
> +	if (mem->driver == INTEL_DRIVER_XE) {
> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> +	} else {
> +		obj[0].offset = CANONICAL(dst_offset);
> +		obj[1].offset = CANONICAL(bb_offset);
> +		obj[0].handle = mem->dst.handle;
> +		obj[1].handle = mem->bb.handle;
> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +						    EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		execbuf.buffer_count = 2;
> +		execbuf.buffers_ptr = to_user_pointer(obj);
> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +		ret = __gem_execbuf(fd, &execbuf);
> +		put_offset(ahnd, mem->dst.handle);
> +		put_offset(ahnd, mem->bb.handle);
> +	}
> +
> +	return ret;
> +}
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset)
> @@ -1659,6 +1841,23 @@ void blt_set_object(struct blt_copy_object *obj,
>  	obj->compression_type = compression_type;
>  }
>  
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs, enum blt_memop_type type,
> +			enum blt_compression compression)
> +{
> +	obj->handle = handle;
> +	obj->region = region;
> +	obj->size = size;
> +	obj->mocs = mocs;
> +	obj->type = type;
> +	obj->compression = compression;
> +	obj->width = width;
> +	obj->height = height;
> +	obj->pitch = pitch;
> +}
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 7b4271620..d6f40680d 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -93,6 +93,19 @@ struct blt_copy_object {
>  	uint32_t plane_offset;
>  };
>  
> +struct blt_mem_object {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +	uint8_t mocs;

Rename to mocs_index (see gen12_block_copy_data) for consistency.

Rest looks ok. BTW looking at mem-copy I see M_MATRIX is supported
for pvc so you should update intel_cmds_info.c either.

What about printing instruction debug similar to dump_bb_fast_cmd?
(print_bb = true?).

With above nits addressed:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> +	enum blt_memop_type type;
> +	enum blt_compression compression;
> +	uint32_t width;
> +	uint32_t height;
> +	uint32_t pitch;
> +	uint32_t *ptr;
> +};
> +
>  struct blt_copy_batch {
>  	uint32_t handle;
>  	uint32_t region;
> @@ -112,6 +125,14 @@ struct blt_copy_data {
>  	bool print_bb;
>  };
>  
> +struct blt_mem_data {
> +	int fd;
> +	enum intel_driver driver;
> +	struct blt_mem_object src;
> +	struct blt_mem_object dst;
> +	struct blt_copy_batch bb;
> +};
> +
>  enum blt_surface_type {
>  	SURFACE_TYPE_1D,
>  	SURFACE_TYPE_2D,
> @@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
>  		  uint64_t ahnd,
>  		  const struct blt_copy_data *blt);
>  
> +void blt_mem_init(int fd, struct blt_mem_data *mem);
> +
> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
> +			 const struct intel_execution_engine2 *e,
> +			 uint64_t ahnd,
> +			 const struct blt_mem_data *mem);
> +
> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
> +			const struct intel_execution_engine2 *e, uint64_t ahnd,
> +			const struct blt_mem_data *mem, uint8_t fill_data);
> +
>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>  		  uint16_t x_offset, uint16_t y_offset);
> @@ -250,6 +282,13 @@ void blt_set_object(struct blt_copy_object *obj,
>  		    uint8_t mocs_index, enum blt_tiling_type tiling,
>  		    enum blt_compression compression,
>  		    enum blt_compression_type compression_type);
> +
> +void blt_set_mem_object(struct blt_mem_object *obj,
> +			uint32_t handle, uint64_t size, uint32_t pitch,
> +			uint32_t width, uint32_t height, uint32_t region,
> +			uint8_t mocs, enum blt_memop_type type,
> +			enum blt_compression compression);
> +
>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>  			uint8_t compression_format,
>  			uint16_t surface_width, uint16_t surface_height,
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ea463376b..a8190d683 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>  
> +/* RAW memory commands */
> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
> +
>  #define CTXT_NO_RESTORE			(1)
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> -- 
> 2.39.1
> 

Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch buffers and submit exec

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>Sent: Monday, October 16, 2023 2:25 PM
>To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Stolarek, Karolina
><karolina.stolarek@intel.com>
>Subject: Re: [PATCH i-g-t 1/2] lib/intel_blt: Add wrappers to prepare batch
>buffers and submit exec
>
>On Fri, Oct 13, 2023 at 04:07:27PM +0530, sai.gowtham.ch@intel.com wrote:
>> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>>
>> Adding wrapper for mem-set and mem-copy instructions to prepare batch
>> buffers and submit exec, (blt_mem_copy, blt_mem_set,
>> emit_blt_mem_copy, emit_blt_set_mem)
>>
>> Cc: Karolina Stolarek <karolina.stolarek@intel.com>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> ---
>>  lib/intel_blt.c | 199
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>  lib/intel_blt.h |  39 ++++++++++
>>  lib/intel_reg.h |   4 +
>>  3 files changed, 242 insertions(+)
>>
>> diff --git a/lib/intel_blt.c b/lib/intel_blt.c index
>> a76c7a404..4e7357b6f 100644
>> --- a/lib/intel_blt.c
>> +++ b/lib/intel_blt.c
>> @@ -13,12 +13,14 @@
>>  #include "igt.h"
>>  #include "igt_syncobj.h"
>>  #include "intel_blt.h"
>> +#include "intel_mocs.h"
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>>  #include "xe/xe_util.h"
>>
>>  #define BITRANGE(start, end) (end - start + 1)  #define
>> GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
>> +#define MEM_COPY_MOCS_SHIFT                     25
>>
>>  /* Blitter tiling definitions sanity checks */
>> static_assert(T_LINEAR == I915_TILING_NONE, "Linear definitions have
>> to match"); @@ -1577,6 +1579,186 @@ int blt_fast_copy(int fd,
>>  	return ret;
>>  }
>>
>> +/**
>> + * blt_mem_init:
>> + * @fd: drm fd
>> + * @mem: structure for initialization
>> + *
>> + * Function is zeroing @mem and sets fd and driver fields
>> +(INTEL_DRIVER_I915 or
>> + * INTEL_DRIVER_XE).
>> + */
>> +void blt_mem_init(int fd, struct blt_mem_data *mem) {
>> +	memset(mem, 0, sizeof(*mem));
>> +
>> +	mem->fd = fd;
>> +	mem->driver = get_intel_driver(fd);
>> +}
>> +
>> +static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct
>> +blt_mem_data *mem) {
>> +	uint64_t dst_offset, src_offset, alignment;
>> +	int i;
>> +	uint32_t *batch;
>> +	uint32_t optype;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
>> +
>> +	i = 0;
>> +	batch[i++] = MEM_COPY_CMD | (1 << 19) | optype;
>> +	batch[i++] = mem->src.width - 1;
>> +	batch[i++] = mem->src.height - 1;
>> +	batch[i++] = mem->src.pitch - 1;
>> +	batch[i++] = mem->dst.pitch - 1;
>> +	batch[i++] = src_offset;
>> +	batch[i++] = src_offset << 32;
>> +	batch[i++] = dst_offset;
>> +	batch[i++] = dst_offset << 32;
>> +	batch[i++] = mem->src.mocs << MEM_COPY_MOCS_SHIFT | mem-
>>dst.mocs;
>> +	batch[i++] = MI_BATCH_BUFFER_END;
>> +
>> +	munmap(batch, mem->bb.size);
>> +}
>> +
>> +/**
>> + * blt_mem_copy:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-copy.
>> + *
>> + * Function does mem blit between @src and @dst described in @blt
>object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +		 const struct intel_execution_engine2 *e,
>> +		 uint64_t ahnd,
>> +		 const struct blt_mem_data *mem)
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[3] = {};
>> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	src_offset = get_offset(ahnd, mem->src.handle, mem->src.size,
>alignment);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_copy(fd, ahnd, mem);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(src_offset);
>> +		obj[2].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->src.handle;
>> +		obj[2].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +			EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[2].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 3;
>> +                execbuf.buffers_ptr = to_user_pointer(obj);
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->src.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct
>blt_mem_data *mem,
>> +			     uint8_t fill_data)
>> +{
>> +	uint64_t dst_offset, alignment;
>> +	int b;
>> +	uint32_t *batch;
>> +	uint32_t value;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>> +alignment);
>> +
>> +	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>> +	value = (uint32_t)fill_data << 24;
>> +
>> +	b = 0;
>> +	batch[b++] = MEM_SET_CMD;
>> +	batch[b++] = mem->dst.width - 1;
>> +	batch[b++] = mem->dst.height - 1;
>> +	batch[b++] = mem->dst.pitch - 1;
>> +	batch[b++] = dst_offset;
>> +	batch[b++] = dst_offset << 32;
>> +	batch[b++] = value | mem->dst.mocs;
>> +	batch[b++] = MI_BATCH_BUFFER_END;
>> +
>> +	munmap(batch, mem->bb.size);
>> +}
>> +/**
>> + * blt_mem_set:
>> + * @fd: drm fd
>> + * @ctx: intel_ctx_t context
>> + * @e: blitter engine for @ctx
>> + * @ahnd: allocator handle
>> + * @blt: blitter data for mem-set.
>> + *
>> + * Function does mem set blit in described @blt object.
>> + *
>> + * Returns:
>> + * execbuffer status.
>> + */
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +		const struct intel_execution_engine2 *e,
>> +		uint64_t ahnd,
>> +		const struct blt_mem_data *mem,
>> +		uint8_t fill_data)
>> +{
>> +	struct drm_i915_gem_execbuffer2 execbuf = {};
>> +	struct drm_i915_gem_exec_object2 obj[2] = {};
>> +	uint64_t dst_offset, bb_offset, alignment;
>> +	int ret;
>> +
>> +	alignment = get_default_alignment(fd, mem->driver);
>> +	dst_offset = get_offset(ahnd, mem->dst.handle, mem->dst.size,
>alignment);
>> +	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size,
>> +alignment);
>> +
>> +	emit_blt_mem_set(fd, ahnd, mem, fill_data);
>> +
>> +	if (mem->driver == INTEL_DRIVER_XE) {
>> +		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
>> +	} else {
>> +		obj[0].offset = CANONICAL(dst_offset);
>> +		obj[1].offset = CANONICAL(bb_offset);
>> +		obj[0].handle = mem->dst.handle;
>> +		obj[1].handle = mem->bb.handle;
>> +		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
>> +
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		obj[1].flags = EXEC_OBJECT_PINNED |
>EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +		execbuf.buffer_count = 2;
>> +		execbuf.buffers_ptr = to_user_pointer(obj);
>> +		execbuf.rsvd1 = ctx ? ctx->id : 0;
>> +		execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> +		ret = __gem_execbuf(fd, &execbuf);
>> +		put_offset(ahnd, mem->dst.handle);
>> +		put_offset(ahnd, mem->bb.handle);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset) @@ -1659,6 +1841,23
>@@ void
>> blt_set_object(struct blt_copy_object *obj,
>>  	obj->compression_type = compression_type;  }
>>
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs, enum blt_memop_type type,
>> +			enum blt_compression compression)
>> +{
>> +	obj->handle = handle;
>> +	obj->region = region;
>> +	obj->size = size;
>> +	obj->mocs = mocs;
>> +	obj->type = type;
>> +	obj->compression = compression;
>> +	obj->width = width;
>> +	obj->height = height;
>> +	obj->pitch = pitch;
>> +}
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_blt.h b/lib/intel_blt.h index 7b4271620..d6f40680d 100644
>> --- a/lib/intel_blt.h
>> +++ b/lib/intel_blt.h
>> @@ -93,6 +93,19 @@ struct blt_copy_object {
>>  	uint32_t plane_offset;
>>  };
>>
>> +struct blt_mem_object {
>> +	uint32_t handle;
>> +	uint32_t region;
>> +	uint64_t size;
>> +	uint8_t mocs;
>
>Rename to mocs_index (see gen12_block_copy_data) for consistency.
>
>Rest looks ok. BTW looking at mem-copy I see M_MATRIX is supported for pvc
>so you should update intel_cmds_info.c either.
Missed it, good observation. Adding M_MATRIX.
>
>What about printing instruction debug similar to dump_bb_fast_cmd?
>(print_bb = true?).
I feel this can be added as enhancement later, after merging this series. 

Will be merging this series with above fixes.

Thanks,
Gowtham
>
>With above nits addressed:
>
>Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>
>--
>Zbigniew
>
>> +	enum blt_memop_type type;
>> +	enum blt_compression compression;
>> +	uint32_t width;
>> +	uint32_t height;
>> +	uint32_t pitch;
>> +	uint32_t *ptr;
>> +};
>> +
>>  struct blt_copy_batch {
>>  	uint32_t handle;
>>  	uint32_t region;
>> @@ -112,6 +125,14 @@ struct blt_copy_data {
>>  	bool print_bb;
>>  };
>>
>> +struct blt_mem_data {
>> +	int fd;
>> +	enum intel_driver driver;
>> +	struct blt_mem_object src;
>> +	struct blt_mem_object dst;
>> +	struct blt_copy_batch bb;
>> +};
>> +
>>  enum blt_surface_type {
>>  	SURFACE_TYPE_1D,
>>  	SURFACE_TYPE_2D,
>> @@ -231,6 +252,17 @@ int blt_fast_copy(int fd,
>>  		  uint64_t ahnd,
>>  		  const struct blt_copy_data *blt);
>>
>> +void blt_mem_init(int fd, struct blt_mem_data *mem);
>> +
>> +int blt_mem_copy(int fd, const intel_ctx_t *ctx,
>> +			 const struct intel_execution_engine2 *e,
>> +			 uint64_t ahnd,
>> +			 const struct blt_mem_data *mem);
>> +
>> +int blt_mem_set(int fd, const intel_ctx_t *ctx,
>> +			const struct intel_execution_engine2 *e, uint64_t
>ahnd,
>> +			const struct blt_mem_data *mem, uint8_t fill_data);
>> +
>>  void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
>>  		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
>>  		  uint16_t x_offset, uint16_t y_offset); @@ -250,6 +282,13 @@
>void
>> blt_set_object(struct blt_copy_object *obj,
>>  		    uint8_t mocs_index, enum blt_tiling_type tiling,
>>  		    enum blt_compression compression,
>>  		    enum blt_compression_type compression_type);
>> +
>> +void blt_set_mem_object(struct blt_mem_object *obj,
>> +			uint32_t handle, uint64_t size, uint32_t pitch,
>> +			uint32_t width, uint32_t height, uint32_t region,
>> +			uint8_t mocs, enum blt_memop_type type,
>> +			enum blt_compression compression);
>> +
>>  void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
>>  			uint8_t compression_format,
>>  			uint16_t surface_width, uint16_t surface_height, diff --
>git
>> a/lib/intel_reg.h b/lib/intel_reg.h index ea463376b..a8190d683 100644
>> --- a/lib/intel_reg.h
>> +++ b/lib/intel_reg.h
>> @@ -2588,6 +2588,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
>THE SOFTWARE.
>>  #define   XY_FAST_COPY_COLOR_DEPTH_64			(4  << 24)
>>  #define   XY_FAST_COPY_COLOR_DEPTH_128			(5  << 24)
>>
>> +/* RAW memory commands */
>> +#define MEM_COPY_CMD                    ((0x2 << 29)|(0x5a << 22)|0x8)
>> +#define MEM_SET_CMD                     ((0x2 << 29)|(0x5b << 22)|0x5)
>> +
>>  #define CTXT_NO_RESTORE			(1)
>>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>> --
>> 2.39.1
>>