From: Hersen Wu <hersenxs.wu@amd.com>
To: <igt-dev@lists.freedesktop.org>, <rodrigo.siqueira@amd.com>,
<aurabindo.pillai@amd.com>, <alex.hung@amd.com>,
<hamza.mahfooz@amd.com>, <wayne.lin@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>, markyacoub@google.com
Subject: [PATCH 3/3] [i-g-t] tests/amdgpu/amd_ilr: Fix psr edp rx crc read timeout
Date: Thu, 18 Jan 2024 08:14:54 -0500 [thread overview]
Message-ID: <20240118131454.19652-3-hersenxs.wu@amd.com> (raw)
In-Reply-To: <20240118131454.19652-1-hersenxs.wu@amd.com>
With debugfs disallow_edp_enter_psr, disable edp
psr before tx read rx crc.
With set_all_output_pipe_to_none of test_init,
tx write dpcd 0x600=2. this will let dpcd 0x170=0.
rx psr and crc check for rx internal logic are disabled.
with disallow_edp_enter_psr, when set test patterns
are committed by igt_display_commit_atomic, kernel
driver will turn on edp with dpcd 0x170=0. then tx
read rx crc successfully.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
---
tests/amdgpu/amd_ilr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/tests/amdgpu/amd_ilr.c b/tests/amdgpu/amd_ilr.c
index b2c0f294d..8e892738f 100644
--- a/tests/amdgpu/amd_ilr.c
+++ b/tests/amdgpu/amd_ilr.c
@@ -205,11 +205,31 @@ static void test_flow(data_t *data, enum sub_test option)
continue;
}
+ /* igt_amd_output_has_ilr_setting check if debugfs exist,
+ * but ilr settings could be all 0s -- not supported.
+ * need check if ilr settings values are supported.
+ */
+ igt_amd_read_ilr_setting(data->drm_fd, output->name, data->supported_ilr);
+ if (data->supported_ilr[0] == 0)
+ continue;
+
igt_info("Testing on output: %s\n", output->name);
/* Init only if display supports ilr link settings */
test_init(data, output);
+ /* with set_all_output_pipe_to_none within test_init,
+ * kernel driver tx write dpcd 0x600=2 to rx. edp rx
+ * exit psr state and stop verify crc from main link.
+ * with disable edp enter psr within kernel, when run
+ * set test pattern, display is turned on. kernel driver
+ * tx will not notify rx psr enable and crc checking by
+ * rx. by this, when tx want to read crc from rx, rx will
+ * check crc and response right away. timeout will not
+ * happens.
+ */
+ igt_amd_disallow_edp_enter_psr(data->drm_fd, output->name, true);
+
mode = igt_output_get_mode(output);
igt_assert(mode);
@@ -243,6 +263,9 @@ static void test_flow(data_t *data, enum sub_test option)
igt_remove_fb(data->drm_fd, &data->fb);
test_fini(data);
+
+ /* restore allow kernel driver eDP PSR */
+ igt_amd_disallow_edp_enter_psr(data->drm_fd, output->name, false);
}
}
--
2.25.1
next prev parent reply other threads:[~2024-01-18 13:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 13:14 [PATCH 1/3] [i-g-t] lib/igt_amd: add debugfs disallow edp enter psr Hersen Wu
2024-01-18 13:14 ` [PATCH 2/3] [i-g-t] tests/amdgpu/amd_bypass: Fix psr edp r/x crc read timeout Hersen Wu
2024-01-18 13:14 ` Hersen Wu [this message]
2024-01-18 15:03 ` [PATCH 1/3] [i-g-t] lib/igt_amd: add debugfs disallow edp enter psr Lin, Wayne
2024-01-18 16:40 ` ✗ Fi.CI.BAT: failure for series starting with [1/3,i-g-t] " Patchwork
2024-01-18 16:47 ` ✓ CI.xeBAT: success " Patchwork
2024-01-22 14:49 ` ✓ CI.xeBAT: success for series starting with [1/3,i-g-t] lib/igt_amd: add debugfs disallow edp enter psr (rev2) Patchwork
2024-01-22 15:09 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-01-23 14:44 ` ✓ CI.xeBAT: success for series starting with [1/3,i-g-t] lib/igt_amd: add debugfs disallow edp enter psr (rev3) Patchwork
2024-01-23 14:52 ` ✓ Fi.CI.BAT: " Patchwork
2024-01-23 19:19 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2024-01-18 2:36 [PATCH 1/3] [i-g-t] lib/igt_amd: add debugfs disallow edp enter psr Hersen Wu
2024-01-18 2:36 ` [PATCH 3/3] [i-g-t] tests/amdgpu/amd_ilr: Fix psr edp rx crc read timeout Hersen Wu
2024-01-18 10:16 ` Lin, Wayne
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