[PATCH i-g-t v2 1/6] lib/rendercopy_gen9: use MOCS index helper

[PATCH i-g-t v2 1/6] lib/rendercopy_gen9: use MOCS index helper

[Matthew Auld]

UC looks to be the sensible default here, since it will work with
display engine if rendering onto scanout surface. Use the matching
helper.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
 lib/rendercopy_gen9.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index efd7cb37c..404406e5f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -180,10 +180,7 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 	ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/
 
 	if (HAS_4TILE(ibb->devid)) {
-		/*
-		 * mocs table version 1 index 3 groub wb use l3
-		 */
-		ss->ss1.mocs_index = 3;
+		ss->ss1.mocs_index = intel_get_uc_mocs_index(i915);
 		ss->ss5.mip_tail_start_lod = 0;
 	} else {
 		ss->ss0.render_cache_read_write = 1;
-- 
2.43.2

[PATCH i-g-t v2 2/6] lib/gpu_cmds: default to uc MOCS index

[Matthew Auld]

Currently we just default to index=0, but that can have different
meaning between HW versions. Rather just default to UC mocs index.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/gpu_cmds.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 49ba364f9..d909efde8 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -214,10 +214,10 @@ gen9_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = 1; /* align 4 */
 	ss->ss0.horizontal_alignment = 1; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_UC)
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
-	else if (mocs == INTEL_BUF_MOCS_WB)
+	if (mocs == INTEL_BUF_MOCS_WB)
 		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
+	else
+		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
@@ -275,10 +275,10 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
 	ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_UC)
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
-	else if (mocs == INTEL_BUF_MOCS_WB)
+	if (mocs == INTEL_BUF_MOCS_WB)
 		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
+	else
+		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
@@ -931,10 +931,10 @@ xehp_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = 1; /* align 4 */
 	ss->ss0.horizontal_alignment = 1; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_UC)
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
-	else if (mocs == INTEL_BUF_MOCS_WB)
+	if (mocs == INTEL_BUF_MOCS_WB)
 		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
+	else
+		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
-- 
2.43.2

[PATCH i-g-t v2 3/6] lib/intel_buf: revamp MOCS usage

[Matthew Auld]

We want to allow the caller the set any valid MOCS index as part of the
the intel_buf. Drop the MOCS enum in favour of raw mocs_index. Also drop
the getter/setter interface, for which there are no current callers for
the setter part. In the next patch we will expose the raw mocs_index.
Should be no functional changes here.

v2 (Zbigniew):
  - Rather just pass along UC directly to lower layers.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/gpu_cmds.c        | 18 +++---------------
 lib/intel_bufops.c    |  3 ++-
 lib/intel_bufops.h    | 23 +++--------------------
 lib/rendercopy_gen9.c |  5 ++---
 4 files changed, 10 insertions(+), 39 deletions(-)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index d909efde8..da41121ce 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -194,7 +194,6 @@ gen9_fill_surface_state(struct intel_bb *ibb,
 	struct gen9_surface_state *ss;
 	uint32_t write_domain, read_domain, offset;
 	uint64_t address;
-	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
 
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
@@ -214,10 +213,7 @@ gen9_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = 1; /* align 4 */
 	ss->ss0.horizontal_alignment = 1; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_WB)
-		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
-	else
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
+	ss->ss1.mocs_index = buf->mocs_index;
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
@@ -255,7 +251,6 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 	struct gen9_surface_state *ss;
 	uint32_t write_domain, read_domain, offset;
 	uint64_t address;
-	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
 
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
@@ -275,10 +270,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
 	ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_WB)
-		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
-	else
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
+	ss->ss1.mocs_index = buf->mocs_index;
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
@@ -911,7 +903,6 @@ xehp_fill_surface_state(struct intel_bb *ibb,
 	struct xehp_surface_state *ss;
 	uint32_t write_domain, read_domain, offset;
 	uint64_t address;
-	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
 
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
@@ -931,10 +922,7 @@ xehp_fill_surface_state(struct intel_bb *ibb,
 	ss->ss0.vertical_alignment = 1; /* align 4 */
 	ss->ss0.horizontal_alignment = 1; /* align 4 */
 
-	if (mocs == INTEL_BUF_MOCS_WB)
-		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
-	else
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
+	ss->ss1.mocs_index = buf->mocs_index;
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 5e2701a7d..c34d778a1 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -29,6 +29,7 @@
 #include "igt.h"
 #include "igt_x86.h"
 #include "intel_bufops.h"
+#include "intel_mocs.h"
 #include "intel_pat.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
@@ -877,8 +878,8 @@ static void __intel_buf_init(struct buf_ops *bops,
 	buf->bpp = bpp;
 	buf->compression = compression;
 	buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
-	buf->mocs = INTEL_BUF_MOCS_DEFAULT;
 	buf->pat_index = pat_index;
+	buf->mocs_index = intel_get_uc_mocs_index(bops->fd);
 	IGT_INIT_LIST_HEAD(&buf->link);
 
 	tile_width = __get_min_stride(width, bpp, tiling);
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 363f7abaa..60f7785fe 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -12,12 +12,6 @@ struct buf_ops;
 #define INTEL_BUF_NAME_MAXSIZE 32
 #define INVALID_ADDR(x) ((x) == INTEL_BUF_INVALID_ADDRESS)
 
-enum intel_buf_mocs {
-	INTEL_BUF_MOCS_DEFAULT,
-	INTEL_BUF_MOCS_UC,
-	INTEL_BUF_MOCS_WB,
-};
-
 struct intel_buf {
 	struct buf_ops *bops;
 
@@ -31,7 +25,6 @@ struct intel_buf {
 	uint32_t compression;
 	uint32_t swizzle_mode;
 	uint32_t yuv_semiplanar_bpp;
-	enum intel_buf_mocs mocs;
 	bool format_is_yuv;
 	bool format_is_yuv_semiplanar;
 	struct {
@@ -68,6 +61,9 @@ struct intel_buf {
 	/* pat_index to use for mapping this buf. Only used in Xe. */
 	uint8_t pat_index;
 
+	/* mocs_index to use for operations using this intel_buf, like render_copy  */
+	uint8_t mocs_index;
+
 	/* For debugging purposes */
 	char name[INTEL_BUF_NAME_MAXSIZE + 1];
 };
@@ -227,17 +223,4 @@ void intel_buf_draw_pattern(struct buf_ops *bops, struct intel_buf *buf,
 			    int cx, int cy, int cw, int ch,
 			    bool use_alternate_colors);
 
-static inline enum intel_buf_mocs intel_buf_get_mocs(const struct intel_buf *buf)
-{
-	igt_assert(buf);
-	return buf->mocs;
-}
-
-static inline void intel_buf_set_mocs(struct intel_buf *buf,
-				      enum intel_buf_mocs mocs)
-{
-	igt_assert(buf);
-	buf->mocs = mocs;
-}
-
 #endif
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 404406e5f..caf4623af 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -153,7 +153,6 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 	struct gen9_surface_state *ss;
 	uint32_t write_domain, read_domain;
 	uint64_t address;
-	int i915 = buf_ops_get_fd(buf->bops);
 
 	igt_assert_lte(buf->surface[0].stride, 256*1024);
 	igt_assert_lte(intel_buf_width(buf), 16384);
@@ -179,12 +178,12 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 	ss->ss0.vertical_alignment = 1; /* align 4 */
 	ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/
 
+	ss->ss1.mocs_index = buf->mocs_index;
+
 	if (HAS_4TILE(ibb->devid)) {
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(i915);
 		ss->ss5.mip_tail_start_lod = 0;
 	} else {
 		ss->ss0.render_cache_read_write = 1;
-		ss->ss1.mocs_index = intel_get_uc_mocs_index(i915);
 		ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
 	}
 
-- 
2.43.2

[PATCH i-g-t v2 4/6] lib/intel_buf: expose mocs_index

[Matthew Auld]

Allow the caller the set the intel_buf.mocs_index as part of the usual
_full variants.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/igt_draw.c            |  7 ++++---
 lib/igt_fb.c              |  3 ++-
 lib/intel_bufops.c        | 30 ++++++++++++++++++++----------
 lib/intel_bufops.h        |  6 ++++--
 lib/intel_mocs.h          |  2 ++
 tests/intel/kms_big_fb.c  |  4 +++-
 tests/intel/kms_dirtyfb.c |  7 +++++--
 tests/intel/kms_psr.c     |  4 +++-
 tests/intel/xe_intel_bb.c |  4 +++-
 tests/intel/xe_pat.c      |  8 ++++----
 10 files changed, 50 insertions(+), 25 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 1b702e376..2c01d7b02 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -663,7 +663,8 @@ static struct intel_buf *create_buf(int fd, struct buf_ops *bops,
 				    tiling, 0,
 				    size, 0,
 				    region,
-				    from->pat_index);
+				    from->pat_index,
+				    DEFAULT_MOCS_INDEX);
 
 	/* Make sure we close handle on destroy path */
 	intel_buf_set_ownership(buf, true);
@@ -723,9 +724,9 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
 		pitch = tiling ? buf->stride / 4 : buf->stride;
 
 		if (ver >= 20)
-			mocs = intel_get_uc_mocs_index(fd) << XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
+			mocs = dst->mocs_index << XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
 		else
-			mocs = intel_get_uc_mocs_index(fd) << XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
+			mocs = dst->mocs_index << XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
 
 		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
 		intel_bb_out(ibb, blt_cmd_tiling | mocs | (pitch-1));
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 0ac2a76b0..cc70cb91c 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2642,7 +2642,8 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
 				    compression, fb->size,
 				    fb->strides[0],
 				    region,
-				    intel_get_pat_idx_uc(fd));
+				    intel_get_pat_idx_uc(fd),
+				    DEFAULT_MOCS_INDEX);
 	intel_buf_set_name(buf, name);
 
 	/* Make sure we close handle on destroy path */
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index c34d778a1..1dc25d61f 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -857,7 +857,8 @@ static void __intel_buf_init(struct buf_ops *bops,
 			     int width, int height, int bpp, int alignment,
 			     uint32_t req_tiling, uint32_t compression,
 			     uint64_t bo_size, int bo_stride,
-			     uint64_t region, uint8_t pat_index)
+			     uint64_t region, uint8_t pat_index,
+			     uint8_t mocs_index)
 {
 	uint32_t tiling = req_tiling;
 	uint64_t size;
@@ -879,7 +880,9 @@ static void __intel_buf_init(struct buf_ops *bops,
 	buf->compression = compression;
 	buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
 	buf->pat_index = pat_index;
-	buf->mocs_index = intel_get_uc_mocs_index(bops->fd);
+	if (mocs_index == DEFAULT_MOCS_INDEX)
+		mocs_index = intel_get_uc_mocs_index(bops->fd);
+	buf->mocs_index = mocs_index;
 	IGT_INIT_LIST_HEAD(&buf->link);
 
 	tile_width = __get_min_stride(width, bpp, tiling);
@@ -973,7 +976,8 @@ void intel_buf_init(struct buf_ops *bops,
 	region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY :
 						     system_memory(bops->fd);
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
-			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX);
+			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
+			 DEFAULT_MOCS_INDEX);
 
 	intel_buf_set_ownership(buf, true);
 }
@@ -990,7 +994,8 @@ void intel_buf_init_in_region(struct buf_ops *bops,
 			      uint64_t region)
 {
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
-			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX);
+			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
+			 DEFAULT_MOCS_INDEX);
 
 	intel_buf_set_ownership(buf, true);
 }
@@ -1053,7 +1058,8 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
 	igt_assert(handle);
 	igt_assert(size);
 	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
-			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX);
+			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX,
+			 DEFAULT_MOCS_INDEX);
 }
 
 /**
@@ -1071,6 +1077,8 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
  * @stride: bo stride
  * @region: region
  * @pat_index: pat_index to use for the binding (only used on xe)
+ * @pat_index: mocs_index to use for operations using this intel_buf, like render
+ * copy.
  *
  * Function configures BO handle within intel_buf structure passed by the caller
  * (with all its metadata - width, height, ...). Useful if BO was created
@@ -1089,11 +1097,12 @@ void intel_buf_init_full(struct buf_ops *bops,
 			 uint64_t size,
 			 int stride,
 			 uint64_t region,
-			 uint8_t pat_index)
+			 uint8_t pat_index,
+			 uint8_t mocs_index)
 {
 	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
 			 req_tiling, compression, size, stride, region,
-			 pat_index);
+			 pat_index, mocs_index);
 }
 
 /**
@@ -1155,7 +1164,7 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 	igt_assert(size);
 	return intel_buf_create_full(bops, handle, width, height, bpp, alignment,
 				     req_tiling, compression, size, 0, -1,
-				     DEFAULT_PAT_INDEX);
+				     DEFAULT_PAT_INDEX, DEFAULT_MOCS_INDEX);
 }
 
 struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
@@ -1167,7 +1176,8 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
 					uint64_t size,
 					int stride,
 					uint64_t region,
-					uint8_t pat_index)
+					uint8_t pat_index,
+					uint8_t mocs_index)
 {
 	struct intel_buf *buf;
 
@@ -1178,7 +1188,7 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
 
 	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
 			 req_tiling, compression, size, stride, region,
-			 pat_index);
+			 pat_index, mocs_index);
 
 	return buf;
 }
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 60f7785fe..af2009b3d 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -158,7 +158,8 @@ void intel_buf_init_full(struct buf_ops *bops,
 			 uint64_t size,
 			 int stride,
 			 uint64_t region,
-			 uint8_t pat_index);
+			 uint8_t pat_index,
+			 uint8_t mocs_index);
 
 struct intel_buf *intel_buf_create(struct buf_ops *bops,
 				   int width, int height,
@@ -191,7 +192,8 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
 					uint64_t size,
 					int stride,
 					uint64_t region,
-					uint8_t pat_index);
+					uint8_t pat_index,
+					uint8_t mocs_index);
 void intel_buf_destroy(struct intel_buf *buf);
 
 static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
index a9e075273..b5c79b0e1 100644
--- a/lib/intel_mocs.h
+++ b/lib/intel_mocs.h
@@ -8,6 +8,8 @@
 
 #include <stdint.h>
 
+#define DEFAULT_MOCS_INDEX ((uint8_t)-1)
+
 uint8_t intel_get_wb_mocs_index(int fd);
 uint8_t intel_get_uc_mocs_index(int fd);
 
diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c
index 0bd79394b..f7f303d41 100644
--- a/tests/intel/kms_big_fb.c
+++ b/tests/intel/kms_big_fb.c
@@ -37,6 +37,7 @@
 #include <string.h>
 
 #include "i915/gem_create.h"
+#include "intel_mocs.h"
 #include "intel_pat.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
@@ -206,7 +207,8 @@ static struct intel_buf *init_buf(data_t *data,
 	buf = intel_buf_create_full(data->bops, handle, width, height,
 				    bpp, 0, tiling, 0, size, 0,
 				    region,
-				    intel_get_pat_idx_uc(data->drm_fd));
+				    intel_get_pat_idx_uc(data->drm_fd),
+				    DEFAULT_MOCS_INDEX);
 
 	intel_buf_set_name(buf, buf_name);
 	intel_buf_set_ownership(buf, true);
diff --git a/tests/intel/kms_dirtyfb.c b/tests/intel/kms_dirtyfb.c
index 9aa066004..9e4832929 100644
--- a/tests/intel/kms_dirtyfb.c
+++ b/tests/intel/kms_dirtyfb.c
@@ -20,6 +20,7 @@
 
 #include "i915/intel_drrs.h"
 #include "i915/intel_fbc.h"
+#include "intel_mocs.h"
 #include "intel_pat.h"
 
 #include "xe/xe_query.h"
@@ -256,7 +257,8 @@ static void run_test(data_t *data)
 				    igt_fb_mod_to_tiling(data->fbs[1].modifier),
 				    0, data->fbs[1].size, 0, is_xe_device(data->drm_fd) ?
 				    system_memory(data->drm_fd) : 0,
-				    intel_get_pat_idx_uc(data->drm_fd));
+				    intel_get_pat_idx_uc(data->drm_fd),
+				    DEFAULT_MOCS_INDEX);
 	dst = intel_buf_create_full(data->bops, data->fbs[2].gem_handle,
 				    data->fbs[2].width,
 				    data->fbs[2].height,
@@ -264,7 +266,8 @@ static void run_test(data_t *data)
 				    0, igt_fb_mod_to_tiling(data->fbs[2].modifier),
 				    0, data->fbs[2].size, 0, is_xe_device(data->drm_fd) ?
 				    system_memory(data->drm_fd) : 0,
-				    intel_get_pat_idx_uc(data->drm_fd));
+				    intel_get_pat_idx_uc(data->drm_fd),
+				    DEFAULT_MOCS_INDEX);
 	ibb = intel_bb_create(data->drm_fd, PAGE_SIZE);
 
 	spin = igt_spin_new(data->drm_fd, .ahnd = ibb->allocator_handle);
diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c
index 3822b3081..c90612426 100644
--- a/tests/intel/kms_psr.c
+++ b/tests/intel/kms_psr.c
@@ -35,6 +35,7 @@
 #include "igt.h"
 #include "igt_sysfs.h"
 #include "igt_psr.h"
+#include "intel_mocs.h"
 #include "intel_pat.h"
 #include <errno.h>
 #include <stdbool.h>
@@ -421,7 +422,8 @@ static struct intel_buf *create_buf_from_fb(data_t *data,
 	handle = gem_open(data->drm_fd, name);
 	buf = intel_buf_create_full(data->bops, handle, width, height,
 				    bpp, 0, tiling, 0, size, stride, region,
-				    intel_get_pat_idx_uc(data->drm_fd));
+				    intel_get_pat_idx_uc(data->drm_fd),
+				    DEFAULT_MOCS_INDEX);
 	intel_buf_set_ownership(buf, true);
 
 	return buf;
diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
index c3a4b5450..09164c41f 100644
--- a/tests/intel/xe_intel_bb.c
+++ b/tests/intel/xe_intel_bb.c
@@ -19,6 +19,7 @@
 #include "igt.h"
 #include "igt_crc.h"
 #include "intel_bufops.h"
+#include "intel_mocs.h"
 #include "intel_pat.h"
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
@@ -393,7 +394,8 @@ static void create_in_region(struct buf_ops *bops, uint64_t region)
 	intel_buf_init_full(bops, handle, &buf,
 			    width/4, height, 32, 0,
 			    I915_TILING_NONE, 0,
-			    size, 0, region, DEFAULT_PAT_INDEX);
+			    size, 0, region, DEFAULT_PAT_INDEX,
+			    DEFAULT_MOCS_INDEX);
 	intel_buf_set_ownership(&buf, true);
 
 	intel_bb_add_intel_buf(ibb, &buf, false);
diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 3d7d7400c..6918ebe7e 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -388,11 +388,11 @@ static void pat_index_render(struct xe_pat_param *p)
 
 	intel_buf_init_full(bops, p->r1_bo, &src, width, height, bpp, 0,
 			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
-			    stride, p->r1, p->r1_pat_index);
+			    stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
 
 	intel_buf_init_full(bops, p->r2_bo, &dst, width, height, bpp, 0,
 			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
-			    stride, p->r2, p->r2_pat_index);
+			    stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
 
 	/* Ensure we always see zeroes for the initial KMD zeroing */
 	render_copy(ibb,
@@ -483,12 +483,12 @@ static void pat_index_dw(struct xe_pat_param *p)
 
 	intel_buf_init_full(bops, p->r1_bo, &r1_buf, width, height, bpp, 0,
 			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
-			    stride, p->r1, p->r1_pat_index);
+			    stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
 	intel_bb_add_intel_buf(ibb, &r1_buf, true);
 
 	intel_buf_init_full(bops, p->r2_bo, &r2_buf, width, height, bpp, 0,
 			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
-			    stride, p->r2, p->r2_pat_index);
+			    stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
 	intel_bb_add_intel_buf(ibb, &r2_buf, true);
 
 	/*
-- 
2.43.2

[PATCH i-g-t v2 5/6] lib/intel_mocs: add defer-to-pat-index

[Matthew Auld]

At least on Xe2 it looks like we can just use MOCS index zero to defer
the selected caching mode to that of the PAT index. This will be useful
in an upcoming patch.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_mocs.c | 14 ++++++++++++++
 lib/intel_mocs.h |  1 +
 2 files changed, 15 insertions(+)

diff --git a/lib/intel_mocs.c b/lib/intel_mocs.c
index 4a9c305dc..bf6ee1958 100644
--- a/lib/intel_mocs.c
+++ b/lib/intel_mocs.c
@@ -9,6 +9,7 @@
 struct drm_intel_mocs_index {
 	uint8_t uc_index;
 	uint8_t wb_index;
+	uint8_t deferred_index;
 };
 
 static void get_mocs_index(int fd, struct drm_intel_mocs_index *mocs)
@@ -25,6 +26,7 @@ static void get_mocs_index(int fd, struct drm_intel_mocs_index *mocs)
 	if (intel_graphics_ver(devid) >= IP_VER(20, 0)) {
 		mocs->uc_index = 3;
 		mocs->wb_index = 4;
+		mocs->deferred_index = 0;
 	} else if (IS_METEORLAKE(devid)) {
 		mocs->uc_index = 5;
 		mocs->wb_index = 10;
@@ -60,3 +62,15 @@ uint8_t intel_get_uc_mocs_index(int fd)
 
 	return mocs.uc_index;
 }
+
+uint8_t intel_get_deferred_mocs_index(int fd)
+{
+	struct drm_intel_mocs_index mocs;
+	uint16_t dev_id = intel_get_drm_devid(fd);
+
+	igt_assert(AT_LEAST_GEN(dev_id, 20));
+
+	get_mocs_index(fd, &mocs);
+
+	return mocs.deferred_index;
+}
diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
index b5c79b0e1..bfdc23210 100644
--- a/lib/intel_mocs.h
+++ b/lib/intel_mocs.h
@@ -12,5 +12,6 @@
 
 uint8_t intel_get_wb_mocs_index(int fd);
 uint8_t intel_get_uc_mocs_index(int fd);
+uint8_t intel_get_deferred_mocs_index(int fd);
 
 #endif /* _INTEL_MOCS_H */
-- 
2.43.2

[PATCH i-g-t v2 6/6] tests/intel/xe_pat: verify wb-transient with pipe crc

[Matthew Auld]

On Xe2 using the L3:XD (wb-transient) caching mode, which is intended
for display use, verify we don't observe display corruption when
rendering unto the display surface. Transient cache entries should be
flushed by the time we do the flip, if not we will detect pipe crc
mismatch vs reference fb.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
 tests/intel/xe_pat.c | 121 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 6918ebe7e..9523cee4e 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -10,6 +10,8 @@
  * Functionality: pat_index
  */
 
+#include <fcntl.h>
+
 #include "igt.h"
 #include "igt_vgem.h"
 #include "intel_blt.h"
@@ -722,6 +724,122 @@ static void prime_external_import_coh(void)
 	drm_close_driver(fd2);
 }
 
+/**
+ * SUBTEST: display-vs-wb-transient
+ * Test category: functionality test
+ * Description: Scanout with dirty L3:XD
+ */
+static void display_vs_wb_transient(int fd)
+{
+	uint16_t pat_index_modes[] = {
+		3, /* UC (baseline) */
+		6, /* L3:XD (uncompressed) */
+	};
+	uint32_t devid = intel_get_drm_devid(fd);
+	igt_render_copyfunc_t render_copy = NULL;
+	igt_crc_t ref_crc = {}, crc = {};
+	igt_plane_t *primary;
+	igt_display_t display;
+	igt_output_t *output;
+	igt_pipe_crc_t *pipe_crc;
+	drmModeModeInfoPtr mode;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
+	struct igt_fb src_fb, dst_fb;
+	struct intel_buf src, dst;
+	enum pipe pipe;
+	int bpp = 32;
+	int i;
+
+	igt_require(intel_get_device_info(devid)->graphics_ver >= 20);
+
+	render_copy = igt_get_render_copyfunc(devid);
+	igt_require(render_copy);
+	igt_require(xe_has_engine_class(fd, DRM_XE_ENGINE_CLASS_RENDER));
+
+	igt_display_require(&display, fd);
+	igt_display_require_output(&display);
+	kmstest_set_vt_graphics_mode();
+
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, SZ_4K);
+
+	for_each_pipe_with_valid_output(&display, pipe, output) {
+		igt_display_reset(&display);
+
+		igt_output_set_pipe(output, pipe);
+		if (!intel_pipe_output_combo_valid(&display))
+			continue;
+
+		mode = igt_output_get_mode(output);
+		pipe_crc = igt_pipe_crc_new(fd, pipe, IGT_PIPE_CRC_SOURCE_AUTO);
+		break;
+	}
+
+	primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+
+	igt_create_fb(fd, mode->hdisplay, mode->vdisplay,
+		      DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, &src_fb);
+	igt_draw_fill_fb(fd, &src_fb, 0xFF);
+
+	igt_plane_set_fb(primary, &src_fb);
+	igt_assert_eq(igt_display_commit2(&display, COMMIT_ATOMIC), 0);
+	igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
+
+	intel_buf_init_full(bops, src_fb.gem_handle, &src, src_fb.width,
+			    src_fb.height, bpp, 0, I915_TILING_NONE,
+			    I915_COMPRESSION_NONE, src_fb.size,
+			    src_fb.strides[0], 0, DEFAULT_PAT_INDEX,
+			    DEFAULT_MOCS_INDEX);
+
+	for (i = 0; i < ARRAY_SIZE(pat_index_modes); i++) {
+		int fw_handle;
+
+		igt_create_fb(fd, mode->hdisplay, mode->vdisplay,
+			      DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_LINEAR, &dst_fb);
+
+		intel_buf_init_full(bops, dst_fb.gem_handle, &dst,
+				    dst_fb.width, dst_fb.height, bpp, 0,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE,
+				    dst_fb.size, dst_fb.strides[0], 0,
+				    pat_index_modes[i],
+				    intel_get_deferred_mocs_index(fd));
+
+		/* c0 -> c6 might flush caches */
+		fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY);
+		igt_assert(fw_handle >= 0);
+
+		render_copy(ibb,
+			    &src,
+			    0, 0, dst_fb.width, dst_fb.height,
+			    &dst,
+			    0, 0);
+		intel_bb_sync(ibb);
+
+		/*
+		 * Display engine is not coherent with GPU/CPU caches, however
+		 * with new L3:XD caching mode, the GPU cache entries marked as
+		 * transient should be automatically flushed by the time we do
+		 * the flip.
+		 */
+
+		igt_plane_set_fb(primary, &dst_fb);
+		igt_assert_eq(igt_display_commit2(&display, COMMIT_ATOMIC), 0);
+		igt_pipe_crc_collect_crc(pipe_crc, &crc);
+
+		igt_assert_crc_equal(&crc, &ref_crc);
+
+		intel_bb_reset(ibb, false);
+
+		intel_buf_close(dst.bops, &dst);
+		igt_remove_fb(fd, &dst_fb);
+		close(fw_handle);
+	}
+
+	igt_remove_fb(fd, &src_fb);
+	intel_bb_destroy(ibb);
+}
+
 static uint8_t get_pat_idx_uc(int fd, bool *compressed)
 {
 	if (compressed)
@@ -1054,6 +1172,9 @@ igt_main_args("V", NULL, help_str, opt_handler, NULL)
 						     ARRAY_SIZE(xe2_pat_index_modes));
 	}
 
+	igt_subtest("display-vs-wb-transient")
+		display_vs_wb_transient(fd);
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.43.2

✓ CI.xeBAT: success for series starting with [i-g-t,v2,1/6] lib/rendercopy_gen9: use MOCS index helper

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1007 bytes --]

== Series Details ==

Series: series starting with [i-g-t,v2,1/6] lib/rendercopy_gen9: use MOCS index helper
URL   : https://patchwork.freedesktop.org/series/130736/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7746_BAT -> XEIGTPW_10778_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_7746 -> IGTPW_10778
  * Linux: xe-897-98da761379cfaa31b32641ad648f83c90a8e629e -> xe-898-1d6fe19a74ebc7356b6cbed32aa1dedb215b4aff

  IGTPW_10778: 10778
  IGT_7746: 7746
  xe-897-98da761379cfaa31b32641ad648f83c90a8e629e: 98da761379cfaa31b32641ad648f83c90a8e629e
  xe-898-1d6fe19a74ebc7356b6cbed32aa1dedb215b4aff: 1d6fe19a74ebc7356b6cbed32aa1dedb215b4aff

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10778/index.html

[-- Attachment #2: Type: text/html, Size: 1566 bytes --]

✗ Fi.CI.BAT: failure for series starting with [i-g-t,v2,1/6] lib/rendercopy_gen9: use MOCS index helper

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4817 bytes --]

== Series Details ==

Series: series starting with [i-g-t,v2,1/6] lib/rendercopy_gen9: use MOCS index helper
URL   : https://patchwork.freedesktop.org/series/130736/
State : failure

== Summary ==

CI Bug Log - changes from IGT_7746 -> IGTPW_10778
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_10778 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_10778, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/index.html

Participating hosts (40 -> 39)
------------------------------

  Additional (1): bat-kbl-2 
  Missing    (2): bat-jsl-1 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_10778:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@module-reload:
    - bat-arls-2:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/bat-arls-2/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-arls-2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gem_contexts:
    - bat-dg2-8:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gtt:
    - bat-dg2-11:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/bat-dg2-11/igt@i915_selftest@live@gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-dg2-11/igt@i915_selftest@live@gtt.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
Known issues
------------

  Here are the changes found in IGTPW_10778 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - bat-kbl-2:          NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1849])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-kbl-2/igt@fbdev@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-kbl-2:          NOTRUN -> [SKIP][10] ([fdo#109271]) +39 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][11] -> [ABORT][12] ([i915#9662])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-1:
    - fi-kbl-7567u:       NOTRUN -> [SKIP][13] ([fdo#109271])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/fi-kbl-7567u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-1.html

  
#### Warnings ####

  * igt@kms_chamelium_edid@dp-edid-read:
    - bat-dg2-13:         [FAIL][14] ([i915#10293]) -> [SKIP][15] ([Intel XE#484])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7746/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html

  
  [Intel XE#484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/484
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#10293]: https://gitlab.freedesktop.org/drm/intel/issues/10293
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#9662]: https://gitlab.freedesktop.org/drm/intel/issues/9662


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7746 -> IGTPW_10778

  CI-20190529: 20190529
  CI_DRM_14388: 1d6fe19a74ebc7356b6cbed32aa1dedb215b4aff @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_10778: 10778
  IGT_7746: 7746


Testlist changes
----------------

+igt@xe_pat@display-vs-wb-transient
-igt@xe_render_copy@render-full
-igt@xe_render_copy@render-hstripes
-igt@xe_render_copy@render-random
-igt@xe_render_copy@render-square
-igt@xe_render_copy@render-vstripes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10778/index.html

[-- Attachment #2: Type: text/html, Size: 5812 bytes --]

Re: [PATCH i-g-t v2 2/6] lib/gpu_cmds: default to uc MOCS index

[Zbigniew Kempczyński]

On Tue, Mar 05, 2024 at 12:17:50PM +0000, Matthew Auld wrote:
> Currently we just default to index=0, but that can have different
> meaning between HW versions. Rather just default to UC mocs index.

Makes sense to me:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/gpu_cmds.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index 49ba364f9..d909efde8 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -214,10 +214,10 @@ gen9_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
>  	ss->ss0.horizontal_alignment = 1; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_UC)
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> -	else if (mocs == INTEL_BUF_MOCS_WB)
> +	if (mocs == INTEL_BUF_MOCS_WB)
>  		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> +	else
> +		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> @@ -275,10 +275,10 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
>  	ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_UC)
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> -	else if (mocs == INTEL_BUF_MOCS_WB)
> +	if (mocs == INTEL_BUF_MOCS_WB)
>  		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> +	else
> +		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> @@ -931,10 +931,10 @@ xehp_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
>  	ss->ss0.horizontal_alignment = 1; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_UC)
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> -	else if (mocs == INTEL_BUF_MOCS_WB)
> +	if (mocs == INTEL_BUF_MOCS_WB)
>  		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> +	else
> +		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> -- 
> 2.43.2
> 

Re: [PATCH i-g-t v2 3/6] lib/intel_buf: revamp MOCS usage

[Zbigniew Kempczyński]

On Tue, Mar 05, 2024 at 12:17:51PM +0000, Matthew Auld wrote:
> We want to allow the caller the set any valid MOCS index as part of the
> the intel_buf. Drop the MOCS enum in favour of raw mocs_index. Also drop
> the getter/setter interface, for which there are no current callers for
> the setter part. In the next patch we will expose the raw mocs_index.
> Should be no functional changes here.
> 
> v2 (Zbigniew):
>   - Rather just pass along UC directly to lower layers.
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/gpu_cmds.c        | 18 +++---------------
>  lib/intel_bufops.c    |  3 ++-
>  lib/intel_bufops.h    | 23 +++--------------------
>  lib/rendercopy_gen9.c |  5 ++---
>  4 files changed, 10 insertions(+), 39 deletions(-)
> 
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index d909efde8..da41121ce 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -194,7 +194,6 @@ gen9_fill_surface_state(struct intel_bb *ibb,
>  	struct gen9_surface_state *ss;
>  	uint32_t write_domain, read_domain, offset;
>  	uint64_t address;
> -	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
>  
>  	if (is_dst) {
>  		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
> @@ -214,10 +213,7 @@ gen9_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
>  	ss->ss0.horizontal_alignment = 1; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_WB)
> -		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> -	else
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> +	ss->ss1.mocs_index = buf->mocs_index;
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> @@ -255,7 +251,6 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>  	struct gen9_surface_state *ss;
>  	uint32_t write_domain, read_domain, offset;
>  	uint64_t address;
> -	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
>  
>  	if (is_dst) {
>  		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
> @@ -275,10 +270,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
>  	ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_WB)
> -		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> -	else
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> +	ss->ss1.mocs_index = buf->mocs_index;
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> @@ -911,7 +903,6 @@ xehp_fill_surface_state(struct intel_bb *ibb,
>  	struct xehp_surface_state *ss;
>  	uint32_t write_domain, read_domain, offset;
>  	uint64_t address;
> -	enum intel_buf_mocs mocs = intel_buf_get_mocs(buf);
>  
>  	if (is_dst) {
>  		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
> @@ -931,10 +922,7 @@ xehp_fill_surface_state(struct intel_bb *ibb,
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
>  	ss->ss0.horizontal_alignment = 1; /* align 4 */
>  
> -	if (mocs == INTEL_BUF_MOCS_WB)
> -		ss->ss1.mocs_index = intel_get_wb_mocs_index(ibb->fd);
> -	else
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(ibb->fd);
> +	ss->ss1.mocs_index = buf->mocs_index;
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> index 5e2701a7d..c34d778a1 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -29,6 +29,7 @@
>  #include "igt.h"
>  #include "igt_x86.h"
>  #include "intel_bufops.h"
> +#include "intel_mocs.h"
>  #include "intel_pat.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> @@ -877,8 +878,8 @@ static void __intel_buf_init(struct buf_ops *bops,
>  	buf->bpp = bpp;
>  	buf->compression = compression;
>  	buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
> -	buf->mocs = INTEL_BUF_MOCS_DEFAULT;
>  	buf->pat_index = pat_index;
> +	buf->mocs_index = intel_get_uc_mocs_index(bops->fd);

Without comment I would be confused. But this is transient state.

>  	IGT_INIT_LIST_HEAD(&buf->link);
>  
>  	tile_width = __get_min_stride(width, bpp, tiling);
> diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
> index 363f7abaa..60f7785fe 100644
> --- a/lib/intel_bufops.h
> +++ b/lib/intel_bufops.h
> @@ -12,12 +12,6 @@ struct buf_ops;
>  #define INTEL_BUF_NAME_MAXSIZE 32
>  #define INVALID_ADDR(x) ((x) == INTEL_BUF_INVALID_ADDRESS)
>  
> -enum intel_buf_mocs {
> -	INTEL_BUF_MOCS_DEFAULT,
> -	INTEL_BUF_MOCS_UC,
> -	INTEL_BUF_MOCS_WB,
> -};
> -
>  struct intel_buf {
>  	struct buf_ops *bops;
>  
> @@ -31,7 +25,6 @@ struct intel_buf {
>  	uint32_t compression;
>  	uint32_t swizzle_mode;
>  	uint32_t yuv_semiplanar_bpp;
> -	enum intel_buf_mocs mocs;
>  	bool format_is_yuv;
>  	bool format_is_yuv_semiplanar;
>  	struct {
> @@ -68,6 +61,9 @@ struct intel_buf {
>  	/* pat_index to use for mapping this buf. Only used in Xe. */
>  	uint8_t pat_index;
>  
> +	/* mocs_index to use for operations using this intel_buf, like render_copy  */
> +	uint8_t mocs_index;
> +
>  	/* For debugging purposes */
>  	char name[INTEL_BUF_NAME_MAXSIZE + 1];
>  };
> @@ -227,17 +223,4 @@ void intel_buf_draw_pattern(struct buf_ops *bops, struct intel_buf *buf,
>  			    int cx, int cy, int cw, int ch,
>  			    bool use_alternate_colors);
>  
> -static inline enum intel_buf_mocs intel_buf_get_mocs(const struct intel_buf *buf)
> -{
> -	igt_assert(buf);
> -	return buf->mocs;
> -}
> -
> -static inline void intel_buf_set_mocs(struct intel_buf *buf,
> -				      enum intel_buf_mocs mocs)
> -{
> -	igt_assert(buf);
> -	buf->mocs = mocs;
> -}
> -
>  #endif
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 404406e5f..caf4623af 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -153,7 +153,6 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
>  	struct gen9_surface_state *ss;
>  	uint32_t write_domain, read_domain;
>  	uint64_t address;
> -	int i915 = buf_ops_get_fd(buf->bops);
>  
>  	igt_assert_lte(buf->surface[0].stride, 256*1024);
>  	igt_assert_lte(intel_buf_width(buf), 16384);
> @@ -179,12 +178,12 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
>  	ss->ss0.vertical_alignment = 1; /* align 4 */
>  	ss->ss0.horizontal_alignment = 1; /* align 4 or HALIGN_32 on display ver >= 13*/
>  
> +	ss->ss1.mocs_index = buf->mocs_index;
> +
>  	if (HAS_4TILE(ibb->devid)) {
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(i915);
>  		ss->ss5.mip_tail_start_lod = 0;
>  	} else {
>  		ss->ss0.render_cache_read_write = 1;
> -		ss->ss1.mocs_index = intel_get_uc_mocs_index(i915);
>  		ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
>  	}
>  
> -- 
> 2.43.2
> 

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

Re: [PATCH i-g-t v2 4/6] lib/intel_buf: expose mocs_index

[Zbigniew Kempczyński]

On Tue, Mar 05, 2024 at 12:17:52PM +0000, Matthew Auld wrote:
> Allow the caller the set the intel_buf.mocs_index as part of the usual
> _full variants.
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/igt_draw.c            |  7 ++++---
>  lib/igt_fb.c              |  3 ++-
>  lib/intel_bufops.c        | 30 ++++++++++++++++++++----------
>  lib/intel_bufops.h        |  6 ++++--
>  lib/intel_mocs.h          |  2 ++
>  tests/intel/kms_big_fb.c  |  4 +++-
>  tests/intel/kms_dirtyfb.c |  7 +++++--
>  tests/intel/kms_psr.c     |  4 +++-
>  tests/intel/xe_intel_bb.c |  4 +++-
>  tests/intel/xe_pat.c      |  8 ++++----
>  10 files changed, 50 insertions(+), 25 deletions(-)
> 
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 1b702e376..2c01d7b02 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -663,7 +663,8 @@ static struct intel_buf *create_buf(int fd, struct buf_ops *bops,
>  				    tiling, 0,
>  				    size, 0,
>  				    region,
> -				    from->pat_index);
> +				    from->pat_index,
> +				    DEFAULT_MOCS_INDEX);
>  
>  	/* Make sure we close handle on destroy path */
>  	intel_buf_set_ownership(buf, true);
> @@ -723,9 +724,9 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data,
>  		pitch = tiling ? buf->stride / 4 : buf->stride;
>  
>  		if (ver >= 20)
> -			mocs = intel_get_uc_mocs_index(fd) << XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
> +			mocs = dst->mocs_index << XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
>  		else
> -			mocs = intel_get_uc_mocs_index(fd) << XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
> +			mocs = dst->mocs_index << XY_FAST_COLOR_BLT_MOCS_INDEX_SHIFT;
>  
>  		intel_bb_out(ibb, XY_FAST_COLOR_BLT | blt_cmd_depth);
>  		intel_bb_out(ibb, blt_cmd_tiling | mocs | (pitch-1));
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 0ac2a76b0..cc70cb91c 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -2642,7 +2642,8 @@ igt_fb_create_intel_buf(int fd, struct buf_ops *bops,
>  				    compression, fb->size,
>  				    fb->strides[0],
>  				    region,
> -				    intel_get_pat_idx_uc(fd));
> +				    intel_get_pat_idx_uc(fd),
> +				    DEFAULT_MOCS_INDEX);
>  	intel_buf_set_name(buf, name);
>  
>  	/* Make sure we close handle on destroy path */
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> index c34d778a1..1dc25d61f 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -857,7 +857,8 @@ static void __intel_buf_init(struct buf_ops *bops,
>  			     int width, int height, int bpp, int alignment,
>  			     uint32_t req_tiling, uint32_t compression,
>  			     uint64_t bo_size, int bo_stride,
> -			     uint64_t region, uint8_t pat_index)
> +			     uint64_t region, uint8_t pat_index,
> +			     uint8_t mocs_index)
>  {
>  	uint32_t tiling = req_tiling;
>  	uint64_t size;
> @@ -879,7 +880,9 @@ static void __intel_buf_init(struct buf_ops *bops,
>  	buf->compression = compression;
>  	buf->addr.offset = INTEL_BUF_INVALID_ADDRESS;
>  	buf->pat_index = pat_index;
> -	buf->mocs_index = intel_get_uc_mocs_index(bops->fd);
> +	if (mocs_index == DEFAULT_MOCS_INDEX)
> +		mocs_index = intel_get_uc_mocs_index(bops->fd);
> +	buf->mocs_index = mocs_index;

I think this is reasonable to pick UC when user passes default.

Patch is fine to me:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

>  	IGT_INIT_LIST_HEAD(&buf->link);
>  
>  	tile_width = __get_min_stride(width, bpp, tiling);
> @@ -973,7 +976,8 @@ void intel_buf_init(struct buf_ops *bops,
>  	region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY :
>  						     system_memory(bops->fd);
>  	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
> -			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX);
> +			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
> +			 DEFAULT_MOCS_INDEX);
>  
>  	intel_buf_set_ownership(buf, true);
>  }
> @@ -990,7 +994,8 @@ void intel_buf_init_in_region(struct buf_ops *bops,
>  			      uint64_t region)
>  {
>  	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
> -			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX);
> +			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
> +			 DEFAULT_MOCS_INDEX);
>  
>  	intel_buf_set_ownership(buf, true);
>  }
> @@ -1053,7 +1058,8 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
>  	igt_assert(handle);
>  	igt_assert(size);
>  	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
> -			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX);
> +			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX,
> +			 DEFAULT_MOCS_INDEX);
>  }
>  
>  /**
> @@ -1071,6 +1077,8 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
>   * @stride: bo stride
>   * @region: region
>   * @pat_index: pat_index to use for the binding (only used on xe)
> + * @pat_index: mocs_index to use for operations using this intel_buf, like render
> + * copy.
>   *
>   * Function configures BO handle within intel_buf structure passed by the caller
>   * (with all its metadata - width, height, ...). Useful if BO was created
> @@ -1089,11 +1097,12 @@ void intel_buf_init_full(struct buf_ops *bops,
>  			 uint64_t size,
>  			 int stride,
>  			 uint64_t region,
> -			 uint8_t pat_index)
> +			 uint8_t pat_index,
> +			 uint8_t mocs_index)
>  {
>  	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
>  			 req_tiling, compression, size, stride, region,
> -			 pat_index);
> +			 pat_index, mocs_index);
>  }
>  
>  /**
> @@ -1155,7 +1164,7 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
>  	igt_assert(size);
>  	return intel_buf_create_full(bops, handle, width, height, bpp, alignment,
>  				     req_tiling, compression, size, 0, -1,
> -				     DEFAULT_PAT_INDEX);
> +				     DEFAULT_PAT_INDEX, DEFAULT_MOCS_INDEX);
>  }
>  
>  struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
> @@ -1167,7 +1176,8 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
>  					uint64_t size,
>  					int stride,
>  					uint64_t region,
> -					uint8_t pat_index)
> +					uint8_t pat_index,
> +					uint8_t mocs_index)
>  {
>  	struct intel_buf *buf;
>  
> @@ -1178,7 +1188,7 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
>  
>  	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
>  			 req_tiling, compression, size, stride, region,
> -			 pat_index);
> +			 pat_index, mocs_index);
>  
>  	return buf;
>  }
> diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
> index 60f7785fe..af2009b3d 100644
> --- a/lib/intel_bufops.h
> +++ b/lib/intel_bufops.h
> @@ -158,7 +158,8 @@ void intel_buf_init_full(struct buf_ops *bops,
>  			 uint64_t size,
>  			 int stride,
>  			 uint64_t region,
> -			 uint8_t pat_index);
> +			 uint8_t pat_index,
> +			 uint8_t mocs_index);
>  
>  struct intel_buf *intel_buf_create(struct buf_ops *bops,
>  				   int width, int height,
> @@ -191,7 +192,8 @@ struct intel_buf *intel_buf_create_full(struct buf_ops *bops,
>  					uint64_t size,
>  					int stride,
>  					uint64_t region,
> -					uint8_t pat_index);
> +					uint8_t pat_index,
> +					uint8_t mocs_index);
>  void intel_buf_destroy(struct intel_buf *buf);
>  
>  static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
> diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
> index a9e075273..b5c79b0e1 100644
> --- a/lib/intel_mocs.h
> +++ b/lib/intel_mocs.h
> @@ -8,6 +8,8 @@
>  
>  #include <stdint.h>
>  
> +#define DEFAULT_MOCS_INDEX ((uint8_t)-1)
> +
>  uint8_t intel_get_wb_mocs_index(int fd);
>  uint8_t intel_get_uc_mocs_index(int fd);
>  
> diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c
> index 0bd79394b..f7f303d41 100644
> --- a/tests/intel/kms_big_fb.c
> +++ b/tests/intel/kms_big_fb.c
> @@ -37,6 +37,7 @@
>  #include <string.h>
>  
>  #include "i915/gem_create.h"
> +#include "intel_mocs.h"
>  #include "intel_pat.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> @@ -206,7 +207,8 @@ static struct intel_buf *init_buf(data_t *data,
>  	buf = intel_buf_create_full(data->bops, handle, width, height,
>  				    bpp, 0, tiling, 0, size, 0,
>  				    region,
> -				    intel_get_pat_idx_uc(data->drm_fd));
> +				    intel_get_pat_idx_uc(data->drm_fd),
> +				    DEFAULT_MOCS_INDEX);
>  
>  	intel_buf_set_name(buf, buf_name);
>  	intel_buf_set_ownership(buf, true);
> diff --git a/tests/intel/kms_dirtyfb.c b/tests/intel/kms_dirtyfb.c
> index 9aa066004..9e4832929 100644
> --- a/tests/intel/kms_dirtyfb.c
> +++ b/tests/intel/kms_dirtyfb.c
> @@ -20,6 +20,7 @@
>  
>  #include "i915/intel_drrs.h"
>  #include "i915/intel_fbc.h"
> +#include "intel_mocs.h"
>  #include "intel_pat.h"
>  
>  #include "xe/xe_query.h"
> @@ -256,7 +257,8 @@ static void run_test(data_t *data)
>  				    igt_fb_mod_to_tiling(data->fbs[1].modifier),
>  				    0, data->fbs[1].size, 0, is_xe_device(data->drm_fd) ?
>  				    system_memory(data->drm_fd) : 0,
> -				    intel_get_pat_idx_uc(data->drm_fd));
> +				    intel_get_pat_idx_uc(data->drm_fd),
> +				    DEFAULT_MOCS_INDEX);
>  	dst = intel_buf_create_full(data->bops, data->fbs[2].gem_handle,
>  				    data->fbs[2].width,
>  				    data->fbs[2].height,
> @@ -264,7 +266,8 @@ static void run_test(data_t *data)
>  				    0, igt_fb_mod_to_tiling(data->fbs[2].modifier),
>  				    0, data->fbs[2].size, 0, is_xe_device(data->drm_fd) ?
>  				    system_memory(data->drm_fd) : 0,
> -				    intel_get_pat_idx_uc(data->drm_fd));
> +				    intel_get_pat_idx_uc(data->drm_fd),
> +				    DEFAULT_MOCS_INDEX);
>  	ibb = intel_bb_create(data->drm_fd, PAGE_SIZE);
>  
>  	spin = igt_spin_new(data->drm_fd, .ahnd = ibb->allocator_handle);
> diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c
> index 3822b3081..c90612426 100644
> --- a/tests/intel/kms_psr.c
> +++ b/tests/intel/kms_psr.c
> @@ -35,6 +35,7 @@
>  #include "igt.h"
>  #include "igt_sysfs.h"
>  #include "igt_psr.h"
> +#include "intel_mocs.h"
>  #include "intel_pat.h"
>  #include <errno.h>
>  #include <stdbool.h>
> @@ -421,7 +422,8 @@ static struct intel_buf *create_buf_from_fb(data_t *data,
>  	handle = gem_open(data->drm_fd, name);
>  	buf = intel_buf_create_full(data->bops, handle, width, height,
>  				    bpp, 0, tiling, 0, size, stride, region,
> -				    intel_get_pat_idx_uc(data->drm_fd));
> +				    intel_get_pat_idx_uc(data->drm_fd),
> +				    DEFAULT_MOCS_INDEX);
>  	intel_buf_set_ownership(buf, true);
>  
>  	return buf;
> diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
> index c3a4b5450..09164c41f 100644
> --- a/tests/intel/xe_intel_bb.c
> +++ b/tests/intel/xe_intel_bb.c
> @@ -19,6 +19,7 @@
>  #include "igt.h"
>  #include "igt_crc.h"
>  #include "intel_bufops.h"
> +#include "intel_mocs.h"
>  #include "intel_pat.h"
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> @@ -393,7 +394,8 @@ static void create_in_region(struct buf_ops *bops, uint64_t region)
>  	intel_buf_init_full(bops, handle, &buf,
>  			    width/4, height, 32, 0,
>  			    I915_TILING_NONE, 0,
> -			    size, 0, region, DEFAULT_PAT_INDEX);
> +			    size, 0, region, DEFAULT_PAT_INDEX,
> +			    DEFAULT_MOCS_INDEX);
>  	intel_buf_set_ownership(&buf, true);
>  
>  	intel_bb_add_intel_buf(ibb, &buf, false);
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index 3d7d7400c..6918ebe7e 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -388,11 +388,11 @@ static void pat_index_render(struct xe_pat_param *p)
>  
>  	intel_buf_init_full(bops, p->r1_bo, &src, width, height, bpp, 0,
>  			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
> -			    stride, p->r1, p->r1_pat_index);
> +			    stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
>  
>  	intel_buf_init_full(bops, p->r2_bo, &dst, width, height, bpp, 0,
>  			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
> -			    stride, p->r2, p->r2_pat_index);
> +			    stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
>  
>  	/* Ensure we always see zeroes for the initial KMD zeroing */
>  	render_copy(ibb,
> @@ -483,12 +483,12 @@ static void pat_index_dw(struct xe_pat_param *p)
>  
>  	intel_buf_init_full(bops, p->r1_bo, &r1_buf, width, height, bpp, 0,
>  			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
> -			    stride, p->r1, p->r1_pat_index);
> +			    stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
>  	intel_bb_add_intel_buf(ibb, &r1_buf, true);
>  
>  	intel_buf_init_full(bops, p->r2_bo, &r2_buf, width, height, bpp, 0,
>  			    I915_TILING_NONE, I915_COMPRESSION_NONE, size,
> -			    stride, p->r2, p->r2_pat_index);
> +			    stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
>  	intel_bb_add_intel_buf(ibb, &r2_buf, true);
>  
>  	/*
> -- 
> 2.43.2
> 

Re: [PATCH i-g-t v2 5/6] lib/intel_mocs: add defer-to-pat-index

[Zbigniew Kempczyński]

On Tue, Mar 05, 2024 at 12:17:53PM +0000, Matthew Auld wrote:
> At least on Xe2 it looks like we can just use MOCS index zero to defer
> the selected caching mode to that of the PAT index. This will be useful
> in an upcoming patch.
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/intel_mocs.c | 14 ++++++++++++++
>  lib/intel_mocs.h |  1 +
>  2 files changed, 15 insertions(+)
> 
> diff --git a/lib/intel_mocs.c b/lib/intel_mocs.c
> index 4a9c305dc..bf6ee1958 100644
> --- a/lib/intel_mocs.c
> +++ b/lib/intel_mocs.c
> @@ -9,6 +9,7 @@
>  struct drm_intel_mocs_index {
>  	uint8_t uc_index;
>  	uint8_t wb_index;
> +	uint8_t deferred_index;

I wonder shouldn't it be called 'prefer_pat' or similar.

Anyway, code is correct what I've seen in xe_mocs.c xe2 defs.
Regarless decision to rename the above:

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew

>  };
>  
>  static void get_mocs_index(int fd, struct drm_intel_mocs_index *mocs)
> @@ -25,6 +26,7 @@ static void get_mocs_index(int fd, struct drm_intel_mocs_index *mocs)
>  	if (intel_graphics_ver(devid) >= IP_VER(20, 0)) {
>  		mocs->uc_index = 3;
>  		mocs->wb_index = 4;
> +		mocs->deferred_index = 0;
>  	} else if (IS_METEORLAKE(devid)) {
>  		mocs->uc_index = 5;
>  		mocs->wb_index = 10;
> @@ -60,3 +62,15 @@ uint8_t intel_get_uc_mocs_index(int fd)
>  
>  	return mocs.uc_index;
>  }
> +
> +uint8_t intel_get_deferred_mocs_index(int fd)
> +{
> +	struct drm_intel_mocs_index mocs;
> +	uint16_t dev_id = intel_get_drm_devid(fd);
> +
> +	igt_assert(AT_LEAST_GEN(dev_id, 20));
> +
> +	get_mocs_index(fd, &mocs);
> +
> +	return mocs.deferred_index;
> +}
> diff --git a/lib/intel_mocs.h b/lib/intel_mocs.h
> index b5c79b0e1..bfdc23210 100644
> --- a/lib/intel_mocs.h
> +++ b/lib/intel_mocs.h
> @@ -12,5 +12,6 @@
>  
>  uint8_t intel_get_wb_mocs_index(int fd);
>  uint8_t intel_get_uc_mocs_index(int fd);
> +uint8_t intel_get_deferred_mocs_index(int fd);
>  
>  #endif /* _INTEL_MOCS_H */
> -- 
> 2.43.2
>