[PATCH i-g-t 0/4] Tes update for atomics related uAPI changes

[PATCH i-g-t 0/4] Tes update for atomics related uAPI changes

[Nirmoy Das]

Update tests as per newly added uAPIs.
https://patchwork.freedesktop.org/series/132290/

Nirmoy Das (4):
  drm-uapi/xe: Add device atomics vm bind flags
  drm-uapi/xe: Add query flag for dev atomics on SMEM
  tests/intel/xe_exec_atomic: Use new vm bind flag
  test/intel/xe_query: Print DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM

 include/drm-uapi/xe_drm.h    | 20 ++++++++++++++++----
 tests/intel/xe_exec_atomic.c | 10 ++++++----
 tests/intel/xe_query.c       |  2 ++
 3 files changed, 24 insertions(+), 8 deletions(-)

-- 
2.42.0

[PATCH i-g-t 1/4] drm-uapi/xe: Add device atomics vm bind flags

[Nirmoy Das]

Align with commit ("drm/xe/uapi: Introduce VMA bind flag for device
atomics")

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 include/drm-uapi/xe_drm.h | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 4353595a4..9171cc0f1 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -881,6 +881,14 @@ struct drm_xe_vm_destroy {
  *    will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
  *    handle MBZ, and the BO offset MBZ. This flag is intended to
  *    implement VK sparse bindings.
+ *  - %DRM_XE_VM_BIND_FLAG_DEVICE_ATOMICS - When this flag is set for
+ *    a VA range, all the corresponding PTEs will have atomic access bit
+ *    set. This will allow device atomics operation for that VA range.
+ *    This flag only works for single placement buffer objects and
+ *    mainly for SMEM only buffer objects where CPU atomics can be perform
+ *    by an application and so KMD can not set device atomics on such buffers
+ *    by default. This flag has no effect on LMEM only placed buffers as atomic
+ *    access bit is set for LMEM backed PTEs always.
  */
 struct drm_xe_vm_bind_op {
 	/** @extensions: Pointer to the first extension struct, if any */
@@ -967,10 +975,11 @@ struct drm_xe_vm_bind_op {
 	/** @op: Bind operation to perform */
 	__u32 op;
 
-#define DRM_XE_VM_BIND_FLAG_READONLY	(1 << 0)
-#define DRM_XE_VM_BIND_FLAG_IMMEDIATE	(1 << 1)
-#define DRM_XE_VM_BIND_FLAG_NULL	(1 << 2)
-#define DRM_XE_VM_BIND_FLAG_DUMPABLE	(1 << 3)
+#define DRM_XE_VM_BIND_FLAG_READONLY		(1 << 0)
+#define DRM_XE_VM_BIND_FLAG_IMMEDIATE		(1 << 1)
+#define DRM_XE_VM_BIND_FLAG_NULL		(1 << 2)
+#define DRM_XE_VM_BIND_FLAG_DUMPABLE		(1 << 3)
+#define DRM_XE_VM_BIND_FLAG_DEVICE_ATOMICS	(1 << 4)
 	/** @flags: Bind flags */
 	__u32 flags;
 
-- 
2.42.0

[PATCH i-g-t 1/4] lib/igt_gt: Add gem_engine_can_block_ggtt_binder

[Nirmoy Das]

On MTL GGTT updates happens through MI_UPDATE_GGTT command.
Add a method to detect if a engine can block ggtt binder.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/igt_gt.c | 15 +++++++++++++++
 lib/igt_gt.h |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index a24a566c7..aa5e75b07 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -659,3 +659,18 @@ int gem_execbuf_flags_to_engine_class(unsigned int flags)
 		igt_assert(0);
 	}
 }
+
+/**
+ * gem_engine_can_block_ggtt_binder:
+ * @fd: open i915 drm file descriptor
+ * @engine: engine to be assessed
+ *
+ * Detect if the platform needs blitter based GGTT
+ * updates.
+ */
+bool gem_engine_can_block_ggtt_binder(int fd,
+		const struct intel_execution_engine2 *engine)
+{
+	return IS_METEORLAKE(intel_get_drm_devid(fd)) &&
+		engine->class == I915_ENGINE_CLASS_COPY;
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 3d10349e4..d0c5510b1 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -83,5 +83,7 @@ extern const struct intel_execution_engine2 {
 } intel_execution_engines2[];
 
 int gem_execbuf_flags_to_engine_class(unsigned int flags);
+bool gem_engine_can_block_ggtt_binder(int fd,
+		const struct intel_execution_engine2 *engine);
 
 #endif /* IGT_GT_H */
-- 
2.41.0

[PATCH i-g-t 2/4] drm-uapi/xe: Add query flag for dev atomics on SMEM

[Nirmoy Das]

Align with commit ("drm/xe/uapi: Add a query flag for
 has_device_atomics_on_smem")

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 include/drm-uapi/xe_drm.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 9171cc0f1..992bd75e1 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -394,6 +394,8 @@ struct drm_xe_query_mem_regions {
  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
  *  - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
  *    available exec queue priority
+ *  - %DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM - Flag is set if the device
+ *    supports device atomics on system memory
  */
 struct drm_xe_query_config {
 	/** @num_params: number of parameters returned in info */
@@ -408,6 +410,7 @@ struct drm_xe_query_config {
 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
 #define DRM_XE_QUERY_CONFIG_VA_BITS			3
 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
+#define DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM	5
 	/** @info: array of elements containing the config info */
 	__u64 info[];
 };
-- 
2.42.0

[PATCH i-g-t 2/4] tests/intel/gem_ctx_shared: Skip some test on MTL

[Nirmoy Das]

We do GGTT update on MTL using bcs engine, blocking that would
fail the test so skip such subtests on bcs engine for MTL.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 tests/intel/gem_ctx_shared.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tests/intel/gem_ctx_shared.c b/tests/intel/gem_ctx_shared.c
index d24ae5483..fd429306e 100644
--- a/tests/intel/gem_ctx_shared.c
+++ b/tests/intel/gem_ctx_shared.c
@@ -1047,6 +1047,12 @@ static void smoketest(int i915, const intel_ctx_cfg_t *cfg,
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", e->name)
 
+#define for_each_nonblocking_ggtt_binder_queue(e, i915, cfg) \
+	for_each_ctx_cfg_engine(i915, cfg, e) \
+		for_each_if(gem_class_can_store_dword(i915, (e)->class) && \
+			    !gem_engine_can_block_ggtt_binder(i915, e)) \
+			igt_dynamic_f("%s", e->name)
+
 igt_main
 {
 	const struct intel_execution_engine2 *e;
@@ -1104,22 +1110,22 @@ igt_main
 			}
 
 			igt_subtest_with_dynamic("Q-independent") {
-				for_each_queue(e, i915, &cfg)
+				for_each_nonblocking_ggtt_binder_queue(e, i915, &cfg)
 					independent(i915, &cfg, e, 0);
 			}
 
 			igt_subtest_with_dynamic("Q-in-order") {
-				for_each_queue(e, i915, &cfg)
+				for_each_nonblocking_ggtt_binder_queue(e, i915, &cfg)
 					reorder(i915, &cfg, e->flags, EQUAL);
 			}
 
 			igt_subtest_with_dynamic("Q-out-order") {
-				for_each_queue(e, i915, &cfg)
+				for_each_nonblocking_ggtt_binder_queue(e, i915, &cfg)
 					reorder(i915, &cfg, e->flags, 0);
 			}
 
 			igt_subtest_with_dynamic("Q-promotion") {
-				for_each_queue(e, i915, &cfg)
+				for_each_nonblocking_ggtt_binder_queue(e, i915, &cfg)
 					promotion(i915, &cfg, e->flags);
 			}
 		}
-- 
2.41.0

[PATCH i-g-t 3/4] tests/intel/gem_ctx_schedule: Skip some test on MTL

[Nirmoy Das]

We do GGTT update on MTL using bcs engine, blocking that would
fail the test so skip such subtests on bcs engine for MTL.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 tests/intel/gem_exec_schedule.c | 39 +++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/tests/intel/gem_exec_schedule.c b/tests/intel/gem_exec_schedule.c
index c94988d36..183ee1a21 100644
--- a/tests/intel/gem_exec_schedule.c
+++ b/tests/intel/gem_exec_schedule.c
@@ -3479,6 +3479,12 @@ static void fairslice(int i915, const intel_ctx_cfg_t *cfg,
 		for_each_if(gem_class_can_store_dword(fd, e->class)) \
 		igt_dynamic_f("%s", e->name)
 
+#define test_each_ggtt_binder_nonblocking_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
+		for_each_if(gem_class_can_store_dword(fd, e->class) && \
+			    !gem_engine_can_block_ggtt_binder(i915, e)) \
+		igt_dynamic_f("%s", e->name)
+
 igt_main
 {
 	int fd = -1;
@@ -3502,21 +3508,22 @@ igt_main
 	igt_subtest_group {
 		const struct intel_execution_engine2 *e;
 
-		test_each_engine_store("fifo", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("fifo", fd, ctx, e)
 			fifo(fd, ctx, e->flags);
 
-		test_each_engine_store("implicit-read-write", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("implicit-read-write", fd, ctx, e)
 			implicit_rw(fd, ctx, e->flags, READ_WRITE);
 
-		test_each_engine_store("implicit-write-read", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("implicit-write-read", fd, ctx, e)
 			implicit_rw(fd, ctx, e->flags, WRITE_READ);
 
-		test_each_engine_store("implicit-boths", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("implicit-boths", fd, ctx, e)
 			implicit_rw(fd, ctx, e->flags, READ_WRITE | WRITE_READ);
 
-		test_each_engine_store("independent", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("independent", fd, ctx, e)
 			independent(fd, ctx, e->flags, 0);
-		test_each_engine_store("u-independent", fd, ctx, e)
+
+		test_each_ggtt_binder_nonblocking_engine("u-independent", fd, ctx, e)
 			independent(fd, ctx, e->flags, IGT_SPIN_USERPTR);
 	}
 
@@ -3612,13 +3619,13 @@ igt_main
 		igt_subtest("smoketest-all")
 			smoketest(fd, &ctx->cfg, ALL_ENGINES, 30);
 
-		test_each_engine_store("in-order", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("in-order", fd, ctx, e)
 			reorder(fd, &ctx->cfg, e->flags, EQUAL);
 
-		test_each_engine_store("out-order", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("out-order", fd, ctx, e)
 			reorder(fd, &ctx->cfg, e->flags, 0);
 
-		test_each_engine_store("promotion", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("promotion", fd, ctx, e)
 			promotion(fd, &ctx->cfg, e->flags);
 
 		igt_subtest_group {
@@ -3685,23 +3692,23 @@ igt_main
 			}
 		}
 
-		test_each_engine_store("noreorder", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("noreorder", fd, ctx, e)
 			noreorder(fd, &ctx->cfg, e->flags, 0, 0);
 
-		test_each_engine_store("noreorder-priority", fd, ctx, e) {
+		test_each_ggtt_binder_nonblocking_engine("noreorder-priority", fd, ctx, e) {
 			igt_require(gem_scheduler_enabled(fd));
 			noreorder(fd, &ctx->cfg, e->flags, MAX_PRIO, 0);
 		}
 
-		test_each_engine_store("noreorder-corked", fd, ctx, e) {
+		test_each_ggtt_binder_nonblocking_engine("noreorder-corked", fd, ctx, e) {
 			igt_require(gem_scheduler_enabled(fd));
 			noreorder(fd, &ctx->cfg, e->flags, MAX_PRIO, CORKED);
 		}
 
-		test_each_engine_store("deep", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("deep", fd, ctx, e)
 			deep(fd, &ctx->cfg, e->flags);
 
-		test_each_engine_store("wide", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("wide", fd, ctx, e)
 			wide(fd, &ctx->cfg, e->flags);
 
 		test_each_engine_store("smoketest", fd, ctx, e)
@@ -3735,10 +3742,10 @@ igt_main
 		test_each_engine("pi-userfault", fd, ctx, e)
 			test_pi_userfault(fd, &ctx->cfg, e->flags);
 
-		test_each_engine("pi-distinct-iova", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("pi-distinct-iova", fd, ctx, e)
 			test_pi_iova(fd, &ctx->cfg, e->flags, 0);
 
-		test_each_engine("pi-shared-iova", fd, ctx, e)
+		test_each_ggtt_binder_nonblocking_engine("pi-shared-iova", fd, ctx, e)
 			test_pi_iova(fd, &ctx->cfg, e->flags, SHARED);
 	}
 
-- 
2.41.0

[PATCH i-g-t 3/4] tests/intel/xe_exec_atomic: Use new vm bind flag

[Nirmoy Das]

Use new vm bind flag to probe device atomics support.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 tests/intel/xe_exec_atomic.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/tests/intel/xe_exec_atomic.c b/tests/intel/xe_exec_atomic.c
index d9790da78..1ec149ca1 100644
--- a/tests/intel/xe_exec_atomic.c
+++ b/tests/intel/xe_exec_atomic.c
@@ -85,7 +85,8 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc
 
 	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
 	bind_engine = xe_bind_exec_queue_create(fd, vm, 0);
-	xe_vm_bind_async(fd, vm, bind_engine, bo, 0, addr, bo_size, &sync, 1);
+	xe_vm_bind_async_flags(fd, vm, bind_engine, bo, 0, addr, bo_size,
+			       &sync, 1, DRM_XE_VM_BIND_FLAG_DEVICE_ATOMICS);
 	data = xe_bo_mmap_ext(fd, bo, bo_size, PROT_READ|PROT_WRITE);
 	data->data = value;
 
@@ -112,9 +113,10 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc
 
 static bool has_atomics(int fd, uint32_t region)
 {
-	/* System memory atomics on dGPU is not functional as of now */
-	if (region == system_memory(fd) && xe_has_vram(fd))
-		return false;
+	struct drm_xe_query_config *config = xe_config(fd);
+
+	if (region == system_memory(fd))
+		return !!config->info[DRM_XE_QUERY_CONFIG_VA_BITS];
 
 	return true;
 }
-- 
2.42.0

[PATCH i-g-t 4/4] test/intel/xe_query: Print DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM

[Nirmoy Das]

Print DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM query flag

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 tests/intel/xe_query.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c
index a5a2dd7d4..f2aa577c5 100644
--- a/tests/intel/xe_query.c
+++ b/tests/intel/xe_query.c
@@ -434,6 +434,8 @@ test_query_config(int fd)
 		config->info[DRM_XE_QUERY_CONFIG_VA_BITS]);
 	igt_info("DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY\t%llu\n",
 		config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY]);
+	igt_info("DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM\t%llu\n",
+		 config->info[DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM]);
 	dump_hex_debug(config, query.size);
 
 	free(config);
-- 
2.42.0

[PATCH i-g-t 4/4] tests/intel/gem_spin_batch: Skip some test on MTL

[Nirmoy Das]

We do GGTT update on MTL using bcs engine, blocking that would
fail the test so skip such subtests on bcs engine for MTL.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 tests/intel/gem_spin_batch.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/intel/gem_spin_batch.c b/tests/intel/gem_spin_batch.c
index 18873be16..ec1458e35 100644
--- a/tests/intel/gem_spin_batch.c
+++ b/tests/intel/gem_spin_batch.c
@@ -227,6 +227,9 @@ static void spin_all(int i915, const intel_ctx_t *ctx, unsigned int flags)
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
+		if (gem_engine_can_block_ggtt_binder(i915, e))
+			continue;
+
 		if (flags & PARALLEL_SPIN_NEW_CTX)
 			ctx = intel_ctx_create(i915, &cfg);
 		ahnd = get_reloc_ahnd(i915, ctx->id);
-- 
2.41.0

Re: [PATCH i-g-t 0/4] Tes update for atomics related uAPI changes

[Nirmoy Das]

Please ignore this series. I forgot to cleanup my out dir which had 
stale patches

On 4/12/2024 10:57 AM, Nirmoy Das wrote:
> Update tests as per newly added uAPIs.
> https://patchwork.freedesktop.org/series/132290/
>
> Nirmoy Das (4):
>    drm-uapi/xe: Add device atomics vm bind flags
>    drm-uapi/xe: Add query flag for dev atomics on SMEM
>    tests/intel/xe_exec_atomic: Use new vm bind flag
>    test/intel/xe_query: Print DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM
>
>   include/drm-uapi/xe_drm.h    | 20 ++++++++++++++++----
>   tests/intel/xe_exec_atomic.c | 10 ++++++----
>   tests/intel/xe_query.c       |  2 ++
>   3 files changed, 24 insertions(+), 8 deletions(-)
>

[PATCH i-g-t 0/4] Tes update for atomics related uAPI changes

[Nirmoy Das]

Update tests as per newly added uAPIs.
https://patchwork.freedesktop.org/series/132290/

Nirmoy Das (4):
  drm-uapi/xe: Add device atomics vm bind flags
  drm-uapi/xe: Add query flag for dev atomics on SMEM
  tests/intel/xe_exec_atomic: Use new vm bind flag
  test/intel/xe_query: Print DRM_XE_QUERY_CONFIG_SUPP_DEV_ATOMIC_ON_SMEM

 include/drm-uapi/xe_drm.h    | 20 ++++++++++++++++----
 tests/intel/xe_exec_atomic.c | 10 ++++++----
 tests/intel/xe_query.c       |  2 ++
 3 files changed, 24 insertions(+), 8 deletions(-)

-- 
2.42.0

[PATCH i-g-t 3/4] tests/intel/xe_exec_atomic: Use new vm bind flag

[Nirmoy Das]

Use new vm bind flag to probe device atomics support.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
 tests/intel/xe_exec_atomic.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/tests/intel/xe_exec_atomic.c b/tests/intel/xe_exec_atomic.c
index d9790da78..1ec149ca1 100644
--- a/tests/intel/xe_exec_atomic.c
+++ b/tests/intel/xe_exec_atomic.c
@@ -85,7 +85,8 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc
 
 	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
 	bind_engine = xe_bind_exec_queue_create(fd, vm, 0);
-	xe_vm_bind_async(fd, vm, bind_engine, bo, 0, addr, bo_size, &sync, 1);
+	xe_vm_bind_async_flags(fd, vm, bind_engine, bo, 0, addr, bo_size,
+			       &sync, 1, DRM_XE_VM_BIND_FLAG_DEVICE_ATOMICS);
 	data = xe_bo_mmap_ext(fd, bo, bo_size, PROT_READ|PROT_WRITE);
 	data->data = value;
 
@@ -112,9 +113,10 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc
 
 static bool has_atomics(int fd, uint32_t region)
 {
-	/* System memory atomics on dGPU is not functional as of now */
-	if (region == system_memory(fd) && xe_has_vram(fd))
-		return false;
+	struct drm_xe_query_config *config = xe_config(fd);
+
+	if (region == system_memory(fd))
+		return !!config->info[DRM_XE_QUERY_CONFIG_VA_BITS];
 
 	return true;
 }
-- 
2.42.0