[PATCH i-g-t v2 04/10] lib/intel_bufops: Drop tilings restrictions

["Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>]

Different platforms supports different tilings so instead of asserting
on buffer creation path move responsibility of passing valid data
to the test. It can use intel_cmds_info to iterate over supported
tilings so this is better extendible and requires fewer changes.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_bufops.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 43d6dd5b43..3bf89798ba 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -898,9 +898,6 @@ static void __intel_buf_init(struct buf_ops *bops,
 
 	if (compression) {
 		igt_require(bops->intel_gen >= 9);
-		igt_assert(req_tiling == I915_TILING_Y ||
-			   req_tiling == I915_TILING_Yf ||
-			   req_tiling == I915_TILING_4);
 		/*
 		 * On GEN12+ we align the main surface to 4 * 4 main surface
 		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
-- 
2.34.1