[PATCH i-g-t v5 00/11] Add render-copy compression on Xe+

[PATCH i-g-t v5 00/11] Add render-copy compression on Xe+

[Zbigniew Kempczyński]

Fills the gap of testing render-copy compression with different
tilings.

v2: Extend cmds-info to collect supported tilings/compression for
    render copy

v3: Predefine simple tilings first, then complex (Karolina)
    Drop static test array in xe_intel_bb to be another
    helper function user (Karolina)

v4: Separate compression format between xe/xe2

v5: Add missing pat index in intel-buf when compression is enabled
    (Matt)

Zbigniew Kempczyński (11):
  lib/intel_bufops: Store devid on buffer ops creation
  lib/intel_blt: Rename confusing fb tile to i915 tile
  lib/intel_blt: Add i915 -> blt tile helper converter
  lib/intel_bufops: Restrict tilings on non-flatccs platforms
  lib/intel_bufops: Start supporting compression on Xe2+
  lib/rendercopy_gen9: Separate xe and xe2 compression format
  lib/intel_cmds_info: Define tiling macros
  lib/intel_cmds_info: Introduce render tilings
  lib/intel_blt: Add render tilings and compression support helper
  tests/xe_render_copy: Add subtest which exercises compression
  tests/xe_intel_bb: Use supported tilings instead hardcoded ones

 lib/gen9_render.h            |  31 +++++---
 lib/intel_blt.c              |  54 +++++++++++++-
 lib/intel_blt.h              |   4 +-
 lib/intel_bufops.c           |  70 ++++++++++++-----
 lib/intel_bufops.h           |   1 +
 lib/intel_cmds_info.c        | 141 ++++++++++++++++++-----------------
 lib/intel_cmds_info.h        |   6 ++
 lib/rendercopy_gen9.c        |  24 ++++--
 tests/intel/xe_intel_bb.c    |  25 +++----
 tests/intel/xe_render_copy.c |  93 +++++++++++++++++++++--
 10 files changed, 321 insertions(+), 128 deletions(-)

-- 
2.34.1

[PATCH i-g-t v5 01/11] lib/intel_bufops: Store devid on buffer ops creation

[Zbigniew Kempczyński]

As I need devid to diverge intel-buf init code lets store it in
bufops structure. This field is commonly used so add function which
returns it.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 lib/intel_bufops.c | 20 +++++++++++++++++---
 lib/intel_bufops.h |  1 +
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 51fdf50adb..43d6dd5b43 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -114,6 +114,7 @@ struct buf_ops {
 	int gen_start;
 	int gen_end;
 	unsigned int intel_gen;
+	uint32_t devid;
 	uint32_t supported_tiles;
 	uint32_t supported_hw_tiles;
 	uint32_t swizzle_x;
@@ -1499,12 +1500,11 @@ static bool probe_hw_tiling(struct buf_ops *bops, uint32_t tiling,
 {
 	uint64_t size = 256 * 256;
 	uint32_t handle, buf_tiling, buf_swizzle, phys_swizzle;
-	uint32_t devid, stride;
+	uint32_t stride;
 	int ret;
 	bool is_set = false;
 
-	devid =  intel_get_drm_devid(bops->fd);
-	stride = get_stride(devid, tiling);
+	stride = get_stride(bops->devid, tiling);
 	handle = gem_create(bops->fd, size);
 
 	/* Single shot, if no fences are available we fail immediately */
@@ -1616,6 +1616,7 @@ static struct buf_ops *__buf_ops_create(int fd, bool check_idempotency)
 
 	bops->fd = fd;
 	bops->intel_gen = generation;
+	bops->devid = devid;
 	bops->driver = is_i915_device(fd) ? INTEL_DRIVER_I915 :
 					    is_xe_device(fd) ? INTEL_DRIVER_XE : 0;
 	igt_assert(bops->driver);
@@ -1785,6 +1786,19 @@ int buf_ops_get_fd(struct buf_ops *bops)
 	return bops->fd;
 }
 
+/**
+ * buf_ops_get_devid
+ * @bops: pointer to buf_ops
+ *
+ * Returns: device id
+ */
+uint32_t buf_ops_get_devid(struct buf_ops *bops)
+{
+	igt_assert(bops);
+
+	return bops->devid;
+}
+
 /**
  * buf_ops_get_driver
  * @bops: pointer to buf_ops
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index b959a8cc8e..84e71d41a2 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -118,6 +118,7 @@ struct buf_ops *buf_ops_create(int fd);
 struct buf_ops *buf_ops_create_with_selftest(int fd);
 void buf_ops_destroy(struct buf_ops *bops);
 int buf_ops_get_fd(struct buf_ops *bops);
+uint32_t buf_ops_get_devid(struct buf_ops *bops);
 enum intel_driver buf_ops_get_driver(struct buf_ops *bops);
 
 bool buf_ops_set_software_tiling(struct buf_ops *bops,
-- 
2.34.1

[PATCH i-g-t v5 02/11] lib/intel_blt: Rename confusing fb tile to i915 tile

[Zbigniew Kempczyński]

Fb tile is defacto drm modifier, thus blt_tile_to_fb_tile() name
is confusing as it converts to I915_TILING*, not drm modifier.
Lets rename it.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 lib/intel_blt.c              | 4 ++--
 lib/intel_blt.h              | 2 +-
 tests/intel/xe_render_copy.c | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 4da5cc855e..5a281036c4 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -536,14 +536,14 @@ static int __block_tiling(enum blt_tiling_type tiling)
 }
 
 /**
- * blt_tile_to_fb_tile:
+ * blt_tile_to_i915_tile:
  * @tiling: tiling id
  *
  * Returns:
  * id of tiling introduced in i915 like I915_TILING_* used for example
  * in render-copy code.
  */
-int blt_tile_to_fb_tile(enum blt_tiling_type tiling)
+int blt_tile_to_i915_tile(enum blt_tiling_type tiling)
 {
 	switch (tiling) {
 	case T_LINEAR: return I915_TILING_NONE;
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index cc59666862..fcfce69bee 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -213,7 +213,7 @@ bool blt_platform_has_flat_ccs_enabled(int fd);
 bool blt_uses_extended_block_copy(int fd);
 
 const char *blt_tiling_name(enum blt_tiling_type tiling);
-int blt_tile_to_fb_tile(enum blt_tiling_type tiling);
+int blt_tile_to_i915_tile(enum blt_tiling_type tiling);
 
 uint32_t blt_get_min_stride(uint32_t width, uint32_t bpp,
 			    enum blt_tiling_type tiling);
diff --git a/tests/intel/xe_render_copy.c b/tests/intel/xe_render_copy.c
index 4f98cb7dfa..ef75c4ce6d 100644
--- a/tests/intel/xe_render_copy.c
+++ b/tests/intel/xe_render_copy.c
@@ -407,7 +407,7 @@ igt_main_args("dpiW:H:", NULL, help_str, opt_handler, NULL)
 					continue;
 
 				tiling_name = blt_tiling_name(tiling);
-				tiling = blt_tile_to_fb_tile(tiling);
+				tiling = blt_tile_to_i915_tile(tiling);
 				igt_dynamic_f("render-%s-%ux%u", tiling_name, surfwidth, surfheight)
 					render(bops, tiling, surfwidth, surfheight, id);
 			}
-- 
2.34.1

[PATCH i-g-t v5 03/11] lib/intel_blt: Add i915 -> blt tile helper converter

[Zbigniew Kempczyński]

We have two kind of buffers in IGT - intel-buf for render and
blt-object for blitter. intel-buf uses I915_TILING* whereas
blt-object blt_tiling_type (T_*). To construct blt-object from
intel-buf we need to convert I915_TILING* to T_*. Add function
which does this conversion.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 lib/intel_blt.c | 21 +++++++++++++++++++++
 lib/intel_blt.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 5a281036c4..946adc538b 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -560,6 +560,27 @@ int blt_tile_to_i915_tile(enum blt_tiling_type tiling)
 	return 0;
 }
 
+/**
+ * i915_tile_to_blt_tile:
+ * @tiling: tiling id
+ *
+ * Returns:
+ * id of blt tiling like T_LINEAR, T_XMAJOR, etc
+ */
+enum blt_tiling_type i915_tile_to_blt_tile(uint32_t tiling)
+{
+	switch (tiling) {
+	case I915_TILING_NONE:	return T_LINEAR;
+	case I915_TILING_X:	return T_XMAJOR;
+	case I915_TILING_Y:	return T_YMAJOR;
+	case I915_TILING_4:	return T_TILE4;
+	case I915_TILING_64:	return T_TILE64;
+	case I915_TILING_Yf:	return T_YFMAJOR;
+	default:
+		igt_assert_f(0, "Unknown tiling!\n");
+	}
+}
+
 /**
  * blt_get_min_stride
  * @width: width in pixels
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index fcfce69bee..6daf46aea4 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -214,6 +214,7 @@ bool blt_uses_extended_block_copy(int fd);
 
 const char *blt_tiling_name(enum blt_tiling_type tiling);
 int blt_tile_to_i915_tile(enum blt_tiling_type tiling);
+enum blt_tiling_type i915_tile_to_blt_tile(uint32_t tiling);
 
 uint32_t blt_get_min_stride(uint32_t width, uint32_t bpp,
 			    enum blt_tiling_type tiling);
-- 
2.34.1

Re: [PATCH i-g-t v5 03/11] lib/intel_blt: Add i915 -> blt tile helper converter

[Zbigniew Kempczyński]

On Thu, May 09, 2024 at 07:33:51AM +0200, Zbigniew Kempczyński wrote:
> We have two kind of buffers in IGT - intel-buf for render and
> blt-object for blitter. intel-buf uses I915_TILING* whereas
> blt-object blt_tiling_type (T_*). To construct blt-object from
> intel-buf we need to convert I915_TILING* to T_*. Add function
> which does this conversion.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
>  lib/intel_blt.c | 21 +++++++++++++++++++++
>  lib/intel_blt.h |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 5a281036c4..946adc538b 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -560,6 +560,27 @@ int blt_tile_to_i915_tile(enum blt_tiling_type tiling)
>  	return 0;
>  }
>  
> +/**
> + * i915_tile_to_blt_tile:
> + * @tiling: tiling id
> + *
> + * Returns:
> + * id of blt tiling like T_LINEAR, T_XMAJOR, etc
> + */
> +enum blt_tiling_type i915_tile_to_blt_tile(uint32_t tiling)
> +{
> +	switch (tiling) {
> +	case I915_TILING_NONE:	return T_LINEAR;
> +	case I915_TILING_X:	return T_XMAJOR;
> +	case I915_TILING_Y:	return T_YMAJOR;
> +	case I915_TILING_4:	return T_TILE4;
> +	case I915_TILING_64:	return T_TILE64;
> +	case I915_TILING_Yf:	return T_YFMAJOR;
> +	default:
> +		igt_assert_f(0, "Unknown tiling!\n");
> +	}
> +}
> +
>  /**
>   * blt_get_min_stride
>   * @width: width in pixels
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index fcfce69bee..6daf46aea4 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -214,6 +214,7 @@ bool blt_uses_extended_block_copy(int fd);
>  
>  const char *blt_tiling_name(enum blt_tiling_type tiling);
>  int blt_tile_to_i915_tile(enum blt_tiling_type tiling);
> +enum blt_tiling_type i915_tile_to_blt_tile(uint32_t tiling);
>  
>  uint32_t blt_get_min_stride(uint32_t width, uint32_t bpp,
>  			    enum blt_tiling_type tiling);
> -- 
> 2.34.1
> 

I need those two patches to my current work and as they are r-b'd
and safe I'm going to merge them individually.

--
Zbigniew

[PATCH i-g-t v5 04/11] lib/intel_bufops: Restrict tilings on non-flatccs platforms

[Zbigniew Kempczyński]

JP noticed after last changes introduced in bufops we keep unnecessary
two conditions instead of pack them to single one. This is refactor,
no functional change.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Suggested-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 lib/intel_bufops.c | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 43d6dd5b43..7118272e5f 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -896,7 +896,9 @@ static void __intel_buf_init(struct buf_ops *bops,
 
 	size = buf->surface[0].size = buf->surface[0].stride * aligned_height;
 
-	if (compression) {
+	if (compression && !HAS_FLATCCS(buf_ops_get_devid(bops))) {
+		int aux_width, aux_height;
+
 		igt_require(bops->intel_gen >= 9);
 		igt_assert(req_tiling == I915_TILING_Y ||
 			   req_tiling == I915_TILING_Yf ||
@@ -907,17 +909,12 @@ static void __intel_buf_init(struct buf_ops *bops,
 		 * CCS units, that is 4 * 64 bytes. These 4 CCS units are in
 		 * turn mapped by one L1 AUX page table entry.
 		 */
+		aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
+		aux_height = intel_buf_ccs_height(bops->intel_gen, buf);
 
-		if (!HAS_FLATCCS(intel_get_drm_devid(bops->fd))) {
-			int aux_width, aux_height;
-
-			aux_width = intel_buf_ccs_width(bops->intel_gen, buf);
-			aux_height = intel_buf_ccs_height(bops->intel_gen, buf);
-
-			buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
-			buf->ccs[0].stride = aux_width;
-			size = buf->ccs[0].offset + aux_width * aux_height;
-		}
+		buf->ccs[0].offset = buf->surface[0].stride * ALIGN(height, 32);
+		buf->ccs[0].stride = aux_width;
+		size = buf->ccs[0].offset + aux_width * aux_height;
 	}
 
 	/* Store buffer size to avoid mistakes in calculating it again */
-- 
2.34.1

[PATCH i-g-t v5 05/11] lib/intel_bufops: Start supporting compression on Xe2+

[Zbigniew Kempczyński]

Xe2+ uses unified compression where PAT index determines using
compressed pages so lets add support of that to intel-buf. It is
necessary to run render-copy with compression on those platforms.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_bufops.c | 31 +++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 7118272e5f..52a5f322ea 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -934,8 +934,14 @@ static void __intel_buf_init(struct buf_ops *bops,
 			if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &bo_size, region))
 				igt_assert_eq(__gem_create(bops->fd, &bo_size, &buf->handle), 0);
 		} else {
+			uint16_t cpu_caching = __xe_default_cpu_caching(bops->fd, region, 0);
+
+			if (AT_LEAST_GEN(bops->devid, 20) && compression)
+				cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
+
 			bo_size = ALIGN(bo_size, xe_get_default_alignment(bops->fd));
-			buf->handle = xe_bo_create(bops->fd, 0, bo_size, region, 0);
+			buf->handle = xe_bo_create_caching(bops->fd, 0, bo_size, region, 0,
+							   cpu_caching);
 		}
 	}
 
@@ -970,11 +976,16 @@ void intel_buf_init(struct buf_ops *bops,
 		    uint32_t tiling, uint32_t compression)
 {
 	uint64_t region;
+	uint8_t pat_index = DEFAULT_PAT_INDEX;
+
+	if (compression && AT_LEAST_GEN(bops->devid, 20))
+		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
 
 	region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY :
 						     system_memory(bops->fd);
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
-			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
+			 tiling, compression, 0, 0, region,
+			 pat_index,
 			 DEFAULT_MOCS_INDEX);
 
 	intel_buf_set_ownership(buf, true);
@@ -991,8 +1002,14 @@ void intel_buf_init_in_region(struct buf_ops *bops,
 			      uint32_t tiling, uint32_t compression,
 			      uint64_t region)
 {
+	uint8_t pat_index = DEFAULT_PAT_INDEX;
+
+	if (compression && AT_LEAST_GEN(bops->devid, 20))
+		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
+
 	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
-			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
+			 tiling, compression, 0, 0, region,
+			 pat_index,
 			 DEFAULT_MOCS_INDEX);
 
 	intel_buf_set_ownership(buf, true);
@@ -1053,10 +1070,16 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
 					  uint32_t req_tiling, uint32_t compression,
 					  uint64_t size)
 {
+	uint8_t pat_index = DEFAULT_PAT_INDEX;
+
 	igt_assert(handle);
 	igt_assert(size);
+
+	if (compression && AT_LEAST_GEN(bops->devid, 20))
+		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
+
 	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
-			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX,
+			 req_tiling, compression, size, 0, -1, pat_index,
 			 DEFAULT_MOCS_INDEX);
 }
 
-- 
2.34.1

Re: [PATCH i-g-t v5 05/11] lib/intel_bufops: Start supporting compression on Xe2+

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> Xe2+ uses unified compression where PAT index determines using
> compressed pages so lets add support of that to intel-buf. It is
> necessary to run render-copy with compression on those platforms.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>   lib/intel_bufops.c | 31 +++++++++++++++++++++++++++----
>   1 file changed, 27 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> index 7118272e5f..52a5f322ea 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -934,8 +934,14 @@ static void __intel_buf_init(struct buf_ops *bops,
>   			if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &bo_size, region))
>   				igt_assert_eq(__gem_create(bops->fd, &bo_size, &buf->handle), 0);
>   		} else {
> +			uint16_t cpu_caching = __xe_default_cpu_caching(bops->fd, region, 0);
> +
> +			if (AT_LEAST_GEN(bops->devid, 20) && compression)
> +				cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
> +
>   			bo_size = ALIGN(bo_size, xe_get_default_alignment(bops->fd));
> -			buf->handle = xe_bo_create(bops->fd, 0, bo_size, region, 0);
> +			buf->handle = xe_bo_create_caching(bops->fd, 0, bo_size, region, 0,
> +							   cpu_caching);
>   		}
>   	}
>   
> @@ -970,11 +976,16 @@ void intel_buf_init(struct buf_ops *bops,
>   		    uint32_t tiling, uint32_t compression)
>   {
>   	uint64_t region;
> +	uint8_t pat_index = DEFAULT_PAT_INDEX;
> +
> +	if (compression && AT_LEAST_GEN(bops->devid, 20))
> +		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
>   
>   	region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY :
>   						     system_memory(bops->fd);
>   	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
> -			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
> +			 tiling, compression, 0, 0, region,
> +			 pat_index,
>   			 DEFAULT_MOCS_INDEX);
>   
>   	intel_buf_set_ownership(buf, true);
> @@ -991,8 +1002,14 @@ void intel_buf_init_in_region(struct buf_ops *bops,
>   			      uint32_t tiling, uint32_t compression,
>   			      uint64_t region)
>   {
> +	uint8_t pat_index = DEFAULT_PAT_INDEX;
> +
> +	if (compression && AT_LEAST_GEN(bops->devid, 20))
> +		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
> +
>   	__intel_buf_init(bops, 0, buf, width, height, bpp, alignment,
> -			 tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX,
> +			 tiling, compression, 0, 0, region,
> +			 pat_index,
>   			 DEFAULT_MOCS_INDEX);
>   
>   	intel_buf_set_ownership(buf, true);
> @@ -1053,10 +1070,16 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops,
>   					  uint32_t req_tiling, uint32_t compression,
>   					  uint64_t size)
>   {
> +	uint8_t pat_index = DEFAULT_PAT_INDEX;
> +
>   	igt_assert(handle);
>   	igt_assert(size);
> +
> +	if (compression && AT_LEAST_GEN(bops->devid, 20))
> +		pat_index = intel_get_pat_idx_uc_comp(bops->fd);
> +
>   	__intel_buf_init(bops, handle, buf, width, height, bpp, alignment,
> -			 req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX,
> +			 req_tiling, compression, size, 0, -1, pat_index,
>   			 DEFAULT_MOCS_INDEX);
>   }
>   

[PATCH i-g-t v5 06/11] lib/rendercopy_gen9: Separate xe and xe2 compression format

[Zbigniew Kempczyński]

Xe and beyond differ how compression format is handled. For Xe it
is 5-bit long whereas for Xe2+ this is 4-bit long field. Instead of
artifically packing 0-15 into 5-bit field lets separate this structures
to conform with the documentation.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 lib/gen9_render.h     | 31 +++++++++++++++++++++----------
 lib/rendercopy_gen9.c | 24 ++++++++++++++++--------
 2 files changed, 37 insertions(+), 18 deletions(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 8ed60a2a54..4c1ed4726a 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -154,16 +154,27 @@ struct gen9_surface_state {
 		uint32_t aux_base_addr_hi;
 	} ss11;
 
-	struct {
-		/*
-		 * compression_format is used only dg2 onward.
-		 * prior to dg2 full ss12 is used for the address
-		 * but due to alignments bits 0..6 will be zero
-		 * and asserted in code to be so
-		 */
-		uint32_t compression_format:5;
-		uint32_t pad0:1;
-		uint32_t clear_address:26;
+	union {
+		struct {
+			/*
+			 * compression_format is used only dg2 onward.
+			 * prior to dg2 full ss12 is used for the address
+			 * but due to alignments bits 0..6 will be zero
+			 * and asserted in code to be so
+			 */
+			uint32_t compression_format:5;
+			uint32_t pad0:1;
+			uint32_t clear_address:26;
+		} xe;
+
+		struct {
+			/*
+			 * On Xe2+ compression format is 4-bit long.
+			 */
+			uint32_t compression_format:4;
+			uint32_t mip_region_depth_in_log:4;
+			uint32_t pad0:24;
+		} xe2;
 	} ss12;
 
 	struct {
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 7c7563d50c..35d79acbab 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -264,7 +264,7 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 			igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 &&
 				   (__builtin_clzl(address + buf->cc.offset) >= 16));
 
-			ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
+			ss->ss12.xe.clear_address = (address + buf->cc.offset) >> 6;
 			ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
 		}
 
@@ -274,13 +274,21 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 			ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1;
 			ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1;
 
-			/*
-			 * For now here is coming only 32bpp rgb format
-			 * which is marked below as B8G8R8X8_UNORM = '8'
-			 * If here ever arrive other formats below need to be
-			 * fixed to take that into account.
-			 */
-			ss->ss12.compression_format = 8;
+			if (AT_LEAST_GEN(ibb->devid, 20)) {
+				/*
+				 * For Xe2+ R8G8B8A8 best compression ratio is
+				 * achieved with compression format = '2'
+				 */
+				ss->ss12.xe2.compression_format = 2;
+			} else {
+				/*
+				 * For now here is coming only 32bpp rgb format
+				 * which is marked below as B8G8R8X8_UNORM = '8'
+				 * If here ever arrive other formats below need to be
+				 * fixed to take that into account.
+				 */
+				ss->ss12.xe.compression_format = 8;
+			}
 		}
 	}
 
-- 
2.34.1

Re: [PATCH i-g-t v5 06/11] lib/rendercopy_gen9: Separate xe and xe2 compression format

[Juha-Pekka Heikkila]

On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> Xe and beyond differ how compression format is handled. For Xe it
> is 5-bit long whereas for Xe2+ this is 4-bit long field. Instead of
> artifically packing 0-15 into 5-bit field lets separate this structures
> to conform with the documentation.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>   lib/gen9_render.h     | 31 +++++++++++++++++++++----------
>   lib/rendercopy_gen9.c | 24 ++++++++++++++++--------
>   2 files changed, 37 insertions(+), 18 deletions(-)
> 
> diff --git a/lib/gen9_render.h b/lib/gen9_render.h
> index 8ed60a2a54..4c1ed4726a 100644
> --- a/lib/gen9_render.h
> +++ b/lib/gen9_render.h
> @@ -154,16 +154,27 @@ struct gen9_surface_state {
>   		uint32_t aux_base_addr_hi;
>   	} ss11;
>   
> -	struct {
> -		/*
> -		 * compression_format is used only dg2 onward.
> -		 * prior to dg2 full ss12 is used for the address
> -		 * but due to alignments bits 0..6 will be zero
> -		 * and asserted in code to be so
> -		 */
> -		uint32_t compression_format:5;
> -		uint32_t pad0:1;
> -		uint32_t clear_address:26;
> +	union {
> +		struct {
> +			/*
> +			 * compression_format is used only dg2 onward.
> +			 * prior to dg2 full ss12 is used for the address
> +			 * but due to alignments bits 0..6 will be zero
> +			 * and asserted in code to be so
> +			 */
> +			uint32_t compression_format:5;
> +			uint32_t pad0:1;
> +			uint32_t clear_address:26;
> +		} xe;
> +
> +		struct {
> +			/*
> +			 * On Xe2+ compression format is 4-bit long.
> +			 */
> +			uint32_t compression_format:4;
> +			uint32_t mip_region_depth_in_log:4;
> +			uint32_t pad0:24;
> +		} xe2;

I'd prefer here use same naming convention as with rest of the 
structure. Ie. xe would become dg2 as commented above and xe2 I figure 
is likely lnl.

otherwise everything look ok, with those fixed

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

>   	} ss12;
>   
>   	struct {
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 7c7563d50c..35d79acbab 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -264,7 +264,7 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
>   			igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 &&
>   				   (__builtin_clzl(address + buf->cc.offset) >= 16));
>   
> -			ss->ss12.clear_address = (address + buf->cc.offset) >> 6;
> +			ss->ss12.xe.clear_address = (address + buf->cc.offset) >> 6;
>   			ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32;
>   		}
>   
> @@ -274,13 +274,21 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
>   			ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1;
>   			ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1;
>   
> -			/*
> -			 * For now here is coming only 32bpp rgb format
> -			 * which is marked below as B8G8R8X8_UNORM = '8'
> -			 * If here ever arrive other formats below need to be
> -			 * fixed to take that into account.
> -			 */
> -			ss->ss12.compression_format = 8;
> +			if (AT_LEAST_GEN(ibb->devid, 20)) {
> +				/*
> +				 * For Xe2+ R8G8B8A8 best compression ratio is
> +				 * achieved with compression format = '2'
> +				 */
> +				ss->ss12.xe2.compression_format = 2;
> +			} else {
> +				/*
> +				 * For now here is coming only 32bpp rgb format
> +				 * which is marked below as B8G8R8X8_UNORM = '8'
> +				 * If here ever arrive other formats below need to be
> +				 * fixed to take that into account.
> +				 */
> +				ss->ss12.xe.compression_format = 8;
> +			}
>   		}
>   	}
>   

[PATCH i-g-t v5 07/11] lib/intel_cmds_info: Define tiling macros

[Zbigniew Kempczyński]

Blitter tilings don't always matches supported render tilings so
it is necessary to add separate fields for this purpose. To avoid
multiple lines where supported tiling is glued with BIT(tiling)
it is worth to predefine them, especially they will be used in next
patch related to supported render copy tilings.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
v3: Predefine single tiling first, then complex (Karolina)
---
 lib/intel_cmds_info.c | 110 +++++++++++++++++-------------------------
 1 file changed, 45 insertions(+), 65 deletions(-)

diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index 669d3e5006..e7aabf6bfb 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -20,75 +20,59 @@
 		.flags = _flags, \
 	}
 
-static const struct blt_cmd_info src_copy = BLT_INFO(SRC_COPY, BIT(T_LINEAR));
-static const struct blt_cmd_info
-		pre_gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY,
-						BIT(T_LINEAR) |
-						BIT(T_XMAJOR));
-static const struct blt_cmd_info
-		gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY,
-					    BIT(T_LINEAR) |
-					    BIT(T_XMAJOR) |
-					    BIT(T_YMAJOR));
-static const struct blt_cmd_info
-		gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
-					      BIT(T_LINEAR)  |
-					      BIT(T_YMAJOR)  |
-					      BIT(T_YFMAJOR) |
-					      BIT(T_TILE64));
-static const struct blt_cmd_info
-		gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
-					      BIT(T_LINEAR) |
-					      BIT(T_YMAJOR) |
-					      BIT(T_TILE4)  |
-					      BIT(T_TILE64));
-static const struct blt_cmd_info
-		dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
-					    BIT(T_LINEAR) |
-					    BIT(T_XMAJOR) |
-					    BIT(T_TILE4)  |
-					    BIT(T_TILE64));
-static const struct blt_cmd_info
-		pvc_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
-					    BIT(T_LINEAR) |
-					    BIT(T_TILE4)  |
-					    BIT(T_TILE64));
-
-static const struct blt_cmd_info
-		gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
-					       BIT(T_LINEAR) |
-					       BIT(T_YMAJOR));
-static const struct blt_cmd_info
-		dg2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
-						 BIT(T_LINEAR) |
-						 BIT(T_XMAJOR) |
-						 BIT(T_TILE4)  |
-						 BIT(T_TILE64),
+#define TILE_4		BIT(T_TILE4)
+#define TILE_64		BIT(T_TILE64)
+#define TILE_L		BIT(T_LINEAR)
+#define TILE_X		BIT(T_XMAJOR)
+#define TILE_Y		BIT(T_YMAJOR)
+#define TILE_Yf		BIT(T_YFMAJOR)
+
+#define TILE_L_4_64	(TILE_L | TILE_4 | TILE_64)
+#define TILE_L_X	(TILE_L | TILE_X)
+#define TILE_L_X_Y	(TILE_L | TILE_X | TILE_Y)
+#define TILE_L_X_4_64	(TILE_L | TILE_X | TILE_4 | TILE_64)
+#define TILE_L_Y	(TILE_L | TILE_Y)
+#define TILE_L_Y_4_64	(TILE_L | TILE_Y | TILE_4 | TILE_64)
+#define TILE_L_Y_Yf_64	(TILE_L | TILE_Y | TILE_Yf | TILE_64)
+
+static const struct blt_cmd_info src_copy = BLT_INFO(SRC_COPY, TILE_L);
+static const struct blt_cmd_info
+		pre_gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY, TILE_L_X);
+
+static const struct blt_cmd_info
+		gen6_xy_src_copy = BLT_INFO(XY_SRC_COPY, TILE_L_X_Y);
+
+static const struct blt_cmd_info
+		gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_Y_Yf_64);
+
+static const struct blt_cmd_info
+		gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_Y_4_64);
+
+static const struct blt_cmd_info
+		dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_X_4_64);
+
+static const struct blt_cmd_info
+		pvc_xy_fast_copy = BLT_INFO(XY_FAST_COPY, TILE_L_4_64);
+
+static const struct blt_cmd_info
+		gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY, TILE_L_Y);
+
+static const struct blt_cmd_info
+		dg2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
 						 BLT_CMD_EXTENDED |
 						 BLT_CMD_SUPPORTS_COMPRESSION);
 
 static const struct blt_cmd_info
-		xe2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
-						 BIT(T_LINEAR) |
-						 BIT(T_XMAJOR) |
-						 BIT(T_TILE4)  |
-						 BIT(T_TILE64),
+		xe2_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
 						 BLT_CMD_EXTENDED |
 						 BLT_CMD_SUPPORTS_COMPRESSION);
 
 static const struct blt_cmd_info
-		mtl_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
-						 BIT(T_LINEAR) |
-						 BIT(T_XMAJOR) |
-						 BIT(T_TILE4)  |
-						 BIT(T_TILE64),
+		mtl_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_X_4_64,
 						 BLT_CMD_EXTENDED);
 
 static const struct blt_cmd_info
-		pvc_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY,
-						 BIT(T_LINEAR) |
-						 BIT(T_TILE4)  |
-						 BIT(T_TILE64),
+		pvc_xy_block_copy = BLT_INFO_EXT(XY_BLOCK_COPY, TILE_L_4_64,
 						 BLT_CMD_EXTENDED);
 
 static const struct blt_cmd_info
@@ -102,17 +86,13 @@ static const struct blt_cmd_info
 				       BIT(M_MATRIX));
 
 static const struct blt_cmd_info
-		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
-						 BIT(T_LINEAR) |
-						 BIT(T_XMAJOR));
+		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT, TILE_L_X);
 
 static const struct blt_cmd_info
-		gen6_xy_color_blt = BLT_INFO_EXT(XY_COLOR_BLT,
-						 BIT(T_LINEAR) |
-						 BIT(T_YMAJOR) |
-						 BIT(T_XMAJOR),
+		gen6_xy_color_blt = BLT_INFO_EXT(XY_COLOR_BLT, TILE_L_X_Y,
 						 BLT_CMD_EXTENDED);
 
+
 const struct intel_cmds_info pre_gen6_cmds_info = {
 	.blt_cmds = {
 		[SRC_COPY] = &src_copy,
-- 
2.34.1

[PATCH i-g-t v5 08/11] lib/intel_cmds_info: Introduce render tilings

[Zbigniew Kempczyński]

Due to hardware differences between blitter and render regarding
supported tilings and compression add new fields in cmds-info
to identify available tilings via render engine.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_cmds_info.c | 31 +++++++++++++++++++++++++++----
 lib/intel_cmds_info.h |  6 ++++++
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index e7aabf6bfb..3f04f24f3c 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -27,8 +27,10 @@
 #define TILE_Y		BIT(T_YMAJOR)
 #define TILE_Yf		BIT(T_YFMAJOR)
 
+#define TILE_4_64	(TILE_4 | TILE_64)
 #define TILE_L_4_64	(TILE_L | TILE_4 | TILE_64)
 #define TILE_L_X	(TILE_L | TILE_X)
+#define TILE_L_X_4	(TILE_L | TILE_X | TILE_4)
 #define TILE_L_X_Y	(TILE_L | TILE_X | TILE_Y)
 #define TILE_L_X_4_64	(TILE_L | TILE_X | TILE_4 | TILE_64)
 #define TILE_L_Y	(TILE_L | TILE_Y)
@@ -93,6 +95,23 @@ static const struct blt_cmd_info
 						 BLT_CMD_EXTENDED);
 
 
+#define RENDER_TILING(_tiling, _compress_tiling)  { \
+		.supported_tiling = _tiling, \
+		.supported_compressed_tiling = _compress_tiling, \
+	}
+
+static const struct render_tiling_info
+		render_tiling_gen12 = RENDER_TILING(TILE_L_X_4, TILE_4);
+
+static const struct render_tiling_info
+		render_tiling_mtl = RENDER_TILING(TILE_L_X_4_64, TILE_4);
+
+static const struct render_tiling_info
+		render_tiling_dg2 = RENDER_TILING(TILE_L_X_4_64, TILE_4_64);
+
+static const struct render_tiling_info
+		render_tiling_xe2 = RENDER_TILING(TILE_L_X_4_64, TILE_L_X_4_64);
+
 const struct intel_cmds_info pre_gen6_cmds_info = {
 	.blt_cmds = {
 		[SRC_COPY] = &src_copy,
@@ -130,7 +149,8 @@ const struct intel_cmds_info gen12_cmds_info = {
 		[XY_FAST_COPY] = &gen12_xy_fast_copy,
 		[XY_BLOCK_COPY] = &gen12_xy_block_copy,
 		[XY_COLOR_BLT] = &gen6_xy_color_blt,
-	}
+	},
+	.render_tilings = &render_tiling_gen12,
 };
 
 const struct intel_cmds_info gen12_dg2_cmds_info = {
@@ -139,14 +159,16 @@ const struct intel_cmds_info gen12_dg2_cmds_info = {
 		[XY_FAST_COPY] = &dg2_xy_fast_copy,
 		[XY_BLOCK_COPY] = &dg2_xy_block_copy,
 		[XY_COLOR_BLT] = &gen6_xy_color_blt,
-	}
+	},
+	.render_tilings = &render_tiling_dg2,
 };
 
 const struct intel_cmds_info gen12_mtl_cmds_info = {
 	.blt_cmds = {
 		[XY_FAST_COPY] = &dg2_xy_fast_copy,
 		[XY_BLOCK_COPY] = &mtl_xy_block_copy,
-	}
+	},
+	.render_tilings = &render_tiling_mtl,
 };
 
 const struct intel_cmds_info gen12_pvc_cmds_info = {
@@ -164,7 +186,8 @@ const struct intel_cmds_info xe2_cmds_info  = {
 		[XY_BLOCK_COPY] = &xe2_xy_block_copy,
 		[MEM_COPY] = &pvc_mem_copy,
 		[MEM_SET] = &pvc_mem_set,
-	}
+	},
+	.render_tilings = &render_tiling_xe2,
 };
 
 const struct blt_cmd_info *blt_get_cmd_info(const struct intel_cmds_info *cmds_info,
diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
index 0a83b6a446..6f7d655083 100644
--- a/lib/intel_cmds_info.h
+++ b/lib/intel_cmds_info.h
@@ -43,8 +43,14 @@ struct blt_cmd_info {
 #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
 };
 
+struct render_tiling_info {
+	uint32_t supported_tiling;
+	uint32_t supported_compressed_tiling;
+};
+
 struct intel_cmds_info {
 	struct blt_cmd_info const *blt_cmds[__BLT_MAX_CMD];
+	struct render_tiling_info const *render_tilings;
 };
 
 extern const struct intel_cmds_info pre_gen6_cmds_info;
-- 
2.34.1

Re: [PATCH i-g-t v5 08/11] lib/intel_cmds_info: Introduce render tilings

[Juha-Pekka Heikkila]

On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> Due to hardware differences between blitter and render regarding
> supported tilings and compression add new fields in cmds-info
> to identify available tilings via render engine.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>   lib/intel_cmds_info.c | 31 +++++++++++++++++++++++++++----
>   lib/intel_cmds_info.h |  6 ++++++
>   2 files changed, 33 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
> index e7aabf6bfb..3f04f24f3c 100644
> --- a/lib/intel_cmds_info.c
> +++ b/lib/intel_cmds_info.c
> @@ -27,8 +27,10 @@
>   #define TILE_Y		BIT(T_YMAJOR)
>   #define TILE_Yf		BIT(T_YFMAJOR)
>   
> +#define TILE_4_64	(TILE_4 | TILE_64)
>   #define TILE_L_4_64	(TILE_L | TILE_4 | TILE_64)
>   #define TILE_L_X	(TILE_L | TILE_X)
> +#define TILE_L_X_4	(TILE_L | TILE_X | TILE_4)
>   #define TILE_L_X_Y	(TILE_L | TILE_X | TILE_Y)
>   #define TILE_L_X_4_64	(TILE_L | TILE_X | TILE_4 | TILE_64)
>   #define TILE_L_Y	(TILE_L | TILE_Y)
> @@ -93,6 +95,23 @@ static const struct blt_cmd_info
>   						 BLT_CMD_EXTENDED);
>   
>   
> +#define RENDER_TILING(_tiling, _compress_tiling)  { \
> +		.supported_tiling = _tiling, \
> +		.supported_compressed_tiling = _compress_tiling, \
> +	}
> +
> +static const struct render_tiling_info
> +		render_tiling_gen12 = RENDER_TILING(TILE_L_X_4, TILE_4);

Is this correct? I'm thinking for gen12 here would say 
RENDER_TILING(TILE_L_X_Y, TILE_Y); ?

> +
> +static const struct render_tiling_info
> +		render_tiling_mtl = RENDER_TILING(TILE_L_X_4_64, TILE_4);
> +
> +static const struct render_tiling_info
> +		render_tiling_dg2 = RENDER_TILING(TILE_L_X_4_64, TILE_4_64);
> +
> +static const struct render_tiling_info
> +		render_tiling_xe2 = RENDER_TILING(TILE_L_X_4_64, TILE_L_X_4_64);
> +
>   const struct intel_cmds_info pre_gen6_cmds_info = {
>   	.blt_cmds = {
>   		[SRC_COPY] = &src_copy,
> @@ -130,7 +149,8 @@ const struct intel_cmds_info gen12_cmds_info = {
>   		[XY_FAST_COPY] = &gen12_xy_fast_copy,
>   		[XY_BLOCK_COPY] = &gen12_xy_block_copy,
>   		[XY_COLOR_BLT] = &gen6_xy_color_blt,
> -	}
> +	},
> +	.render_tilings = &render_tiling_gen12,
>   };
>   
>   const struct intel_cmds_info gen12_dg2_cmds_info = {
> @@ -139,14 +159,16 @@ const struct intel_cmds_info gen12_dg2_cmds_info = {
>   		[XY_FAST_COPY] = &dg2_xy_fast_copy,
>   		[XY_BLOCK_COPY] = &dg2_xy_block_copy,
>   		[XY_COLOR_BLT] = &gen6_xy_color_blt,
> -	}
> +	},
> +	.render_tilings = &render_tiling_dg2,
>   };
>   
>   const struct intel_cmds_info gen12_mtl_cmds_info = {
>   	.blt_cmds = {
>   		[XY_FAST_COPY] = &dg2_xy_fast_copy,
>   		[XY_BLOCK_COPY] = &mtl_xy_block_copy,
> -	}
> +	},
> +	.render_tilings = &render_tiling_mtl,
>   };
>   
>   const struct intel_cmds_info gen12_pvc_cmds_info = {
> @@ -164,7 +186,8 @@ const struct intel_cmds_info xe2_cmds_info  = {
>   		[XY_BLOCK_COPY] = &xe2_xy_block_copy,
>   		[MEM_COPY] = &pvc_mem_copy,
>   		[MEM_SET] = &pvc_mem_set,
> -	}
> +	},
> +	.render_tilings = &render_tiling_xe2,
>   };
>   
>   const struct blt_cmd_info *blt_get_cmd_info(const struct intel_cmds_info *cmds_info,
> diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
> index 0a83b6a446..6f7d655083 100644
> --- a/lib/intel_cmds_info.h
> +++ b/lib/intel_cmds_info.h
> @@ -43,8 +43,14 @@ struct blt_cmd_info {
>   #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
>   };
>   
> +struct render_tiling_info {
> +	uint32_t supported_tiling;
> +	uint32_t supported_compressed_tiling;
> +};
> +
>   struct intel_cmds_info {
>   	struct blt_cmd_info const *blt_cmds[__BLT_MAX_CMD];
> +	struct render_tiling_info const *render_tilings;
>   };
>   
>   extern const struct intel_cmds_info pre_gen6_cmds_info;

Re: [PATCH i-g-t v5 08/11] lib/intel_cmds_info: Introduce render tilings

[Zbigniew Kempczyński]

On Tue, May 14, 2024 at 08:26:15PM +0300, Juha-Pekka Heikkila wrote:
> On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> > Due to hardware differences between blitter and render regarding
> > supported tilings and compression add new fields in cmds-info
> > to identify available tilings via render engine.
> > 
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> >   lib/intel_cmds_info.c | 31 +++++++++++++++++++++++++++----
> >   lib/intel_cmds_info.h |  6 ++++++
> >   2 files changed, 33 insertions(+), 4 deletions(-)
> > 
> > diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
> > index e7aabf6bfb..3f04f24f3c 100644
> > --- a/lib/intel_cmds_info.c
> > +++ b/lib/intel_cmds_info.c
> > @@ -27,8 +27,10 @@
> >   #define TILE_Y		BIT(T_YMAJOR)
> >   #define TILE_Yf		BIT(T_YFMAJOR)
> > +#define TILE_4_64	(TILE_4 | TILE_64)
> >   #define TILE_L_4_64	(TILE_L | TILE_4 | TILE_64)
> >   #define TILE_L_X	(TILE_L | TILE_X)
> > +#define TILE_L_X_4	(TILE_L | TILE_X | TILE_4)
> >   #define TILE_L_X_Y	(TILE_L | TILE_X | TILE_Y)
> >   #define TILE_L_X_4_64	(TILE_L | TILE_X | TILE_4 | TILE_64)
> >   #define TILE_L_Y	(TILE_L | TILE_Y)
> > @@ -93,6 +95,23 @@ static const struct blt_cmd_info
> >   						 BLT_CMD_EXTENDED);
> > +#define RENDER_TILING(_tiling, _compress_tiling)  { \
> > +		.supported_tiling = _tiling, \
> > +		.supported_compressed_tiling = _compress_tiling, \
> > +	}
> > +
> > +static const struct render_tiling_info
> > +		render_tiling_gen12 = RENDER_TILING(TILE_L_X_4, TILE_4);
> 
> Is this correct? I'm thinking for gen12 here would say
> RENDER_TILING(TILE_L_X_Y, TILE_Y); ?

I've just written tiling detection tool and it reports render is able
to use L/X/Y/Yf tilings (software tile64 is not yet implemented).
So you are right, it should be TILE_L_X_Y. I'm going to experiment
and update the supported tilings in intel_cmds_info.c later.

--
Zbigniew

> 
> > +
> > +static const struct render_tiling_info
> > +		render_tiling_mtl = RENDER_TILING(TILE_L_X_4_64, TILE_4);
> > +
> > +static const struct render_tiling_info
> > +		render_tiling_dg2 = RENDER_TILING(TILE_L_X_4_64, TILE_4_64);
> > +
> > +static const struct render_tiling_info
> > +		render_tiling_xe2 = RENDER_TILING(TILE_L_X_4_64, TILE_L_X_4_64);
> > +
> >   const struct intel_cmds_info pre_gen6_cmds_info = {
> >   	.blt_cmds = {
> >   		[SRC_COPY] = &src_copy,
> > @@ -130,7 +149,8 @@ const struct intel_cmds_info gen12_cmds_info = {
> >   		[XY_FAST_COPY] = &gen12_xy_fast_copy,
> >   		[XY_BLOCK_COPY] = &gen12_xy_block_copy,
> >   		[XY_COLOR_BLT] = &gen6_xy_color_blt,
> > -	}
> > +	},
> > +	.render_tilings = &render_tiling_gen12,
> >   };
> >   const struct intel_cmds_info gen12_dg2_cmds_info = {
> > @@ -139,14 +159,16 @@ const struct intel_cmds_info gen12_dg2_cmds_info = {
> >   		[XY_FAST_COPY] = &dg2_xy_fast_copy,
> >   		[XY_BLOCK_COPY] = &dg2_xy_block_copy,
> >   		[XY_COLOR_BLT] = &gen6_xy_color_blt,
> > -	}
> > +	},
> > +	.render_tilings = &render_tiling_dg2,
> >   };
> >   const struct intel_cmds_info gen12_mtl_cmds_info = {
> >   	.blt_cmds = {
> >   		[XY_FAST_COPY] = &dg2_xy_fast_copy,
> >   		[XY_BLOCK_COPY] = &mtl_xy_block_copy,
> > -	}
> > +	},
> > +	.render_tilings = &render_tiling_mtl,
> >   };
> >   const struct intel_cmds_info gen12_pvc_cmds_info = {
> > @@ -164,7 +186,8 @@ const struct intel_cmds_info xe2_cmds_info  = {
> >   		[XY_BLOCK_COPY] = &xe2_xy_block_copy,
> >   		[MEM_COPY] = &pvc_mem_copy,
> >   		[MEM_SET] = &pvc_mem_set,
> > -	}
> > +	},
> > +	.render_tilings = &render_tiling_xe2,
> >   };
> >   const struct blt_cmd_info *blt_get_cmd_info(const struct intel_cmds_info *cmds_info,
> > diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
> > index 0a83b6a446..6f7d655083 100644
> > --- a/lib/intel_cmds_info.h
> > +++ b/lib/intel_cmds_info.h
> > @@ -43,8 +43,14 @@ struct blt_cmd_info {
> >   #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
> >   };
> > +struct render_tiling_info {
> > +	uint32_t supported_tiling;
> > +	uint32_t supported_compressed_tiling;
> > +};
> > +
> >   struct intel_cmds_info {
> >   	struct blt_cmd_info const *blt_cmds[__BLT_MAX_CMD];
> > +	struct render_tiling_info const *render_tilings;
> >   };
> >   extern const struct intel_cmds_info pre_gen6_cmds_info;
> 

[PATCH i-g-t v5 09/11] lib/intel_blt: Add render tilings and compression support helper

[Zbigniew Kempczyński]

Add function which is similar to already existing blt supports_tiling()
but returns tiling/compression capabilities of render engine.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 lib/intel_blt.c | 29 +++++++++++++++++++++++++++++
 lib/intel_blt.h |  1 +
 2 files changed, 30 insertions(+)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 946adc538b..a8433387d2 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -495,6 +495,35 @@ bool blt_uses_extended_block_copy(int fd)
 	return blt_cmd_has_property(cmds_info, XY_BLOCK_COPY, BLT_CMD_EXTENDED);
 }
 
+/**
+ * render_supports_tiling
+ * @fd: drm fd
+ * @tiling: tiling format
+ * @compression: check tiling which will be compressed
+ *
+ * Check if render provided by @fd device supports @tiling format wrt
+ * @compression
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool render_supports_tiling(int fd, enum blt_tiling_type tiling, bool compression)
+{
+	const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(fd);
+
+	igt_assert(cmds_info);
+
+	if (!cmds_info->render_tilings) {
+		igt_warn("Render tilings are not defined\n");
+		return false;
+	}
+
+	if (!compression)
+		return cmds_info->render_tilings->supported_tiling & BIT(tiling);
+
+	return cmds_info->render_tilings->supported_compressed_tiling & BIT(tiling);
+}
+
 /**
  * blt_tiling_name:
  * @tiling: tiling id
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 6daf46aea4..edf75c0887 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -211,6 +211,7 @@ bool blt_xy_src_copy_supports_tiling(int fd, enum blt_tiling_type tiling);
 bool blt_block_copy_supports_compression(int fd);
 bool blt_platform_has_flat_ccs_enabled(int fd);
 bool blt_uses_extended_block_copy(int fd);
+bool render_supports_tiling(int fd, enum blt_tiling_type tiling, bool compression);
 
 const char *blt_tiling_name(enum blt_tiling_type tiling);
 int blt_tile_to_i915_tile(enum blt_tiling_type tiling);
-- 
2.34.1

[PATCH i-g-t v5 10/11] tests/xe_render_copy: Add subtest which exercises compression

[Zbigniew Kempczyński]

Add subtest which iterates over all supported tilings and does
render-copy to and from compressed surface.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_render_copy.c | 91 ++++++++++++++++++++++++++++++++++--
 1 file changed, 86 insertions(+), 5 deletions(-)

diff --git a/tests/intel/xe_render_copy.c b/tests/intel/xe_render_copy.c
index ef75c4ce6d..6f6c2e39bf 100644
--- a/tests/intel/xe_render_copy.c
+++ b/tests/intel/xe_render_copy.c
@@ -37,6 +37,10 @@
  *
  * SUBTEST: render-full
  * Description: Copy surface using 3d engine (1:1)
+ *
+ * SUBTEST: render-full-compressed
+ * Description: Copy surface using 3d engine (1:1) when intermediate surface
+ *              is compressed
  */
 #define WIDTH	256
 #define HEIGHT	256
@@ -56,9 +60,13 @@ static void scratch_buf_init(struct buf_ops *bops,
 {
 	int fd = buf_ops_get_fd(bops);
 	int bpp = 32;
+	uint64_t region = system_memory(fd);
+
+	if (compression && xe_has_vram(fd))
+		region = vram_memory(fd, 0);
 
 	intel_buf_init_in_region(bops, buf, width, height, bpp, 0,
-				 req_tiling, compression, system_memory(fd));
+				 req_tiling, compression, region);
 
 	igt_assert(intel_buf_width(buf) == width);
 	igt_assert(intel_buf_height(buf) == height);
@@ -120,6 +128,67 @@ static int compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2,
 	return ret;
 }
 
+static bool buf_is_aux_compressed(struct buf_ops *bops, struct intel_buf *buf)
+{
+	int xe = buf_ops_get_fd(bops);
+	unsigned int gen = intel_gen(buf_ops_get_devid(bops));
+	uint32_t ccs_size;
+	uint8_t *ptr;
+	bool is_compressed = false;
+
+	igt_assert_neq(buf->ccs[0].offset, 0);
+
+	ccs_size = intel_buf_ccs_width(gen, buf) * intel_buf_ccs_height(gen, buf);
+	ptr = xe_bo_map(xe, buf->handle, buf->size);
+	for (int i = 0; i < ccs_size; i++)
+		if (ptr[buf->ccs[0].offset + i] != 0) {
+			is_compressed = true;
+			break;
+		}
+	munmap(ptr, buf->size);
+
+	return is_compressed;
+}
+
+static bool buf_is_compressed(struct buf_ops *bops, struct intel_buf *buf)
+{
+	struct drm_xe_engine_class_instance inst = {
+		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
+	};
+	int xe = buf_ops_get_fd(bops);
+	struct blt_copy_object obj;
+	uint64_t ahnd;
+	uint32_t vm, exec_queue;
+	uint32_t tiling = i915_tile_to_blt_tile(buf->tiling);
+	uint32_t devid = buf_ops_get_devid(bops);
+	intel_ctx_t *ctx;
+	bool is_compressed;
+
+	if (!HAS_FLATCCS(devid))
+		return buf_is_aux_compressed(bops, buf);
+
+	vm = xe_vm_create(xe, 0, 0);
+	exec_queue = xe_exec_queue_create(xe, vm, &inst, 0);
+	ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0);
+	ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
+
+	blt_set_object(&obj, buf->handle,
+		       buf->size, buf->region, buf->mocs_index,
+		       buf->pat_index, tiling,
+		       buf->compression ? COMPRESSION_ENABLED : COMPRESSION_DISABLED,
+		       COMPRESSION_TYPE_3D);
+	blt_set_geom(&obj, buf->surface[0].stride, 0, 0, buf->width, buf->height, 0, 0);
+
+	is_compressed = blt_surface_is_compressed(xe, ctx, NULL, ahnd, &obj);
+
+	xe_exec_queue_destroy(xe, exec_queue);
+	xe_vm_destroy(xe, vm);
+	put_ahnd(ahnd);
+	free(ctx);
+
+	return is_compressed;
+}
+
 /*
  *
  * Scenarios implemented are presented below. We copy from linear to and forth
@@ -176,6 +245,7 @@ enum render_copy_testtype {
 	COPY_HSTRIPES,
 	COPY_RANDOM,
 	COPY_FULL,
+	COPY_FULL_COMPRESSED,
 };
 
 static const char * const testname[] = {
@@ -184,6 +254,7 @@ static const char * const testname[] = {
 	[COPY_HSTRIPES]	= "hstripes",
 	[COPY_RANDOM]	= "random",
 	[COPY_FULL]	= "full",
+	[COPY_FULL_COMPRESSED] = "full-compressed",
 };
 
 static int render(struct buf_ops *bops, uint32_t tiling,
@@ -196,6 +267,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
 	uint32_t fails = 0;
 	uint32_t devid = intel_get_drm_devid(xe);
 	igt_render_copyfunc_t render_copy = NULL;
+	int compression = testtype == COPY_FULL_COMPRESSED ? I915_COMPRESSION_RENDER :
+							     I915_COMPRESSION_NONE;
+	bool is_compressed;
 	struct posrc {
 		uint32_t x0, y0;
 		uint32_t x1, y1;
@@ -241,7 +315,7 @@ static int render(struct buf_ops *bops, uint32_t tiling,
 	scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
 			 I915_COMPRESSION_NONE);
 	scratch_buf_init(bops, &dst, width, height, tiling,
-			 I915_COMPRESSION_NONE);
+			 compression);
 	scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
 			 I915_COMPRESSION_NONE);
 	scratch_buf_init(bops, &grfs, 64, height * 4, I915_TILING_NONE,
@@ -317,6 +391,7 @@ static int render(struct buf_ops *bops, uint32_t tiling,
 
 
 	case COPY_FULL:
+	case COPY_FULL_COMPRESSED:
 		render_copy(ibb,
 			    &src, 0, 0, width, height,
 			    &dst, 0, 0);
@@ -339,7 +414,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
 					   tiling, width, height);
 	}
 
-	fails = compare_bufs(&src, &final, true);
+	fails = compare_bufs(&src, &final, false);
+	if (compression == I915_COMPRESSION_RENDER)
+		is_compressed = buf_is_compressed(bops, &dst);
 
 	intel_buf_close(bops, &src);
 	intel_buf_close(bops, &dst);
@@ -347,6 +424,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
 
 	igt_assert_f(fails == 0, "%s: (tiling: %d) fails: %d\n",
 		     __func__, tiling, fails);
+	if (compression == I915_COMPRESSION_RENDER && blt_platform_has_flat_ccs_enabled(xe))
+		igt_assert_f(is_compressed, "%s: (tiling: %d) buffer is not compressed\n",
+			     __func__, tiling);
 
 	return fails;
 }
@@ -398,12 +478,13 @@ igt_main_args("dpiW:H:", NULL, help_str, opt_handler, NULL)
 		srand(time(NULL));
 	}
 
-	for (int id = 0; id <= COPY_FULL; id++) {
+	for (int id = 0; id <= COPY_FULL_COMPRESSED; id++) {
 		igt_subtest_with_dynamic_f("render-%s", testname[id]) {
 			igt_require(xe_has_engine_class(xe, DRM_XE_ENGINE_CLASS_RENDER));
 
 			for_each_tiling(tiling) {
-				if (!blt_block_copy_supports_tiling(xe, tiling))
+				if (!render_supports_tiling(xe, tiling,
+							    id == COPY_FULL_COMPRESSED))
 					continue;
 
 				tiling_name = blt_tiling_name(tiling);
-- 
2.34.1

Re: [PATCH i-g-t v5 10/11] tests/xe_render_copy: Add subtest which exercises compression

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> Add subtest which iterates over all supported tilings and does
> render-copy to and from compressed surface.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>   tests/intel/xe_render_copy.c | 91 ++++++++++++++++++++++++++++++++++--
>   1 file changed, 86 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/intel/xe_render_copy.c b/tests/intel/xe_render_copy.c
> index ef75c4ce6d..6f6c2e39bf 100644
> --- a/tests/intel/xe_render_copy.c
> +++ b/tests/intel/xe_render_copy.c
> @@ -37,6 +37,10 @@
>    *
>    * SUBTEST: render-full
>    * Description: Copy surface using 3d engine (1:1)
> + *
> + * SUBTEST: render-full-compressed
> + * Description: Copy surface using 3d engine (1:1) when intermediate surface
> + *              is compressed
>    */
>   #define WIDTH	256
>   #define HEIGHT	256
> @@ -56,9 +60,13 @@ static void scratch_buf_init(struct buf_ops *bops,
>   {
>   	int fd = buf_ops_get_fd(bops);
>   	int bpp = 32;
> +	uint64_t region = system_memory(fd);
> +
> +	if (compression && xe_has_vram(fd))
> +		region = vram_memory(fd, 0);
>   
>   	intel_buf_init_in_region(bops, buf, width, height, bpp, 0,
> -				 req_tiling, compression, system_memory(fd));
> +				 req_tiling, compression, region);
>   
>   	igt_assert(intel_buf_width(buf) == width);
>   	igt_assert(intel_buf_height(buf) == height);
> @@ -120,6 +128,67 @@ static int compare_bufs(struct intel_buf *buf1, struct intel_buf *buf2,
>   	return ret;
>   }
>   
> +static bool buf_is_aux_compressed(struct buf_ops *bops, struct intel_buf *buf)
> +{
> +	int xe = buf_ops_get_fd(bops);
> +	unsigned int gen = intel_gen(buf_ops_get_devid(bops));
> +	uint32_t ccs_size;
> +	uint8_t *ptr;
> +	bool is_compressed = false;
> +
> +	igt_assert_neq(buf->ccs[0].offset, 0);
> +
> +	ccs_size = intel_buf_ccs_width(gen, buf) * intel_buf_ccs_height(gen, buf);
> +	ptr = xe_bo_map(xe, buf->handle, buf->size);
> +	for (int i = 0; i < ccs_size; i++)
> +		if (ptr[buf->ccs[0].offset + i] != 0) {
> +			is_compressed = true;
> +			break;
> +		}
> +	munmap(ptr, buf->size);
> +
> +	return is_compressed;
> +}
> +
> +static bool buf_is_compressed(struct buf_ops *bops, struct intel_buf *buf)
> +{
> +	struct drm_xe_engine_class_instance inst = {
> +		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
> +	};
> +	int xe = buf_ops_get_fd(bops);
> +	struct blt_copy_object obj;
> +	uint64_t ahnd;
> +	uint32_t vm, exec_queue;
> +	uint32_t tiling = i915_tile_to_blt_tile(buf->tiling);
> +	uint32_t devid = buf_ops_get_devid(bops);
> +	intel_ctx_t *ctx;
> +	bool is_compressed;
> +
> +	if (!HAS_FLATCCS(devid))
> +		return buf_is_aux_compressed(bops, buf);
> +
> +	vm = xe_vm_create(xe, 0, 0);
> +	exec_queue = xe_exec_queue_create(xe, vm, &inst, 0);
> +	ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0);
> +	ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
> +
> +	blt_set_object(&obj, buf->handle,
> +		       buf->size, buf->region, buf->mocs_index,
> +		       buf->pat_index, tiling,
> +		       buf->compression ? COMPRESSION_ENABLED : COMPRESSION_DISABLED,
> +		       COMPRESSION_TYPE_3D);
> +	blt_set_geom(&obj, buf->surface[0].stride, 0, 0, buf->width, buf->height, 0, 0);
> +
> +	is_compressed = blt_surface_is_compressed(xe, ctx, NULL, ahnd, &obj);
> +
> +	xe_exec_queue_destroy(xe, exec_queue);
> +	xe_vm_destroy(xe, vm);
> +	put_ahnd(ahnd);
> +	free(ctx);
> +
> +	return is_compressed;
> +}
> +
>   /*
>    *
>    * Scenarios implemented are presented below. We copy from linear to and forth
> @@ -176,6 +245,7 @@ enum render_copy_testtype {
>   	COPY_HSTRIPES,
>   	COPY_RANDOM,
>   	COPY_FULL,
> +	COPY_FULL_COMPRESSED,
>   };
>   
>   static const char * const testname[] = {
> @@ -184,6 +254,7 @@ static const char * const testname[] = {
>   	[COPY_HSTRIPES]	= "hstripes",
>   	[COPY_RANDOM]	= "random",
>   	[COPY_FULL]	= "full",
> +	[COPY_FULL_COMPRESSED] = "full-compressed",
>   };
>   
>   static int render(struct buf_ops *bops, uint32_t tiling,
> @@ -196,6 +267,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
>   	uint32_t fails = 0;
>   	uint32_t devid = intel_get_drm_devid(xe);
>   	igt_render_copyfunc_t render_copy = NULL;
> +	int compression = testtype == COPY_FULL_COMPRESSED ? I915_COMPRESSION_RENDER :
> +							     I915_COMPRESSION_NONE;
> +	bool is_compressed;
>   	struct posrc {
>   		uint32_t x0, y0;
>   		uint32_t x1, y1;
> @@ -241,7 +315,7 @@ static int render(struct buf_ops *bops, uint32_t tiling,
>   	scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
>   			 I915_COMPRESSION_NONE);
>   	scratch_buf_init(bops, &dst, width, height, tiling,
> -			 I915_COMPRESSION_NONE);
> +			 compression);
>   	scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
>   			 I915_COMPRESSION_NONE);
>   	scratch_buf_init(bops, &grfs, 64, height * 4, I915_TILING_NONE,
> @@ -317,6 +391,7 @@ static int render(struct buf_ops *bops, uint32_t tiling,
>   
>   
>   	case COPY_FULL:
> +	case COPY_FULL_COMPRESSED:
>   		render_copy(ibb,
>   			    &src, 0, 0, width, height,
>   			    &dst, 0, 0);
> @@ -339,7 +414,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
>   					   tiling, width, height);
>   	}
>   
> -	fails = compare_bufs(&src, &final, true);
> +	fails = compare_bufs(&src, &final, false);
> +	if (compression == I915_COMPRESSION_RENDER)
> +		is_compressed = buf_is_compressed(bops, &dst);
>   
>   	intel_buf_close(bops, &src);
>   	intel_buf_close(bops, &dst);
> @@ -347,6 +424,9 @@ static int render(struct buf_ops *bops, uint32_t tiling,
>   
>   	igt_assert_f(fails == 0, "%s: (tiling: %d) fails: %d\n",
>   		     __func__, tiling, fails);
> +	if (compression == I915_COMPRESSION_RENDER && blt_platform_has_flat_ccs_enabled(xe))
> +		igt_assert_f(is_compressed, "%s: (tiling: %d) buffer is not compressed\n",
> +			     __func__, tiling);
>   
>   	return fails;
>   }
> @@ -398,12 +478,13 @@ igt_main_args("dpiW:H:", NULL, help_str, opt_handler, NULL)
>   		srand(time(NULL));
>   	}
>   
> -	for (int id = 0; id <= COPY_FULL; id++) {
> +	for (int id = 0; id <= COPY_FULL_COMPRESSED; id++) {
>   		igt_subtest_with_dynamic_f("render-%s", testname[id]) {
>   			igt_require(xe_has_engine_class(xe, DRM_XE_ENGINE_CLASS_RENDER));
>   
>   			for_each_tiling(tiling) {
> -				if (!blt_block_copy_supports_tiling(xe, tiling))
> +				if (!render_supports_tiling(xe, tiling,
> +							    id == COPY_FULL_COMPRESSED))
>   					continue;
>   
>   				tiling_name = blt_tiling_name(tiling);

[PATCH i-g-t v5 11/11] tests/xe_intel_bb: Use supported tilings instead hardcoded ones

[Zbigniew Kempczyński]

Use introduced render tilings in cmds-info to select appropriate one
on which render subtest is executed.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_intel_bb.c | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
index 09164c41fc..ad6a2d22ca 100644
--- a/tests/intel/xe_intel_bb.c
+++ b/tests/intel/xe_intel_bb.c
@@ -18,6 +18,7 @@
 
 #include "igt.h"
 #include "igt_crc.h"
+#include "intel_blt.h"
 #include "intel_bufops.h"
 #include "intel_mocs.h"
 #include "intel_pat.h"
@@ -978,19 +979,10 @@ const char *help_str =
 
 igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
 {
-	int xe, i;
+	int xe;
 	struct buf_ops *bops;
 	uint32_t width;
 
-	struct test {
-		uint32_t tiling;
-		const char *tiling_name;
-	} tests[] = {
-		{ I915_TILING_NONE, "none" },
-		{ I915_TILING_X, "x" },
-		{ I915_TILING_4, "4" },
-	};
-
 	igt_fixture {
 		xe = drm_open_driver(DRIVER_XE);
 		bops = buf_ops_create(xe);
@@ -1053,14 +1045,19 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
 		delta_check(bops);
 
 	igt_subtest_with_dynamic("render") {
+		int tiling;
+
 		igt_require(xe_has_engine_class(xe, DRM_XE_ENGINE_CLASS_RENDER));
 
-		for (i = 0; i < ARRAY_SIZE(tests); i++) {
-			const struct test *t = &tests[i];
+		for_each_tiling(tiling) {
+			if (!render_supports_tiling(xe, tiling, false))
+				continue;
 
 			for (width = 512; width <= 1024; width += 512)
-				igt_dynamic_f("render-%s-%u", t->tiling_name, width)
-					render(bops, t->tiling, width, width);
+				igt_dynamic_f("render-%s-%u",
+					      blt_tiling_name(tiling), width)
+					render(bops, blt_tile_to_i915_tile(tiling),
+					       width, width);
 		}
 	}
 
-- 
2.34.1

Re: [PATCH i-g-t v5 11/11] tests/xe_intel_bb: Use supported tilings instead hardcoded ones

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 9.5.2024 8.33, Zbigniew Kempczyński wrote:
> Use introduced render tilings in cmds-info to select appropriate one
> on which render subtest is executed.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>   tests/intel/xe_intel_bb.c | 25 +++++++++++--------------
>   1 file changed, 11 insertions(+), 14 deletions(-)
> 
> diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
> index 09164c41fc..ad6a2d22ca 100644
> --- a/tests/intel/xe_intel_bb.c
> +++ b/tests/intel/xe_intel_bb.c
> @@ -18,6 +18,7 @@
>   
>   #include "igt.h"
>   #include "igt_crc.h"
> +#include "intel_blt.h"
>   #include "intel_bufops.h"
>   #include "intel_mocs.h"
>   #include "intel_pat.h"
> @@ -978,19 +979,10 @@ const char *help_str =
>   
>   igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
>   {
> -	int xe, i;
> +	int xe;
>   	struct buf_ops *bops;
>   	uint32_t width;
>   
> -	struct test {
> -		uint32_t tiling;
> -		const char *tiling_name;
> -	} tests[] = {
> -		{ I915_TILING_NONE, "none" },
> -		{ I915_TILING_X, "x" },
> -		{ I915_TILING_4, "4" },
> -	};
> -
>   	igt_fixture {
>   		xe = drm_open_driver(DRIVER_XE);
>   		bops = buf_ops_create(xe);
> @@ -1053,14 +1045,19 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
>   		delta_check(bops);
>   
>   	igt_subtest_with_dynamic("render") {
> +		int tiling;
> +
>   		igt_require(xe_has_engine_class(xe, DRM_XE_ENGINE_CLASS_RENDER));
>   
> -		for (i = 0; i < ARRAY_SIZE(tests); i++) {
> -			const struct test *t = &tests[i];
> +		for_each_tiling(tiling) {
> +			if (!render_supports_tiling(xe, tiling, false))
> +				continue;
>   
>   			for (width = 512; width <= 1024; width += 512)
> -				igt_dynamic_f("render-%s-%u", t->tiling_name, width)
> -					render(bops, t->tiling, width, width);
> +				igt_dynamic_f("render-%s-%u",
> +					      blt_tiling_name(tiling), width)
> +					render(bops, blt_tile_to_i915_tile(tiling),
> +					       width, width);
>   		}
>   	}
>   

✓ CI.xeBAT: success for Add render-copy compression on Xe+ (rev5)

[Patchwork]

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== Series Details ==

Series: Add render-copy compression on Xe+ (rev5)
URL   : https://patchwork.freedesktop.org/series/132902/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7843_BAT -> XEIGTPW_11117_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 5)
------------------------------

  Additional (1): bat-lnl-1 

New tests
---------

  New tests have been introduced between XEIGT_7843_BAT and XEIGTPW_11117_BAT:

### New IGT tests (8) ###

  * igt@xe_intel_bb@render@render-linear-1024:
    - Statuses : 4 pass(s)
    - Exec time: [0.04, 0.10] s

  * igt@xe_intel_bb@render@render-linear-512:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@xe_intel_bb@render@render-tile4-1024:
    - Statuses : 4 pass(s)
    - Exec time: [0.04, 0.10] s

  * igt@xe_intel_bb@render@render-tile4-512:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@xe_intel_bb@render@render-tile64-1024:
    - Statuses : 3 pass(s)
    - Exec time: [0.05, 0.10] s

  * igt@xe_intel_bb@render@render-tile64-512:
    - Statuses : 3 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@xe_intel_bb@render@render-xmajor-1024:
    - Statuses : 4 pass(s)
    - Exec time: [0.04, 0.10] s

  * igt@xe_intel_bb@render@render-xmajor-512:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.02] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11117_BAT that come from known issues:

### IGT changes ###

  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1442
  [Intel XE#1446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1446
  [Intel XE#1462]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1462
  [Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_7843 -> IGTPW_11117
  * Linux: xe-1257-34d52122a69076639d526b035c8edd5b43201f84 -> xe-1263-92f877dd46245e4a44b6d24b5e303b8c03c40c75

  IGTPW_11117: 11117
  IGT_7843: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1257-34d52122a69076639d526b035c8edd5b43201f84: 34d52122a69076639d526b035c8edd5b43201f84
  xe-1263-92f877dd46245e4a44b6d24b5e303b8c03c40c75: 92f877dd46245e4a44b6d24b5e303b8c03c40c75

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/index.html

[-- Attachment #2: Type: text/html, Size: 3094 bytes --]

✗ Fi.CI.BAT: failure for Add render-copy compression on Xe+ (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 19359 bytes --]

== Series Details ==

Series: Add render-copy compression on Xe+ (rev5)
URL   : https://patchwork.freedesktop.org/series/132902/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14737 -> IGTPW_11117
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_11117 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_11117, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/index.html

Participating hosts (42 -> 41)
------------------------------

  Additional (3): fi-glk-j4005 bat-dg2-11 bat-mtlp-6 
  Missing    (4): fi-kbl-8809g fi-cfl-8109u fi-snb-2520m bat-adlp-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_11117:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests:
    - bat-jsl-3:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-jsl-3/igt@dmabuf@all-tests.html

  
Known issues
------------

  Here are the changes found in IGTPW_11117 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-arls-3:         NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@debugfs_test@basic-hwmon.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@info:
    - bat-mtlp-6:         NOTRUN -> [SKIP][4] ([i915#1849] / [i915#2582])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@fbdev@info.html

  * igt@fbdev@write:
    - bat-mtlp-6:         NOTRUN -> [SKIP][5] ([i915#2582]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@fbdev@write.html

  * igt@gem_huc_copy@huc-copy:
    - fi-glk-j4005:       NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-arls-3:         NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html
    - fi-glk-j4005:       NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/fi-glk-j4005/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-6:         NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@gem_mmap@basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][11] ([i915#4083])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@gem_mmap@basic.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][12] ([i915#4083])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@gem_render_tiled_blits@basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / [i915#4079])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-arls-3:         NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@gem_tiled_blits@basic.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][17] ([i915#4077]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][18] ([i915#4079]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@gem_tiled_pread_basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-11:         NOTRUN -> [SKIP][20] ([i915#6621])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@i915_pm_rps@basic-api.html
    - bat-arls-3:         NOTRUN -> [SKIP][21] ([i915#10209])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@i915_pm_rps@basic-api.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][22] ([i915#6621])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][23] ([i915#4212] / [i915#9792]) +8 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg2-11:         NOTRUN -> [SKIP][24] ([i915#4212]) +7 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][25] ([i915#5190] / [i915#9792])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-11:         NOTRUN -> [SKIP][26] ([i915#5190])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-arls-3:         NOTRUN -> [SKIP][27] ([i915#10200]) +9 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-11:         NOTRUN -> [SKIP][28] ([i915#4215] / [i915#5190])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-dg2-11:         NOTRUN -> [SKIP][29] ([i915#4103] / [i915#4213]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - bat-arls-3:         NOTRUN -> [SKIP][30] ([i915#10202]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-mtlp-6:         NOTRUN -> [SKIP][31] ([i915#9792]) +17 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg2-11:         NOTRUN -> [SKIP][32] ([i915#3555] / [i915#3840])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_dsc@dsc-basic.html
    - bat-arls-3:         NOTRUN -> [SKIP][33] ([i915#9886])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_dsc@dsc-basic.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-mtlp-6:         NOTRUN -> [SKIP][34] ([i915#3637] / [i915#9792]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-arls-3:         NOTRUN -> [SKIP][35] ([i915#10207])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg2-11:         NOTRUN -> [SKIP][36]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-6:         NOTRUN -> [SKIP][37] ([i915#5274] / [i915#9792])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
    - bat-dg2-11:         NOTRUN -> [SKIP][38] ([i915#5274])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-mtlp-6:         NOTRUN -> [SKIP][39] ([i915#4342] / [i915#5354] / [i915#9792])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][40] ([i915#9197]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg2-11:         NOTRUN -> [SKIP][41] ([i915#5354])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html
    - bat-arls-3:         NOTRUN -> [SKIP][42] ([i915#9812])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][43] ([i915#5354] / [i915#9792])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-cursor-plane-move:
    - bat-mtlp-6:         NOTRUN -> [SKIP][44] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-arls-3:         NOTRUN -> [SKIP][45] ([i915#9732]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_psr@psr-primary-page-flip:
    - fi-glk-j4005:       NOTRUN -> [SKIP][46] +10 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - bat-dg2-11:         NOTRUN -> [SKIP][47] ([i915#1072] / [i915#9732]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-6:         NOTRUN -> [SKIP][48] ([i915#3555] / [i915#8809] / [i915#9792])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg2-11:         NOTRUN -> [SKIP][49] ([i915#3555])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-arls-3:         NOTRUN -> [SKIP][50] ([i915#10208] / [i915#8809])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-11:         NOTRUN -> [SKIP][51] ([i915#3708])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html
    - bat-mtlp-6:         NOTRUN -> [SKIP][52] ([i915#3708] / [i915#9792])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-6:         NOTRUN -> [SKIP][53] ([i915#3708] / [i915#4077]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-arls-3:         NOTRUN -> [SKIP][54] ([i915#10212] / [i915#3708])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg2-11:         NOTRUN -> [SKIP][55] ([i915#3708] / [i915#4077]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@prime_vgem@basic-gtt.html
    - bat-arls-3:         NOTRUN -> [SKIP][56] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - bat-mtlp-6:         NOTRUN -> [SKIP][57] ([i915#3708]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@prime_vgem@basic-read.html
    - bat-arls-3:         NOTRUN -> [SKIP][58] ([i915#10214] / [i915#3708])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-mtlp-6:         NOTRUN -> [SKIP][59] ([i915#10216] / [i915#3708])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-6/igt@prime_vgem@basic-write.html
    - bat-dg2-11:         NOTRUN -> [SKIP][60] ([i915#3291] / [i915#3708]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-11/igt@prime_vgem@basic-write.html
    - bat-arls-3:         NOTRUN -> [SKIP][61] ([i915#10216] / [i915#3708])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-dg2-8:          [FAIL][62] ([i915#10378]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14737/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@i915_module_load@load:
    - bat-arls-3:         [ABORT][64] ([i915#11041]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14737/bat-arls-3/igt@i915_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-arls-3/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@module-reload:
    - {bat-mtlp-9}:       [CRASH][66] ([i915#10911]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14737/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
  [i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
  [i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
  [i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
  [i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
  [i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
  [i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
  [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
  [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
  [i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7843 -> IGTPW_11117

  CI-20190529: 20190529
  CI_DRM_14737: 92f877dd46245e4a44b6d24b5e303b8c03c40c75 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_11117: 11117
  IGT_7843: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/index.html

[-- Attachment #2: Type: text/html, Size: 24531 bytes --]

Re: ✗ Fi.CI.BAT: failure for Add render-copy compression on Xe+ (rev5)

[Zbigniew Kempczyński]

On Thu, May 09, 2024 at 07:43:57AM +0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  Add render-copy compression on Xe+ (rev5)                       
>    URL:     https://patchwork.freedesktop.org/series/132902/                
>    State:   failure                                                         
>    Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/index.html 
> 
>              CI Bug Log - changes from CI_DRM_14737 -> IGTPW_11117
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with IGTPW_11117 absolutely need to be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in IGTPW_11117, please notify your bug team
>    ('I915-ci-infra@lists.freedesktop.org') to allow them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
>    External URL:
>    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11117/index.html
> 
> Participating hosts (42 -> 41)
> 
>    Additional (3): fi-glk-j4005 bat-dg2-11 bat-mtlp-6
>    Missing (4): fi-kbl-8809g fi-cfl-8109u fi-snb-2520m bat-adlp-6
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in IGTPW_11117:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@dmabuf@all-tests:
>           * bat-jsl-3: NOTRUN -> INCOMPLETE

Unrelated to the change.

--
Zbigniew

> 
> Known issues
> 
>    Here are the changes found in IGTPW_11117 that come from known issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@debugfs_test@basic-hwmon:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#9318)
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#9318)
>      * igt@fbdev@info:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#1849 / i915#2582)
>      * igt@fbdev@write:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#2582) +3 other tests skip
>      * igt@gem_huc_copy@huc-copy:
> 
>           * fi-glk-j4005: NOTRUN -> SKIP (i915#2190)
>      * igt@gem_lmem_swapping@parallel-random-engines:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#10213) +3 other tests skip
>           * fi-glk-j4005: NOTRUN -> SKIP (i915#4613) +3 other tests skip
>      * igt@gem_lmem_swapping@verify-random:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4613) +3 other tests skip
>      * igt@gem_mmap@basic:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4083)
>           * bat-arls-3: NOTRUN -> SKIP (i915#4083)
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4083)
>      * igt@gem_render_tiled_blits@basic:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4079) +1 other test skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10197 / i915#10211 / i915#4079)
>      * igt@gem_tiled_blits@basic:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#10196 / i915#4077) +2 other
>             tests skip
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4077) +2 other tests skip
>      * igt@gem_tiled_fence_blits@basic:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4077) +2 other tests skip
>      * igt@gem_tiled_pread_basic:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4079) +1 other test skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10206 / i915#4079)
>      * igt@i915_pm_rps@basic-api:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#6621)
>           * bat-arls-3: NOTRUN -> SKIP (i915#10209)
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#6621)
>      * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4212 / i915#9792) +8 other tests
>             skip
>      * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4212) +7 other tests skip
>      * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#5190 / i915#9792)
>           * bat-dg2-11: NOTRUN -> SKIP (i915#5190)
>      * igt@kms_addfb_basic@basic-y-tiled-legacy:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#10200) +9 other tests skip
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4215 / i915#5190)
>      * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#4103 / i915#4213) +1 other test
>             skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10202) +1 other test skip
>      * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#9792) +17 other tests skip
>      * igt@kms_dsc@dsc-basic:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#3555 / i915#3840)
>           * bat-arls-3: NOTRUN -> SKIP (i915#9886)
>      * igt@kms_flip@basic-flip-vs-dpms:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#3637 / i915#9792) +3 other tests
>             skip
>      * igt@kms_force_connector_basic@force-load-detect:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#10207)
>           * bat-dg2-11: NOTRUN -> SKIP
>      * igt@kms_force_connector_basic@prune-stale-modes:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#5274 / i915#9792)
>           * bat-dg2-11: NOTRUN -> SKIP (i915#5274)
>      * igt@kms_frontbuffer_tracking@basic:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#4342 / i915#5354 / i915#9792)
>      * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#9197) +3 other tests skip
>      * igt@kms_pm_backlight@basic-brightness:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#5354)
>           * bat-arls-3: NOTRUN -> SKIP (i915#9812)
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#5354 / i915#9792)
>      * igt@kms_psr@psr-cursor-plane-move:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#1072 / i915#9673 / i915#9732 /
>             i915#9792) +3 other tests skip
>      * igt@kms_psr@psr-primary-mmap-gtt:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#9732) +3 other tests skip
>      * igt@kms_psr@psr-primary-page-flip:
> 
>           * fi-glk-j4005: NOTRUN -> SKIP +10 other tests skip
>      * igt@kms_psr@psr-sprite-plane-onoff:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#1072 / i915#9732) +3 other tests
>             skip
>      * igt@kms_setmode@basic-clone-single-crtc:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#3555 / i915#8809 / i915#9792)
>           * bat-dg2-11: NOTRUN -> SKIP (i915#3555)
>           * bat-arls-3: NOTRUN -> SKIP (i915#10208 / i915#8809)
>      * igt@prime_vgem@basic-fence-flip:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#3708)
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#3708 / i915#9792)
>      * igt@prime_vgem@basic-fence-mmap:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#3708 / i915#4077) +1 other test
>             skip
>      * igt@prime_vgem@basic-fence-read:
> 
>           * bat-arls-3: NOTRUN -> SKIP (i915#10212 / i915#3708)
>      * igt@prime_vgem@basic-gtt:
> 
>           * bat-dg2-11: NOTRUN -> SKIP (i915#3708 / i915#4077) +1 other test
>             skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10196 / i915#3708 / i915#4077)
>             +1 other test skip
>      * igt@prime_vgem@basic-read:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#3708) +1 other test skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10214 / i915#3708)
>      * igt@prime_vgem@basic-write:
> 
>           * bat-mtlp-6: NOTRUN -> SKIP (i915#10216 / i915#3708)
>           * bat-dg2-11: NOTRUN -> SKIP (i915#3291 / i915#3708) +2 other tests
>             skip
>           * bat-arls-3: NOTRUN -> SKIP (i915#10216 / i915#3708)
> 
>     Possible fixes
> 
>      * igt@gem_lmem_swapping@basic@lmem0:
> 
>           * bat-dg2-8: FAIL (i915#10378) -> PASS
>      * igt@i915_module_load@load:
> 
>           * bat-arls-3: ABORT (i915#11041) -> PASS
>      * igt@i915_pm_rpm@module-reload:
> 
>           * {bat-mtlp-9}: CRASH (i915#10911) -> PASS
> 
>    {name}: This element is suppressed. This means it is ignored when
>    computing
>    the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
> Build changes
> 
>      * CI: CI-20190529 -> None
>      * IGT: IGT_7843 -> IGTPW_11117
> 
>    CI-20190529: 20190529
>    CI_DRM_14737: 92f877dd46245e4a44b6d24b5e303b8c03c40c75 @
>    git://anongit.freedesktop.org/gfx-ci/linux
>    IGTPW_11117: 11117
>    IGT_7843: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56 @
>    https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

✗ CI.xeFULL: failure for Add render-copy compression on Xe+ (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38095 bytes --]

== Series Details ==

Series: Add render-copy compression on Xe+ (rev5)
URL   : https://patchwork.freedesktop.org/series/132902/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_7843_full -> XEIGTPW_11117_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_11117_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_11117_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 1)
------------------------------

  ERROR: It appears as if the changes made in XEIGTPW_11117_full prevented too many machines from booting.

  Missing    (2): shard-adlp shard-lnl 

New tests
---------

  New tests have been introduced between XEIGT_7843_full and XEIGTPW_11117_full:

### New IGT tests (11) ###

  * igt@xe_intel_bb@render@render-linear-1024:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@xe_intel_bb@render@render-linear-512:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@xe_intel_bb@render@render-tile4-1024:
    - Statuses : 1 pass(s)
    - Exec time: [0.07] s

  * igt@xe_intel_bb@render@render-tile4-512:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@xe_intel_bb@render@render-tile64-1024:
    - Statuses : 1 pass(s)
    - Exec time: [0.08] s

  * igt@xe_intel_bb@render@render-tile64-512:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_intel_bb@render@render-xmajor-1024:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@xe_intel_bb@render@render-xmajor-512:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_render_copy@render-full-compressed:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_render_copy@render-full-compressed@render-tile4-256x256:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@xe_render_copy@render-full-compressed@render-tile64-256x256:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_11117_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][1] ([Intel XE#1201] / [Intel XE#801]) +15 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-6-4-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [FAIL][2] ([Intel XE#650]) +11 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-6-4-mc-ccs.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg2-set2:     [PASS][3] -> [SKIP][4] ([Intel XE#1201] / [Intel XE#829]) +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#1201] / [Intel XE#1252])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-7:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#1201] / [Intel XE#787]) +69 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-7.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-7:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +19 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-7.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#1201] / [Intel XE#306])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1201] / [Intel XE#373]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][12] ([Intel XE#1178])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-dg2-set2:     [PASS][13] -> [DMESG-WARN][14] ([Intel XE#1214] / [Intel XE#282]) +4 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-433/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][15] ([Intel XE#1214] / [Intel XE#282])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][16] -> [SKIP][17] ([Intel XE#1201] / [Intel XE#1234]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [PASS][18] -> [INCOMPLETE][19] ([Intel XE#1195])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#1201] / [Intel XE#651]) +5 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#1201] / [Intel XE#653]) +5 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_lease@lease-invalid-crtc:
    - shard-dg2-set2:     [PASS][22] -> [SKIP][23] ([Intel XE#1201]) +8 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-464/igt@kms_lease@lease-invalid-crtc.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_lease@lease-invalid-crtc.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][24] ([Intel XE#616]) +3 other tests fail
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#1201] / [Intel XE#498]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-6.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-d-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#1201] / [Intel XE#305]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-6.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#1201] / [Intel XE#455]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-6.html

  * igt@kms_prop_blob@blob-prop-core:
    - shard-dg2-set2:     [PASS][29] -> [SKIP][30] ([Intel XE#1201] / [Intel XE#780])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@kms_prop_blob@blob-prop-core.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_prop_blob@blob-prop-core.html

  * igt@kms_psr@fbc-psr-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#929]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_psr@fbc-psr-sprite-plane-onoff.html

  * igt@kms_rmfb@close-fd@pipe-b-hdmi-a-7:
    - shard-dg2-set2:     NOTRUN -> [FAIL][32] ([Intel XE#294])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_rmfb@close-fd@pipe-b-hdmi-a-7.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][34] ([Intel XE#1127] / [Intel XE#1201])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-dg2-set2:     NOTRUN -> [FAIL][35] ([Intel XE#771] / [Intel XE#899])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][36] ([Intel XE#899])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-6.html

  * igt@xe_copy_basic@mem-set-linear-0xfd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#1126] / [Intel XE#1201])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfd.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-dg2-set2:     [PASS][38] -> [FAIL][39] ([Intel XE#1600])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-466/igt@xe_evict@evict-large-multi-vm-cm.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_exec_fault_mode@once-invalid-userptr-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#1201] / [Intel XE#288]) +7 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html

  * igt@xe_gt_freq@freq_low_max:
    - shard-dg2-set2:     [PASS][41] -> [FAIL][42] ([Intel XE#1045] / [Intel XE#1204])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@xe_gt_freq@freq_low_max.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@xe_gt_freq@freq_low_max.html

  * igt@xe_live_ktest@xe_migrate:
    - shard-dg2-set2:     [PASS][43] -> [SKIP][44] ([Intel XE#1192] / [Intel XE#1201])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-464/igt@xe_live_ktest@xe_migrate.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@xe_live_ktest@xe_migrate.html

  * igt@xe_pm@s3-basic-exec:
    - shard-dg2-set2:     [PASS][45] -> [DMESG-WARN][46] ([Intel XE#1162] / [Intel XE#1214]) +1 other test dmesg-warn
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@xe_pm@s3-basic-exec.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@xe_pm@s3-basic-exec.html

  
#### Possible fixes ####

  * igt@kms_atomic_interruptible@legacy-setmode:
    - shard-dg2-set2:     [SKIP][47] ([Intel XE#1201] / [Intel XE#1234]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_atomic_interruptible@legacy-setmode.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_atomic_interruptible@legacy-setmode.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][49] ([Intel XE#1201] / [Intel XE#829]) -> [PASS][50] +3 other tests pass
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_color@ctm-0-75:
    - shard-dg2-set2:     [SKIP][51] ([Intel XE#1201]) -> [PASS][52] +17 other tests pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_color@ctm-0-75.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_color@ctm-0-75.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-dg2-set2:     [DMESG-WARN][53] ([Intel XE#1214] / [Intel XE#282]) -> [PASS][54] +4 other tests pass
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-435/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a6:
    - shard-dg2-set2:     [DMESG-WARN][55] ([Intel XE#1162] / [Intel XE#1214]) -> [PASS][56] +5 other tests pass
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-464/igt@kms_flip@flip-vs-suspend@c-hdmi-a6.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@kms_flip@flip-vs-suspend@c-hdmi-a6.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-dg2-set2:     [INCOMPLETE][57] ([Intel XE#1195]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][59] ([Intel XE#1600]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-466/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_evict@evict-threads-large:
    - shard-dg2-set2:     [TIMEOUT][61] ([Intel XE#1473] / [Intel XE#392]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@xe_evict@evict-threads-large.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@xe_evict@evict-threads-large.html

  * igt@xe_module_load@many-reload:
    - shard-dg2-set2:     [DMESG-WARN][63] ([Intel XE#1214]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@xe_module_load@many-reload.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@xe_module_load@many-reload.html

  
#### Warnings ####

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-dg2-set2:     [DMESG-FAIL][65] ([Intel XE#1162] / [Intel XE#1345] / [Intel XE#1548]) -> [DMESG-FAIL][66] ([Intel XE#1345] / [Intel XE#1548])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@core_hotunplug@hotunplug-rescan.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@core_hotunplug@hotunplug-rescan.html

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - shard-dg2-set2:     [SKIP][67] ([Intel XE#1201]) -> [FAIL][68] ([Intel XE#650])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][69] ([Intel XE#1201] / [Intel XE#829]) -> [SKIP][70] ([Intel XE#1124] / [Intel XE#1201]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][71] ([Intel XE#1201] / [Intel XE#607]) -> [SKIP][72] ([Intel XE#1201] / [Intel XE#829])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-dg2-set2:     [SKIP][73] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][74] ([Intel XE#1201] / [Intel XE#829])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-dg2-set2:     [SKIP][75] ([Intel XE#1201]) -> [SKIP][76] ([Intel XE#1201] / [Intel XE#346])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_big_joiner@invalid-modeset.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-dg2-set2:     [SKIP][77] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][78] ([Intel XE#1201])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-435/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][79] ([Intel XE#1201] / [Intel XE#829]) -> [SKIP][80] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
    - shard-dg2-set2:     [SKIP][81] ([Intel XE#1201] / [Intel XE#829]) -> [SKIP][82] ([Intel XE#1201] / [Intel XE#1252])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][83] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][84] ([Intel XE#1201] / [Intel XE#829])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color@gamma:
    - shard-dg2-set2:     [SKIP][85] ([Intel XE#1201]) -> [SKIP][86] ([Intel XE#1201] / [Intel XE#306])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_chamelium_color@gamma.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@hdmi-mode-timings:
    - shard-dg2-set2:     [SKIP][87] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][88] ([Intel XE#1201]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-435/igt@kms_chamelium_edid@hdmi-mode-timings.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_chamelium_edid@hdmi-mode-timings.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2-set2:     [SKIP][89] ([Intel XE#1201]) -> [SKIP][90] ([Intel XE#1201] / [Intel XE#373])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@srm:
    - shard-dg2-set2:     [SKIP][91] ([Intel XE#1201] / [Intel XE#455]) -> [FAIL][92] ([Intel XE#1178])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-464/igt@kms_content_protection@srm.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-dg2-set2:     [FAIL][93] ([Intel XE#1188]) -> [SKIP][94] ([Intel XE#1201] / [Intel XE#455])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-435/igt@kms_content_protection@uevent.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg2-set2:     [SKIP][95] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][96] ([Intel XE#1201])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-464/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [FAIL][97] ([Intel XE#616]) -> [DMESG-FAIL][98] ([Intel XE#1162])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-6.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-dg2-set2:     [DMESG-WARN][99] ([Intel XE#1214] / [Intel XE#282] / [Intel XE#910]) -> [DMESG-WARN][100] ([Intel XE#1214] / [Intel XE#282]) +1 other test dmesg-warn
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-dg2-set2:     [DMESG-WARN][101] ([Intel XE#1214] / [Intel XE#282]) -> [SKIP][102] ([Intel XE#1201])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-dg2-set2:     [SKIP][103] ([Intel XE#1201]) -> [DMESG-WARN][104] ([Intel XE#1214] / [Intel XE#282])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-dg2-set2:     [SKIP][105] ([Intel XE#1201]) -> [SKIP][106] ([Intel XE#1201] / [Intel XE#455])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     [SKIP][107] ([Intel XE#1201]) -> [SKIP][108] ([Intel XE#1201] / [Intel XE#701])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_feature_discovery@chamelium.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-dg2-set2:     [SKIP][109] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][110] ([Intel XE#1201]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-dg2-set2:     [FAIL][111] ([Intel XE#650]) -> [SKIP][112] ([Intel XE#1201] / [Intel XE#829])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-466/igt@kms_flip_tiling@flip-change-tiling.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][113] ([Intel XE#1201] / [Intel XE#1234]) -> [SKIP][114] ([Intel XE#1201] / [Intel XE#651])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     [SKIP][115] ([Intel XE#1201]) -> [SKIP][116] ([Intel XE#1201] / [Intel XE#651]) +5 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-dg2-set2:     [SKIP][117] ([Intel XE#1201]) -> [SKIP][118] ([Intel XE#1201] / [Intel XE#653]) +5 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2-set2:     [SKIP][119] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][120] ([Intel XE#1201]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-dg2-set2:     [DMESG-FAIL][121] ([Intel XE#1162]) -> [FAIL][122] ([Intel XE#616]) +2 other tests fail
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-set2:     [SKIP][123] ([Intel XE#1201]) -> [SKIP][124] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format:
    - shard-dg2-set2:     [INCOMPLETE][125] ([Intel XE#1195] / [Intel XE#904] / [Intel XE#909]) -> [TIMEOUT][126] ([Intel XE#380] / [Intel XE#904] / [Intel XE#909])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][127] ([Intel XE#1195] / [Intel XE#904] / [Intel XE#909]) -> [TIMEOUT][128] ([Intel XE#904] / [Intel XE#909]) +1 other test timeout
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a-hdmi-a-6.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats:
    - shard-dg2-set2:     [INCOMPLETE][129] ([Intel XE#1195] / [Intel XE#909]) -> [TIMEOUT][130] ([Intel XE#295] / [Intel XE#380] / [Intel XE#909])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-463/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-435/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-dg2-set2:     [SKIP][131] ([Intel XE#1201]) -> [SKIP][132] ([Intel XE#1201] / [Intel XE#305] / [Intel XE#455])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     [SKIP][133] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][134] ([Intel XE#1201]) +2 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-436/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-434/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2-set2:     [SKIP][135] ([Intel XE#1201]) -> [SKIP][136] ([Intel XE#1201] / [Intel XE#929]) +4 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_psr@psr-cursor-render.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-464/igt@kms_psr@psr-cursor-render.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2-set2:     [SKIP][137] ([Intel XE#1201] / [Intel XE#829]) -> [SKIP][138] ([Intel XE#1201] / [Intel XE#327])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7843/shard-dg2-434/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11117/shard-dg2-466/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1045]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1045
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1162
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
  [Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
  [Intel XE#1214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1214
  [Intel XE#1234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1234
  [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
  [Intel XE#1345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1345
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1548
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#282]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/282
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/294
  [Intel XE#295]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/295
  [Intel XE#305]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/305
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/380
  [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/650
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
  [Intel XE#780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/780
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#801]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/801
  [Intel XE#829]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/829
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/904
  [Intel XE#909]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/909
  [Intel XE#910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/910
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929


Build changes
-------------

  * IGT: IGT_7843 -> IGTPW_11117
  * Linux: xe-1257-34d52122a69076639d526b035c8edd5b43201f84 -> xe-1263-92f877dd46245e4a44b6d24b5e303b8c03c40c75

  IGTPW_11117: 11117
  IGT_7843: 0df7b9b97f9da0e364f5ee30fe331004b8c86b56 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1257-34d52122a69076639d526b035c8edd5b43201f84: 34d52122a69076639d526b035c8edd5b43201f84
  xe-1263-92f877dd46245e4a44b6d24b5e303b8c03c40c75: 92f877dd46245e4a44b6d24b5e303b8c03c40c75

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-132902v5/index.html

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