[PATCH i-g-t v3 10/10] tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely accessing two memory locations with SVM

[Bommu Krishnaiah <krishnaiah.bommu@intel.com>]

svm-sparse-access verifies the functionality of sparsely accessing two memory locations using SVM

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 lib/xe/xe_util.c     | 18 ++++++++++++++++++
 lib/xe/xe_util.h     |  1 +
 tests/intel/xe_svm.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)

diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index c19cdae0c..217d3fa1b 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -146,6 +146,24 @@ void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val
 	*batch++ = MI_BATCH_BUFFER_END;
 }
 
+/**
+ * Insert commands to batch buffer to store values in two memory locations.
+ */
+void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val)
+{
+	int i = 0;
+
+	batch[i] = MI_STORE_DWORD_IMM;
+	batch[++i] = dst_va;
+	batch[++i] = dst_va >> 32;
+	batch[++i] = val;
+	batch[++i] = MI_STORE_DWORD_IMM;
+	batch[++i] = dst_va1;
+	batch[++i] = dst_va1 >> 32;
+	batch[++i] = val;
+	batch[++i] = MI_BATCH_BUFFER_END;
+}
+
 /**
  * Creates a command buffer, fills it with commands using the provided fill
  * function, and sets up the execution queue for submission.
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 50f2a4bc4..f463cca3b 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -46,6 +46,7 @@ uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
 void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val);
 void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val);
+void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val);
 void xe_submit_cmd(struct xe_buffer *cmdbuf);
 int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
 void xe_destroy_buffer(struct xe_buffer *buffer);
diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c
index 86c9e86b8..0bdc1cc1e 100644
--- a/tests/intel/xe_svm.c
+++ b/tests/intel/xe_svm.c
@@ -45,6 +45,9 @@
  *
  * SUBTEST: svm-mprotect
  * Description: verify SVM functionality while accessing read only memory
+ *
+ * SUBTEST: svm-sparse-access
+ * Description: verify Sparsely access two memory locations with svm
  */
 
 #include <fcntl.h>
@@ -380,6 +383,39 @@ static void svm_mprotect(int fd, uint32_t vm, struct drm_xe_engine_class_instanc
 	free(dst);
 }
 
+/**
+ *  Sparsely access two memory locations
+ */
+static void svm_sparse_access(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t gpu_va = 0x1a0000;
+	size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE);
+	uint32_t size = 1024*1024, sz_dw = size/4;
+	uint32_t *dst, *dst_to_access, *dst_to_access1;
+
+	struct xe_buffer cmd_buf = {
+			.fd = fd,
+			.gpu_addr = (void *)(uintptr_t)gpu_va,
+			.vm = vm,
+			.size = bo_size,
+			.placement = vram_if_possible(fd, eci->gt_id),
+			.flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+	};
+
+	dst = malloc(size);
+	dst_to_access = dst + (sz_dw>>1);
+	dst_to_access1 = dst + (sz_dw>>2);
+
+	xe_create_cmdbuf_fill_two_dw(&cmd_buf, insert_two_stores, (uint64_t)dst_to_access, (uint64_t)dst_to_access1, 0xc0ffee, eci);
+	xe_submit_cmd(&cmd_buf);
+
+	igt_assert_eq(*dst_to_access, 0xc0ffee);
+	igt_assert_eq(*dst_to_access1, 0xc0ffee);
+
+	xe_destroy_cmdbuf(&cmd_buf);
+	free(dst);
+}
+
 igt_main
 {
 	int fd;
@@ -428,6 +464,10 @@ igt_main
 		xe_for_each_engine(fd, hwe)
 			svm_mprotect(fd, vm, hwe);
 
+	igt_subtest_f("svm-sparse-access")
+		xe_for_each_engine(fd, hwe)
+			svm_sparse_access(fd, vm, hwe);
+
 	igt_fixture {
 		xe_vm_destroy(fd, vm);
 		drm_close_driver(fd);
-- 
2.25.1