From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>,
Oak Zeng <oak.zeng@intel.com>,
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Subject: [PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for buffer creation and command submission etc
Date: Fri, 17 May 2024 17:16:49 +0530 [thread overview]
Message-ID: <20240517114658.810283-2-krishnaiah.bommu@intel.com> (raw)
In-Reply-To: <20240517114658.810283-1-krishnaiah.bommu@intel.com>
Introduce helper functions for buffer creation, binding, command submission, and
destruction, applicable for SVM and other tests.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Oak Zeng <oak.zeng@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
lib/xe/xe_util.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_util.h | 33 +++++++++++
2 files changed, 184 insertions(+)
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 050162b5e..de848b8bc 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -10,6 +10,157 @@
#include "xe/xe_ioctl.h"
#include "xe/xe_query.h"
#include "xe/xe_util.h"
+#include "lib/svga/vm_basic_types.h"
+
+/**
+ * Submits a command buffer to the GPU, waits for its completion, and verifies
+ * the user fence value
+ */
+int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf)
+{
+ int64_t timeout = ONE_SEC;
+
+ struct drm_xe_sync sync[1] = {
+ { .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+ .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE,
+ .addr = xe_cmdbuf_exec_ufence_gpuva(cmdbuf),},
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ .exec_queue_id = cmdbuf->exec_queue,
+ .address = (uint64_t)cmdbuf->gpu_addr,
+ };
+
+ xe_exec(cmdbuf->fd, &exec);
+ return __xe_wait_ufence(cmdbuf->fd, xe_cmdbuf_exec_ufence_cpuva(cmdbuf),USER_FENCE_VALUE, cmdbuf->exec_queue, &timeout);
+}
+
+/**
+ * Wrapper function to submit a command buffer and assert its successful
+ * execution.
+ */
+void xe_submit_cmd(struct xe_buffer *cmdbuf)
+{
+ int64_t ret;
+
+ ret = __xe_submit_cmd(cmdbuf);
+ igt_assert_eq(ret, 0);
+}
+
+/**
+ * Creates a buffer, maps it to both CPU and GPU address spaces, and binds it
+ * to a virtual memory (VM) space.
+ */
+void xe_create_buffer(struct xe_buffer *buffer)
+{
+ struct drm_xe_sync sync[1] = {
+ { .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE },
+ };
+
+ buffer->bind_queue = xe_bind_exec_queue_create(buffer->fd, buffer->vm, 0);
+ buffer->bind_ufence = aligned_alloc(xe_get_default_alignment(buffer->fd), PAGE_ALIGN_UFENCE);
+ sync->addr = (uint64_t)buffer->bind_ufence;
+
+ if (!buffer->is_userptr) {
+ buffer->bo = xe_bo_create(buffer->fd, 0, buffer->size, buffer->placement, buffer->flag);
+ buffer->cpu_addr = xe_bo_map(buffer->fd, buffer->bo, buffer->size);
+ xe_vm_bind_async(buffer->fd, buffer->vm, buffer->bind_queue, buffer->bo, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+ } else {
+ buffer->cpu_addr = aligned_alloc(xe_get_default_alignment(buffer->fd), buffer->size);
+ xe_vm_bind_userptr_async(buffer->fd, buffer->vm, buffer->bind_queue, to_user_pointer(buffer->cpu_addr), (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+ }
+
+ xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
+}
+
+/**
+ * Destroys a buffer created by xe_create_buffer and releases associated
+ * resources.
+ */
+void xe_destroy_buffer(struct xe_buffer *buffer)
+{
+ struct drm_xe_sync sync[1] = {
+ { .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE },
+ };
+ sync->addr = (uint64_t)buffer->bind_ufence;
+
+ xe_vm_unbind_async(buffer->fd, buffer->vm, buffer->bind_queue, 0, (uint64_t)buffer->gpu_addr, buffer->size, sync, 1);
+ xe_wait_ufence(buffer->fd, (uint64_t *)buffer->bind_ufence, USER_FENCE_VALUE, buffer->bind_queue, ONE_SEC);
+
+ munmap(buffer->cpu_addr, buffer->size);
+ if (!buffer->is_userptr)
+ gem_close(buffer->fd, buffer->bo);
+ else
+ free(buffer->cpu_addr);
+
+ free(buffer->bind_ufence);
+ xe_exec_queue_destroy(buffer->fd, buffer->bind_queue);
+}
+
+/**
+ * Inserts a MI_STORE_DWORD_IMM_GEN4 command into a batch buffer, which stores
+ * an immediate value to a given destination virtual address.
+ * */
+void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val)
+{
+ int i = 0;
+
+ batch[i] = MI_STORE_DWORD_IMM_GEN4;
+ batch[++i] = dst_va;
+ batch[++i] = dst_va >> 32;
+ batch[++i] = val;
+ batch[++i] = MI_BATCH_BUFFER_END;
+}
+
+/**
+ * Creates a command buffer, fills it with commands using the provided fill
+ * function, and sets up the execution queue for submission.
+ */
+void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func, uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci)
+{
+ //make some room for a exec_ufence, which will be used to sync the
+ //submission of this command....
+
+ cmd_buf->size = xe_bb_size(cmd_buf->fd, cmd_buf->size + PAGE_ALIGN_UFENCE);
+ xe_create_buffer(cmd_buf);
+ cmd_buf->exec_queue = xe_exec_queue_create(cmd_buf->fd, cmd_buf->vm, eci, 0);
+ fill_func(cmd_buf->cpu_addr, dst_va, val);
+}
+
+/**
+ * Destroys a command buffer created by xe_create_cmdbuf and releases
+ * associated resources.
+ */
+void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf)
+{
+ xe_exec_queue_destroy(cmd_buf->fd, cmd_buf->exec_queue);
+ xe_destroy_buffer(cmd_buf);
+}
+
+/**
+ * Returns the GPU virtual address of the execution user fence located at the
+ * end of the command buffer.
+ */
+uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf)
+{
+ /* the last 8 bytes of the cmd buffer is used as ufence */
+ return (uint64_t)cmd_buf->gpu_addr + cmd_buf->size - 8;
+}
+
+/**
+ * Returns the CPU virtual address of the execution user fence located at the
+ * end of the command buffer.
+ */
+uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf)
+{
+ /* the last 8 bytes of the cmd buffer is used as ufence */
+ return cmd_buf->cpu_addr + cmd_buf->size - 8;
+}
static bool __region_belongs_to_regions_type(struct drm_xe_mem_region *region,
uint32_t *mem_regions_type,
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 6480ea01a..c38f79e60 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -12,6 +12,39 @@
#include <stdint.h>
#include <xe_drm.h>
+#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
+#define ONE_SEC MS_TO_NS(1000)
+#define PAGE_ALIGN_UFENCE 4096
+
+struct xe_buffer {
+ void *cpu_addr;
+ void *gpu_addr;
+ /*the user fence used to vm bind this buffer*/
+ uint32_t *bind_ufence;
+ uint64_t size;
+ uint32_t flag;
+ uint32_t vm;
+ uint32_t bo;
+ uint32_t placement;
+ uint32_t bind_queue;
+ /*only a cmd buffer has a exec queue*/
+ uint32_t exec_queue;
+ int fd;
+ bool is_userptr;
+};
+
+typedef void (*cmdbuf_fill_func_t) (uint32_t *batch, uint64_t dst_gpu_va, uint32_t val);
+void xe_create_buffer(struct xe_buffer *buffer);
+void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func,
+ uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci);
+uint64_t xe_cmdbuf_exec_ufence_gpuva(struct xe_buffer *cmd_buf);
+uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf);
+void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val);
+void xe_submit_cmd(struct xe_buffer *cmdbuf);
+int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf);
+void xe_destroy_buffer(struct xe_buffer *buffer);
+void xe_destroy_cmdbuf(struct xe_buffer *cmd_buf);
+
#define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
(xe_region_class(fd, region) == DRM_XE_MEM_REGION_CLASS_SYSMEM)
#define XE_IS_VRAM_MEMORY_REGION(fd, region) \
--
2.25.1
next prev parent reply other threads:[~2024-05-17 11:46 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-17 11:46 [PATCH i-g-t v3 00/10] tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM) Bommu Krishnaiah
2024-05-17 11:46 ` Bommu Krishnaiah [this message]
2024-05-17 14:09 ` [PATCH i-g-t v3 01/10] lib/xe/xe_util: Introduce helper functions for buffer creation and command submission etc Zeng, Oak
2024-05-17 18:05 ` Kamil Konieczny
2024-05-17 11:46 ` [PATCH i-g-t v3 02/10] tests/intel/xe_svm: basic xe-basic test Bommu Krishnaiah
2024-05-17 14:23 ` Zeng, Oak
2024-05-20 8:51 ` Piecielska, Katarzyna
2024-05-17 11:46 ` [PATCH i-g-t v3 03/10] tests/intel/xe_svm: Add SVM basic tests using malloc and mmap Bommu Krishnaiah
2024-05-17 14:39 ` Zeng, Oak
2024-05-17 17:07 ` Bommu, Krishnaiah
2024-05-17 11:46 ` [PATCH i-g-t v3 04/10] tests/intel/xe_svm: add random access test for SVM Bommu Krishnaiah
2024-05-17 14:48 ` Zeng, Oak
2024-05-17 11:46 ` [PATCH i-g-t v3 05/10] tests/intel/xe_svm: add huge page " Bommu Krishnaiah
2024-05-18 2:01 ` Zeng, Oak
2024-05-17 11:46 ` [PATCH i-g-t v3 06/10] tests/intel/xe_svm: Add support for GPU atomic access test for svm Bommu Krishnaiah
2024-05-18 2:16 ` Zeng, Oak
2024-05-17 11:46 ` [PATCH i-g-t v3 07/10] tests/intel/xe_svm: Add svm-invalid-va test to verify SVM functionality with invalid address access Bommu Krishnaiah
2024-05-18 2:19 ` Zeng, Oak
2024-05-17 11:46 ` [PATCH i-g-t v3 08/10] tests/intel/xe_svm: Add svm-benchmark test to measure SVM performance with a simple benchmark Bommu Krishnaiah
2024-05-18 2:27 ` Zeng, Oak
2024-05-17 11:46 ` [PATCH i-g-t v3 09/10] tests/intel/xe_svm: Add svm-mprotect test to verify SVM functionality with read-only memory access Bommu Krishnaiah
2024-05-17 11:46 ` [PATCH i-g-t v3 10/10] tests/intel/xe_svm: Add svm-sparse-access test to verify sparsely accessing two memory locations with SVM Bommu Krishnaiah
2024-05-17 12:35 ` ✗ GitLab.Pipeline: warning for tests/intel/xe_svm: Add tests for Shared Virtual Memory (SVM) Patchwork
2024-05-17 12:52 ` ✓ CI.xeBAT: success " Patchwork
2024-05-17 13:06 ` ✓ Fi.CI.BAT: " Patchwork
2024-05-17 14:48 ` ✗ CI.xeFULL: failure " Patchwork
2024-05-17 20:00 ` ✗ Fi.CI.IGT: " Patchwork
2024-05-22 11:38 ` [PATCH i-g-t v3 00/10] " Matthew Brost
2024-05-22 11:42 ` Matthew Brost
2024-05-22 16:53 ` Zeng, Oak
2024-05-23 17:26 ` Matthew Brost
2024-05-24 3:12 ` Zeng, Oak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240517114658.810283-2-krishnaiah.bommu@intel.com \
--to=krishnaiah.bommu@intel.com \
--cc=himal.prasad.ghimiray@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=oak.zeng@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox