* [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs
@ 2024-10-25 18:52 Ashutosh Dixit
2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Ashutosh Dixit @ 2024-10-25 18:52 UTC (permalink / raw)
To: igt-dev; +Cc: Umesh Nerlige Ramappa
Ashutosh Dixit (2):
drm-uapi/xe: Sync with OA syncs uapi update
tests/intel/xe_oa: Tests for OA syncs
include/drm-uapi/xe_drm.h | 29 ++++-
lib/xe/xe_oa.c | 6 +-
lib/xe/xe_oa.h | 2 +
tests/intel/xe_oa.c | 261 ++++++++++++++++++++++++++++++++++++++
4 files changed, 290 insertions(+), 8 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit @ 2024-10-25 18:52 ` Ashutosh Dixit 2024-10-25 19:36 ` Umesh Nerlige Ramappa 2024-10-28 15:16 ` Kamil Konieczny 2024-10-25 18:52 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs Ashutosh Dixit ` (3 subsequent siblings) 4 siblings, 2 replies; 14+ messages in thread From: Ashutosh Dixit @ 2024-10-25 18:52 UTC (permalink / raw) To: igt-dev; +Cc: Umesh Nerlige Ramappa Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA sync properties") which adds OA syncs uapi. Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- include/drm-uapi/xe_drm.h | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index f0a450db95..4a8a4a63e9 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -3,8 +3,8 @@ * Copyright © 2023 Intel Corporation */ -#ifndef _XE_DRM_H_ -#define _XE_DRM_H_ +#ifndef _UAPI_XE_DRM_H_ +#define _UAPI_XE_DRM_H_ #include "drm.h" @@ -134,7 +134,7 @@ extern "C" { * redefine the interface more easily than an ever growing struct of * increasing complexity, and for large parts of that interface to be * entirely optional. The downside is more pointer chasing; chasing across - * the boundary with pointers encapsulated inside u64. + * the __user boundary with pointers encapsulated inside u64. * * Example chaining: * @@ -512,7 +512,9 @@ struct drm_xe_query_gt_list { * containing the following in mask: * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` * means 32 DSS are available for compute. - * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks + * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type + * may be omitted if the driver is unable to query the mask from the + * hardware. * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) * available per Dual Sub Slices (DSS). For example a query response * containing the following in mask: @@ -1483,6 +1485,7 @@ struct drm_xe_oa_unit { /** @capabilities: OA capabilities bit-mask */ __u64 capabilities; #define DRM_XE_OA_CAPS_BASE (1 << 0) +#define DRM_XE_OA_CAPS_SYNCS (1 << 1) /** @oa_timestamp_freq: OA timestamp freq */ __u64 oa_timestamp_freq; @@ -1632,6 +1635,22 @@ enum drm_xe_oa_property_id { * to be disabled for the stream exec queue. */ DRM_XE_OA_PROPERTY_NO_PREEMPT, + + /** + * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array + * specified in @DRM_XE_OA_PROPERTY_SYNCS + */ + DRM_XE_OA_PROPERTY_NUM_SYNCS, + + /** + * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array + * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA + * configuration will wait till input fences signal. Output fences + * will signal after the new OA configuration takes effect. For + * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar + * to the VM bind case. + */ + DRM_XE_OA_PROPERTY_SYNCS, }; /** @@ -1698,4 +1717,4 @@ struct drm_xe_oa_stream_info { } #endif -#endif /* _XE_DRM_H_ */ +#endif /* _UAPI_XE_DRM_H_ */ -- 2.41.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update 2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit @ 2024-10-25 19:36 ` Umesh Nerlige Ramappa 2024-10-28 15:16 ` Kamil Konieczny 1 sibling, 0 replies; 14+ messages in thread From: Umesh Nerlige Ramappa @ 2024-10-25 19:36 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: igt-dev On Fri, Oct 25, 2024 at 11:52:04AM -0700, Ashutosh Dixit wrote: >Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA >sync properties") which adds OA syncs uapi. > >Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> >--- > include/drm-uapi/xe_drm.h | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > >diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h >index f0a450db95..4a8a4a63e9 100644 >--- a/include/drm-uapi/xe_drm.h >+++ b/include/drm-uapi/xe_drm.h >@@ -3,8 +3,8 @@ > * Copyright © 2023 Intel Corporation > */ > >-#ifndef _XE_DRM_H_ >-#define _XE_DRM_H_ >+#ifndef _UAPI_XE_DRM_H_ >+#define _UAPI_XE_DRM_H_ > > #include "drm.h" > >@@ -134,7 +134,7 @@ extern "C" { > * redefine the interface more easily than an ever growing struct of > * increasing complexity, and for large parts of that interface to be > * entirely optional. The downside is more pointer chasing; chasing across >- * the boundary with pointers encapsulated inside u64. >+ * the __user boundary with pointers encapsulated inside u64. > * > * Example chaining: > * >@@ -512,7 +512,9 @@ struct drm_xe_query_gt_list { > * containing the following in mask: > * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` > * means 32 DSS are available for compute. >- * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks >+ * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type >+ * may be omitted if the driver is unable to query the mask from the >+ * hardware. > * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) > * available per Dual Sub Slices (DSS). For example a query response > * containing the following in mask: >@@ -1483,6 +1485,7 @@ struct drm_xe_oa_unit { > /** @capabilities: OA capabilities bit-mask */ > __u64 capabilities; > #define DRM_XE_OA_CAPS_BASE (1 << 0) >+#define DRM_XE_OA_CAPS_SYNCS (1 << 1) > > /** @oa_timestamp_freq: OA timestamp freq */ > __u64 oa_timestamp_freq; >@@ -1632,6 +1635,22 @@ enum drm_xe_oa_property_id { > * to be disabled for the stream exec queue. > */ > DRM_XE_OA_PROPERTY_NO_PREEMPT, >+ >+ /** >+ * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array >+ * specified in @DRM_XE_OA_PROPERTY_SYNCS >+ */ >+ DRM_XE_OA_PROPERTY_NUM_SYNCS, >+ >+ /** >+ * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array >+ * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA >+ * configuration will wait till input fences signal. Output fences >+ * will signal after the new OA configuration takes effect. For >+ * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar >+ * to the VM bind case. >+ */ >+ DRM_XE_OA_PROPERTY_SYNCS, > }; > > /** >@@ -1698,4 +1717,4 @@ struct drm_xe_oa_stream_info { > } > #endif > >-#endif /* _XE_DRM_H_ */ >+#endif /* _UAPI_XE_DRM_H_ */ >-- >2.41.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update 2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit 2024-10-25 19:36 ` Umesh Nerlige Ramappa @ 2024-10-28 15:16 ` Kamil Konieczny 2024-10-29 19:38 ` Dixit, Ashutosh 1 sibling, 1 reply; 14+ messages in thread From: Kamil Konieczny @ 2024-10-28 15:16 UTC (permalink / raw) To: igt-dev; +Cc: Ashutosh Dixit, Umesh Nerlige Ramappa Hi Ashutosh, On 2024-10-25 at 11:52:04 -0700, Ashutosh Dixit wrote: > Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA > sync properties") which adds OA syncs uapi. > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > --- > include/drm-uapi/xe_drm.h | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h > index f0a450db95..4a8a4a63e9 100644 > --- a/include/drm-uapi/xe_drm.h > +++ b/include/drm-uapi/xe_drm.h > @@ -3,8 +3,8 @@ > * Copyright © 2023 Intel Corporation > */ > > -#ifndef _XE_DRM_H_ > -#define _XE_DRM_H_ > +#ifndef _UAPI_XE_DRM_H_ > +#define _UAPI_XE_DRM_H_ imho this shouldn't be here, did you use make INSTALL_HDR_PATH=<dest-dir> headers_install documented in README.md? Regards, Kamil > > #include "drm.h" > > @@ -134,7 +134,7 @@ extern "C" { > * redefine the interface more easily than an ever growing struct of > * increasing complexity, and for large parts of that interface to be > * entirely optional. The downside is more pointer chasing; chasing across > - * the boundary with pointers encapsulated inside u64. > + * the __user boundary with pointers encapsulated inside u64. > * > * Example chaining: > * > @@ -512,7 +512,9 @@ struct drm_xe_query_gt_list { > * containing the following in mask: > * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` > * means 32 DSS are available for compute. > - * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks > + * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type > + * may be omitted if the driver is unable to query the mask from the > + * hardware. > * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) > * available per Dual Sub Slices (DSS). For example a query response > * containing the following in mask: > @@ -1483,6 +1485,7 @@ struct drm_xe_oa_unit { > /** @capabilities: OA capabilities bit-mask */ > __u64 capabilities; > #define DRM_XE_OA_CAPS_BASE (1 << 0) > +#define DRM_XE_OA_CAPS_SYNCS (1 << 1) > > /** @oa_timestamp_freq: OA timestamp freq */ > __u64 oa_timestamp_freq; > @@ -1632,6 +1635,22 @@ enum drm_xe_oa_property_id { > * to be disabled for the stream exec queue. > */ > DRM_XE_OA_PROPERTY_NO_PREEMPT, > + > + /** > + * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array > + * specified in @DRM_XE_OA_PROPERTY_SYNCS > + */ > + DRM_XE_OA_PROPERTY_NUM_SYNCS, > + > + /** > + * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array > + * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA > + * configuration will wait till input fences signal. Output fences > + * will signal after the new OA configuration takes effect. For > + * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar > + * to the VM bind case. > + */ > + DRM_XE_OA_PROPERTY_SYNCS, > }; > > /** > @@ -1698,4 +1717,4 @@ struct drm_xe_oa_stream_info { > } > #endif > > -#endif /* _XE_DRM_H_ */ > +#endif /* _UAPI_XE_DRM_H_ */ > -- > 2.41.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update 2024-10-28 15:16 ` Kamil Konieczny @ 2024-10-29 19:38 ` Dixit, Ashutosh 0 siblings, 0 replies; 14+ messages in thread From: Dixit, Ashutosh @ 2024-10-29 19:38 UTC (permalink / raw) To: Kamil Konieczny, igt-dev, Ashutosh Dixit, Umesh Nerlige Ramappa On Mon, 28 Oct 2024 08:16:55 -0700, Kamil Konieczny wrote: > > Hi Ashutosh, > On 2024-10-25 at 11:52:04 -0700, Ashutosh Dixit wrote: > > Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA > > sync properties") which adds OA syncs uapi. > > > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > > --- > > include/drm-uapi/xe_drm.h | 29 ++++++++++++++++++++++++----- > > 1 file changed, 24 insertions(+), 5 deletions(-) > > > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h > > index f0a450db95..4a8a4a63e9 100644 > > --- a/include/drm-uapi/xe_drm.h > > +++ b/include/drm-uapi/xe_drm.h > > @@ -3,8 +3,8 @@ > > * Copyright © 2023 Intel Corporation > > */ > > > > -#ifndef _XE_DRM_H_ > > -#define _XE_DRM_H_ > > +#ifndef _UAPI_XE_DRM_H_ > > +#define _UAPI_XE_DRM_H_ > > imho this shouldn't be here, did you use > make INSTALL_HDR_PATH=<dest-dir> headers_install > > documented in README.md? Thanks Kamil, I didn't know about INSTALL_HDR_PATH. Will fix this in the next version. Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit 2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit @ 2024-10-25 18:52 ` Ashutosh Dixit 2024-10-25 19:35 ` Umesh Nerlige Ramappa 2024-10-25 22:02 ` ✓ Fi.CI.BAT: success for tests/intel/oa: Tests for OA syncs (rev4) Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Ashutosh Dixit @ 2024-10-25 18:52 UTC (permalink / raw) To: igt-dev; +Cc: Umesh Nerlige Ramappa Verify OA syncs signal correctly in open and change config code paths. Verify with different types of sync objects as well as by both waiting and skipping the wait for syncs to signal. v2: Significantly expand oa syncs testing as described above Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- lib/xe/xe_oa.c | 6 +- lib/xe/xe_oa.h | 2 + tests/intel/xe_oa.c | 261 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+), 3 deletions(-) diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c index 4fdd0b8c95..c168669c5d 100644 --- a/lib/xe/xe_oa.c +++ b/lib/xe/xe_oa.c @@ -1025,8 +1025,8 @@ const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, return "unknown"; } -static void xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, - struct drm_xe_ext_set_property *extn) +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, + struct drm_xe_ext_set_property *extn) { __u64 *prop = from_user_pointer(properties->properties_ptr); struct drm_xe_ext_set_property *ext = extn; @@ -1063,7 +1063,7 @@ int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg) struct intel_xe_oa_open_prop *oprop = (struct intel_xe_oa_open_prop *)arg; igt_assert_lte(oprop->num_properties, XE_OA_MAX_SET_PROPERTIES); - xe_oa_prop_to_ext(oprop, ext); + intel_xe_oa_prop_to_ext(oprop, ext); } return igt_ioctl(fd, DRM_IOCTL_XE_OBSERVATION, &p); diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h index 962f9dddcc..7d3d074560 100644 --- a/lib/xe/xe_oa.h +++ b/lib/xe/xe_oa.h @@ -398,6 +398,8 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, const struct intel_xe_perf_record_header *record); +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, + struct drm_xe_ext_set_property *extn); int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg); void intel_xe_perf_ioctl_err(int fd, enum drm_xe_observation_op op, void *arg, int err); diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c index 92f5828c79..27f30ebe73 100644 --- a/tests/intel/xe_oa.c +++ b/tests/intel/xe_oa.c @@ -22,6 +22,7 @@ #include "drm.h" #include "igt.h" #include "igt_device.h" +#include "igt_syncobj.h" #include "igt_sysfs.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" @@ -4463,6 +4464,231 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open, __perf_close(stream_fd); } + +/* Return alternative config_id if available, else just return config_id */ +static void find_alt_oa_config(u32 config_id, u32 *alt_config_id) +{ + struct dirent *entry; + int metrics_fd, dir_fd; + DIR *metrics_dir; + bool ret; + + metrics_fd = openat(sysfs, "metrics", O_DIRECTORY); + igt_assert_lte(0, metrics_fd); + + metrics_dir = fdopendir(metrics_fd); + igt_assert(metrics_dir); + + while ((entry = readdir(metrics_dir))) { + if (entry->d_type != DT_DIR) + continue; + + dir_fd = openat(metrics_fd, entry->d_name, O_RDONLY); + ret = __igt_sysfs_get_u32(dir_fd, "id", alt_config_id); + close(dir_fd); + if (!ret) + continue; + + if (config_id != *alt_config_id) + goto exit; + } + + *alt_config_id = config_id; +exit: + closedir(metrics_dir); +} + +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + +#define WAIT (0x1 << 0) +#define CONFIG (0x1 << 1) + +enum oa_sync_type { + OA_SYNC_TYPE_SYNCOBJ, + OA_SYNC_TYPE_USERPTR, + OA_SYNC_TYPE_UFENCE, +}; + +struct oa_sync { + enum oa_sync_type sync_type; + u32 syncobj; + u32 vm; + u32 bo; + size_t bo_size; + struct { + uint64_t vm_sync; + uint64_t pad; + uint64_t oa_sync; + } *data; +}; + +static void +oa_sync_init(enum oa_sync_type sync_type, const struct drm_xe_engine_class_instance *hwe, + struct oa_sync *osync, struct drm_xe_sync *sync) +{ + uint64_t addr = 0x1a0000; + + osync->sync_type = sync_type; + sync->flags = DRM_XE_SYNC_FLAG_SIGNAL; + + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + osync->syncobj = syncobj_create(drm_fd, 0); + sync->handle = osync->syncobj; + sync->type = DRM_XE_SYNC_TYPE_SYNCOBJ; + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + sync->type = DRM_XE_SYNC_TYPE_USER_FENCE; + sync->timeline_value = USER_FENCE_VALUE; + + osync->vm = xe_vm_create(drm_fd, 0, 0); + osync->bo_size = xe_bb_size(drm_fd, sizeof(*osync->data)); + if (osync->sync_type == OA_SYNC_TYPE_USERPTR) { + osync->data = aligned_alloc(xe_get_default_alignment(drm_fd), + osync->bo_size); + igt_assert(osync->data); + } else { + osync->bo = xe_bo_create(drm_fd, osync->vm, osync->bo_size, + vram_if_possible(drm_fd, hwe->gt_id), + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); + osync->data = xe_bo_map(drm_fd, osync->bo, osync->bo_size); + } + memset(osync->data, 0, osync->bo_size); + + sync->addr = to_user_pointer(&osync->data[0].vm_sync); + if (osync->bo) + xe_vm_bind_async(drm_fd, osync->vm, 0, osync->bo, 0, + addr, osync->bo_size, sync, 1); + else + xe_vm_bind_userptr_async(drm_fd, osync->vm, 0, + to_user_pointer(osync->data), + addr, osync->bo_size, sync, 1); + xe_wait_ufence(drm_fd, &osync->data[0].vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + + sync->addr = to_user_pointer(&osync->data[0].oa_sync); + break; + default: + igt_assert(false); + } +} + +static void oa_sync_wait(struct oa_sync *osync) +{ + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + igt_assert(syncobj_wait(drm_fd, &osync->syncobj, 1, INT64_MAX, 0, NULL)); + syncobj_reset(drm_fd, &osync->syncobj, 1); + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + xe_wait_ufence(drm_fd, &osync->data[0].oa_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + osync->data[0].oa_sync = 0; + break; + default: + igt_assert(false); + } +} + +static void oa_sync_free(struct oa_sync *osync) +{ + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + syncobj_destroy(drm_fd, osync->syncobj); + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + if (osync->bo) { + munmap(osync->data, osync->bo_size); + gem_close(drm_fd, osync->bo); + } else { + free(osync->data); + } + xe_vm_destroy(drm_fd, osync->vm); + break; + default: + igt_assert(false); + } +} + +/** + * SUBTEST: syncs-%s-%s + * + * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and + * reconfig flags) signal correctly in open and reconfig code + * paths + * + * arg[1]: + * + * @syncobj: sync type syncobj + * @userptr: sync type userptr + * @ufence: sync type ufence + * + * arg[2]: + * + * @wait-cfg: Exercise reconfig path and wait for syncs to signal + * @wait: Don't exercise reconfig path and wait for syncs to signal + * @cfg: Exercise reconfig path but don't wait for syncs to signal + * @none: Don't exercise reconfig path and don't wait for syncs to signal + */ +static void test_syncs(const struct drm_xe_engine_class_instance *hwe, + enum oa_sync_type sync_type, int flags) +{ + struct drm_xe_ext_set_property extn[XE_OA_MAX_SET_PROPERTIES] = {}; + struct intel_xe_perf_metric_set *test_set = metric_set(hwe); + struct drm_xe_sync sync = {}; + struct oa_sync osync = {}; + uint64_t open_properties[] = { + DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0, + DRM_XE_OA_PROPERTY_SAMPLE_OA, true, + DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set, + DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format), + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), + }; + struct intel_xe_oa_open_prop open_param = { + .num_properties = ARRAY_SIZE(open_properties) / 2, + .properties_ptr = to_user_pointer(open_properties), + }; + uint64_t config_properties[] = { + DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0, /* Filled later */ + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), + }; + struct intel_xe_oa_open_prop config_param = { + .num_properties = ARRAY_SIZE(config_properties) / 2, + .properties_ptr = to_user_pointer(config_properties), + }; + uint32_t alt_config_id; + int ret; + + oa_sync_init(sync_type, hwe, &osync, &sync); + + stream_fd = __perf_open(drm_fd, &open_param, false); + + /* Reset the sync object if we are going to reconfig the stream */ + if (flags & (WAIT | CONFIG)) + oa_sync_wait(&osync); + + if (!(flags & CONFIG)) + goto exit; + + /* Change stream configuration */ + find_alt_oa_config(test_set->perf_oa_metrics_set, &alt_config_id); + + config_properties[1] = alt_config_id; + intel_xe_oa_prop_to_ext(&config_param, extn); + + ret = igt_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_CONFIG, extn); + igt_assert_eq(ret, test_set->perf_oa_metrics_set); + + if (flags & WAIT) + oa_sync_wait(&osync); +exit: + __perf_close(stream_fd); + oa_sync_free(&osync); +} + static const char *xe_engine_class_name(uint32_t engine_class) { switch (engine_class) { @@ -4511,6 +4737,25 @@ static const char *xe_engine_class_name(uint32_t engine_class) igt_main { + const struct sync_section { + const char *name; + enum oa_sync_type sync_type; + unsigned int flags; + } sync_sections[] = { + { "syncobj-wait-cfg", OA_SYNC_TYPE_SYNCOBJ, WAIT | CONFIG}, + { "syncobj-wait", OA_SYNC_TYPE_SYNCOBJ, WAIT }, + { "syncobj-cfg", OA_SYNC_TYPE_SYNCOBJ, CONFIG }, + { "syncobj-none", OA_SYNC_TYPE_SYNCOBJ, 0 }, + { "userptr-wait-cfg", OA_SYNC_TYPE_USERPTR, WAIT | CONFIG}, + { "userptr-wait", OA_SYNC_TYPE_USERPTR, WAIT }, + { "userptr-cfg", OA_SYNC_TYPE_USERPTR, CONFIG }, + { "userptr-none", OA_SYNC_TYPE_USERPTR, 0 }, + { "ufence-wait-cfg", OA_SYNC_TYPE_UFENCE, WAIT | CONFIG}, + { "ufence-wait", OA_SYNC_TYPE_UFENCE, WAIT }, + { "ufence-cfg", OA_SYNC_TYPE_UFENCE, CONFIG }, + { "ufence-none", OA_SYNC_TYPE_UFENCE, 0 }, + { NULL }, + }; struct drm_xe_engine_class_instance *hwe = NULL; struct xe_device *xe_dev; @@ -4713,6 +4958,22 @@ igt_main } } + igt_subtest_group { + igt_fixture { + struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd); + struct drm_xe_oa_unit *oau = (struct drm_xe_oa_unit *)&qoa->oa_units[0]; + + igt_require(oau->capabilities & DRM_XE_OA_CAPS_SYNCS); + } + + for (const struct sync_section *s = sync_sections; s->name; s++) { + igt_subtest_with_dynamic_f("syncs-%s", s->name) + __for_one_render_engine(hwe) + test_syncs(hwe, s->sync_type, s->flags); + + } + } + igt_fixture { /* leave sysctl options in their default state... */ write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1); -- 2.41.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-25 18:52 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs Ashutosh Dixit @ 2024-10-25 19:35 ` Umesh Nerlige Ramappa 2024-10-25 19:45 ` Dixit, Ashutosh 0 siblings, 1 reply; 14+ messages in thread From: Umesh Nerlige Ramappa @ 2024-10-25 19:35 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: igt-dev On Fri, Oct 25, 2024 at 11:52:05AM -0700, Ashutosh Dixit wrote: >Verify OA syncs signal correctly in open and change config code >paths. Verify with different types of sync objects as well as by both >waiting and skipping the wait for syncs to signal. > >v2: Significantly expand oa syncs testing as described above Are we just enabling output sync for the OA use case, as in, user can only wait for the OA configuration to complete, but cannot control when the OA config starts? Which is what existed earlier, so it should be fine either ways. LGTM, Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > >Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> >--- > lib/xe/xe_oa.c | 6 +- > lib/xe/xe_oa.h | 2 + > tests/intel/xe_oa.c | 261 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 266 insertions(+), 3 deletions(-) > >diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c >index 4fdd0b8c95..c168669c5d 100644 >--- a/lib/xe/xe_oa.c >+++ b/lib/xe/xe_oa.c >@@ -1025,8 +1025,8 @@ const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, > return "unknown"; > } > >-static void xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, >- struct drm_xe_ext_set_property *extn) >+void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, >+ struct drm_xe_ext_set_property *extn) > { > __u64 *prop = from_user_pointer(properties->properties_ptr); > struct drm_xe_ext_set_property *ext = extn; >@@ -1063,7 +1063,7 @@ int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg) > struct intel_xe_oa_open_prop *oprop = (struct intel_xe_oa_open_prop *)arg; > > igt_assert_lte(oprop->num_properties, XE_OA_MAX_SET_PROPERTIES); >- xe_oa_prop_to_ext(oprop, ext); >+ intel_xe_oa_prop_to_ext(oprop, ext); > } > > return igt_ioctl(fd, DRM_IOCTL_XE_OBSERVATION, &p); >diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h >index 962f9dddcc..7d3d074560 100644 >--- a/lib/xe/xe_oa.h >+++ b/lib/xe/xe_oa.h >@@ -398,6 +398,8 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per > const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, > const struct intel_xe_perf_record_header *record); > >+void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, >+ struct drm_xe_ext_set_property *extn); > int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg); > void intel_xe_perf_ioctl_err(int fd, enum drm_xe_observation_op op, void *arg, int err); > >diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c >index 92f5828c79..27f30ebe73 100644 >--- a/tests/intel/xe_oa.c >+++ b/tests/intel/xe_oa.c >@@ -22,6 +22,7 @@ > #include "drm.h" > #include "igt.h" > #include "igt_device.h" >+#include "igt_syncobj.h" > #include "igt_sysfs.h" > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" >@@ -4463,6 +4464,231 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open, > __perf_close(stream_fd); > } > >+ >+/* Return alternative config_id if available, else just return config_id */ >+static void find_alt_oa_config(u32 config_id, u32 *alt_config_id) >+{ >+ struct dirent *entry; >+ int metrics_fd, dir_fd; >+ DIR *metrics_dir; >+ bool ret; >+ >+ metrics_fd = openat(sysfs, "metrics", O_DIRECTORY); >+ igt_assert_lte(0, metrics_fd); >+ >+ metrics_dir = fdopendir(metrics_fd); >+ igt_assert(metrics_dir); >+ >+ while ((entry = readdir(metrics_dir))) { >+ if (entry->d_type != DT_DIR) >+ continue; >+ >+ dir_fd = openat(metrics_fd, entry->d_name, O_RDONLY); >+ ret = __igt_sysfs_get_u32(dir_fd, "id", alt_config_id); >+ close(dir_fd); >+ if (!ret) >+ continue; >+ >+ if (config_id != *alt_config_id) >+ goto exit; >+ } >+ >+ *alt_config_id = config_id; >+exit: >+ closedir(metrics_dir); >+} >+ >+#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull >+ >+#define WAIT (0x1 << 0) >+#define CONFIG (0x1 << 1) >+ >+enum oa_sync_type { >+ OA_SYNC_TYPE_SYNCOBJ, >+ OA_SYNC_TYPE_USERPTR, >+ OA_SYNC_TYPE_UFENCE, >+}; >+ >+struct oa_sync { >+ enum oa_sync_type sync_type; >+ u32 syncobj; >+ u32 vm; >+ u32 bo; >+ size_t bo_size; >+ struct { >+ uint64_t vm_sync; >+ uint64_t pad; >+ uint64_t oa_sync; >+ } *data; >+}; >+ >+static void >+oa_sync_init(enum oa_sync_type sync_type, const struct drm_xe_engine_class_instance *hwe, >+ struct oa_sync *osync, struct drm_xe_sync *sync) >+{ >+ uint64_t addr = 0x1a0000; >+ >+ osync->sync_type = sync_type; >+ sync->flags = DRM_XE_SYNC_FLAG_SIGNAL; >+ >+ switch (osync->sync_type) { >+ case OA_SYNC_TYPE_SYNCOBJ: >+ osync->syncobj = syncobj_create(drm_fd, 0); >+ sync->handle = osync->syncobj; >+ sync->type = DRM_XE_SYNC_TYPE_SYNCOBJ; >+ break; >+ case OA_SYNC_TYPE_USERPTR: >+ case OA_SYNC_TYPE_UFENCE: >+ sync->type = DRM_XE_SYNC_TYPE_USER_FENCE; >+ sync->timeline_value = USER_FENCE_VALUE; >+ >+ osync->vm = xe_vm_create(drm_fd, 0, 0); >+ osync->bo_size = xe_bb_size(drm_fd, sizeof(*osync->data)); >+ if (osync->sync_type == OA_SYNC_TYPE_USERPTR) { >+ osync->data = aligned_alloc(xe_get_default_alignment(drm_fd), >+ osync->bo_size); >+ igt_assert(osync->data); >+ } else { >+ osync->bo = xe_bo_create(drm_fd, osync->vm, osync->bo_size, >+ vram_if_possible(drm_fd, hwe->gt_id), >+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); >+ osync->data = xe_bo_map(drm_fd, osync->bo, osync->bo_size); >+ } >+ memset(osync->data, 0, osync->bo_size); >+ >+ sync->addr = to_user_pointer(&osync->data[0].vm_sync); >+ if (osync->bo) >+ xe_vm_bind_async(drm_fd, osync->vm, 0, osync->bo, 0, >+ addr, osync->bo_size, sync, 1); >+ else >+ xe_vm_bind_userptr_async(drm_fd, osync->vm, 0, >+ to_user_pointer(osync->data), >+ addr, osync->bo_size, sync, 1); >+ xe_wait_ufence(drm_fd, &osync->data[0].vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); >+ >+ sync->addr = to_user_pointer(&osync->data[0].oa_sync); >+ break; >+ default: >+ igt_assert(false); >+ } >+} >+ >+static void oa_sync_wait(struct oa_sync *osync) >+{ >+ switch (osync->sync_type) { >+ case OA_SYNC_TYPE_SYNCOBJ: >+ igt_assert(syncobj_wait(drm_fd, &osync->syncobj, 1, INT64_MAX, 0, NULL)); >+ syncobj_reset(drm_fd, &osync->syncobj, 1); >+ break; >+ case OA_SYNC_TYPE_USERPTR: >+ case OA_SYNC_TYPE_UFENCE: >+ xe_wait_ufence(drm_fd, &osync->data[0].oa_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); >+ osync->data[0].oa_sync = 0; >+ break; >+ default: >+ igt_assert(false); >+ } >+} >+ >+static void oa_sync_free(struct oa_sync *osync) >+{ >+ switch (osync->sync_type) { >+ case OA_SYNC_TYPE_SYNCOBJ: >+ syncobj_destroy(drm_fd, osync->syncobj); >+ break; >+ case OA_SYNC_TYPE_USERPTR: >+ case OA_SYNC_TYPE_UFENCE: >+ if (osync->bo) { >+ munmap(osync->data, osync->bo_size); >+ gem_close(drm_fd, osync->bo); >+ } else { >+ free(osync->data); >+ } >+ xe_vm_destroy(drm_fd, osync->vm); >+ break; >+ default: >+ igt_assert(false); >+ } >+} >+ >+/** >+ * SUBTEST: syncs-%s-%s >+ * >+ * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and >+ * reconfig flags) signal correctly in open and reconfig code >+ * paths >+ * >+ * arg[1]: >+ * >+ * @syncobj: sync type syncobj >+ * @userptr: sync type userptr >+ * @ufence: sync type ufence >+ * >+ * arg[2]: >+ * >+ * @wait-cfg: Exercise reconfig path and wait for syncs to signal >+ * @wait: Don't exercise reconfig path and wait for syncs to signal >+ * @cfg: Exercise reconfig path but don't wait for syncs to signal >+ * @none: Don't exercise reconfig path and don't wait for syncs to signal >+ */ >+static void test_syncs(const struct drm_xe_engine_class_instance *hwe, >+ enum oa_sync_type sync_type, int flags) >+{ >+ struct drm_xe_ext_set_property extn[XE_OA_MAX_SET_PROPERTIES] = {}; >+ struct intel_xe_perf_metric_set *test_set = metric_set(hwe); >+ struct drm_xe_sync sync = {}; >+ struct oa_sync osync = {}; >+ uint64_t open_properties[] = { >+ DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0, >+ DRM_XE_OA_PROPERTY_SAMPLE_OA, true, >+ DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set, >+ DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format), >+ DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, >+ DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), >+ }; >+ struct intel_xe_oa_open_prop open_param = { >+ .num_properties = ARRAY_SIZE(open_properties) / 2, >+ .properties_ptr = to_user_pointer(open_properties), >+ }; >+ uint64_t config_properties[] = { >+ DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0, /* Filled later */ >+ DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, >+ DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), >+ }; >+ struct intel_xe_oa_open_prop config_param = { >+ .num_properties = ARRAY_SIZE(config_properties) / 2, >+ .properties_ptr = to_user_pointer(config_properties), >+ }; >+ uint32_t alt_config_id; >+ int ret; >+ >+ oa_sync_init(sync_type, hwe, &osync, &sync); >+ >+ stream_fd = __perf_open(drm_fd, &open_param, false); >+ >+ /* Reset the sync object if we are going to reconfig the stream */ >+ if (flags & (WAIT | CONFIG)) >+ oa_sync_wait(&osync); >+ >+ if (!(flags & CONFIG)) >+ goto exit; >+ >+ /* Change stream configuration */ >+ find_alt_oa_config(test_set->perf_oa_metrics_set, &alt_config_id); >+ >+ config_properties[1] = alt_config_id; >+ intel_xe_oa_prop_to_ext(&config_param, extn); >+ >+ ret = igt_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_CONFIG, extn); >+ igt_assert_eq(ret, test_set->perf_oa_metrics_set); >+ >+ if (flags & WAIT) >+ oa_sync_wait(&osync); >+exit: >+ __perf_close(stream_fd); >+ oa_sync_free(&osync); >+} >+ > static const char *xe_engine_class_name(uint32_t engine_class) > { > switch (engine_class) { >@@ -4511,6 +4737,25 @@ static const char *xe_engine_class_name(uint32_t engine_class) > > igt_main > { >+ const struct sync_section { >+ const char *name; >+ enum oa_sync_type sync_type; >+ unsigned int flags; >+ } sync_sections[] = { >+ { "syncobj-wait-cfg", OA_SYNC_TYPE_SYNCOBJ, WAIT | CONFIG}, >+ { "syncobj-wait", OA_SYNC_TYPE_SYNCOBJ, WAIT }, >+ { "syncobj-cfg", OA_SYNC_TYPE_SYNCOBJ, CONFIG }, >+ { "syncobj-none", OA_SYNC_TYPE_SYNCOBJ, 0 }, >+ { "userptr-wait-cfg", OA_SYNC_TYPE_USERPTR, WAIT | CONFIG}, >+ { "userptr-wait", OA_SYNC_TYPE_USERPTR, WAIT }, >+ { "userptr-cfg", OA_SYNC_TYPE_USERPTR, CONFIG }, >+ { "userptr-none", OA_SYNC_TYPE_USERPTR, 0 }, >+ { "ufence-wait-cfg", OA_SYNC_TYPE_UFENCE, WAIT | CONFIG}, >+ { "ufence-wait", OA_SYNC_TYPE_UFENCE, WAIT }, >+ { "ufence-cfg", OA_SYNC_TYPE_UFENCE, CONFIG }, >+ { "ufence-none", OA_SYNC_TYPE_UFENCE, 0 }, >+ { NULL }, >+ }; > struct drm_xe_engine_class_instance *hwe = NULL; > struct xe_device *xe_dev; > >@@ -4713,6 +4958,22 @@ igt_main > } > } > >+ igt_subtest_group { >+ igt_fixture { >+ struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd); >+ struct drm_xe_oa_unit *oau = (struct drm_xe_oa_unit *)&qoa->oa_units[0]; >+ >+ igt_require(oau->capabilities & DRM_XE_OA_CAPS_SYNCS); >+ } >+ >+ for (const struct sync_section *s = sync_sections; s->name; s++) { >+ igt_subtest_with_dynamic_f("syncs-%s", s->name) >+ __for_one_render_engine(hwe) >+ test_syncs(hwe, s->sync_type, s->flags); >+ >+ } >+ } >+ > igt_fixture { > /* leave sysctl options in their default state... */ > write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1); >-- >2.41.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-25 19:35 ` Umesh Nerlige Ramappa @ 2024-10-25 19:45 ` Dixit, Ashutosh 0 siblings, 0 replies; 14+ messages in thread From: Dixit, Ashutosh @ 2024-10-25 19:45 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: igt-dev On Fri, 25 Oct 2024 12:35:35 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh, > On Fri, Oct 25, 2024 at 11:52:05AM -0700, Ashutosh Dixit wrote: > > Verify OA syncs signal correctly in open and change config code > > paths. Verify with different types of sync objects as well as by both > > waiting and skipping the wait for syncs to signal. > > > > v2: Significantly expand oa syncs testing as described above > > Are we just enabling output sync for the OA use case, as in, user can only > wait for the OA configuration to complete, but cannot control when the OA > config starts? No, both input and output syncs are implemented in the kernel. But this patch only adds tests for the output syncs. I am tracking writing tests for input syncs elsewhere. Input syncs are also straightforward, xe_sync_entry_add_deps() basically does that for you, you just need to call that function from the right place. The output sync's are quite tricky and I have fixed many uaf bugs with these tests. > Which is what existed earlier, so it should be fine either ways. You need both input and output syncs for it to be useful (that allows pipelining the workload while keeping it sync'd with a particular OA config). Mesa is using and have tested both. > > LGTM, > > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for tests/intel/oa: Tests for OA syncs (rev4) 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit 2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit 2024-10-25 18:52 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs Ashutosh Dixit @ 2024-10-25 22:02 ` Patchwork 2024-10-25 22:28 ` ✓ CI.xeBAT: " Patchwork 2024-10-27 12:56 ` ✗ CI.xeFULL: failure " Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2024-10-25 22:02 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 4706 bytes --] == Series Details == Series: tests/intel/oa: Tests for OA syncs (rev4) URL : https://patchwork.freedesktop.org/series/137482/ State : success == Summary == CI Bug Log - changes from IGT_8086 -> IGTPW_11987 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/index.html Participating hosts (46 -> 45) ------------------------------ Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_11987 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - bat-arls-2: [PASS][1] -> [SKIP][2] ([i915#10341]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-arls-2/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-arls-2/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live: - bat-mtlp-8: [PASS][3] -> [ABORT][4] ([i915#12216]) +1 other test abort [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-mtlp-8/igt@i915_selftest@live.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-mtlp-8/igt@i915_selftest@live.html * igt@i915_selftest@live@late_gt_pm: - bat-arls-2: [PASS][5] -> [DMESG-FAIL][6] ([i915#10262]) +37 other tests dmesg-fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-arls-2/igt@i915_selftest@live@late_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-arls-2/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-dg2-13: [PASS][7] -> [DMESG-WARN][8] ([i915#12253]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html #### Possible fixes #### * igt@i915_selftest@live: - bat-arlh-3: [ABORT][9] ([i915#12133]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-arlh-3/igt@i915_selftest@live.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-arlh-3/igt@i915_selftest@live.html - bat-adlp-6: [INCOMPLETE][11] ([i915#9413]) -> [PASS][12] +1 other test pass [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-adlp-6/igt@i915_selftest@live.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-adlp-6/igt@i915_selftest@live.html - bat-twl-2: [DMESG-WARN][13] ([i915#12133]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-twl-2/igt@i915_selftest@live.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-twl-2/igt@i915_selftest@live.html * igt@i915_selftest@live@gt_mocs: - bat-twl-2: [DMESG-WARN][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-twl-2/igt@i915_selftest@live@gt_mocs.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-twl-2/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@workarounds: - bat-arlh-3: [ABORT][17] ([i915#12061]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8086/bat-arlh-3/igt@i915_selftest@live@workarounds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/bat-arlh-3/igt@i915_selftest@live@workarounds.html [i915#10262]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262 [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341 [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 [i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133 [i915#12216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12216 [i915#12253]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12253 [i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_8086 -> IGTPW_11987 * Linux: CI_DRM_15600 -> CI_DRM_15601 CI-20190529: 20190529 CI_DRM_15600: 263b21a91964ddc599f4f85cf3511b0aafd2028e @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_15601: 3ec61d11c7429a65dcc3ac46b9e845f13891a306 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_11987: 690bba0c6a9a345ec062cba6ba7b6e1e4f71f6b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git IGT_8086: 18939acec2446c6644644186b090d16e366af8bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11987/index.html [-- Attachment #2: Type: text/html, Size: 5562 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.xeBAT: success for tests/intel/oa: Tests for OA syncs (rev4) 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit ` (2 preceding siblings ...) 2024-10-25 22:02 ` ✓ Fi.CI.BAT: success for tests/intel/oa: Tests for OA syncs (rev4) Patchwork @ 2024-10-25 22:28 ` Patchwork 2024-10-27 12:56 ` ✗ CI.xeFULL: failure " Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2024-10-25 22:28 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 8450 bytes --] == Series Details == Series: tests/intel/oa: Tests for OA syncs (rev4) URL : https://patchwork.freedesktop.org/series/137482/ State : success == Summary == CI Bug Log - changes from XEIGT_8086_BAT -> XEIGTPW_11987_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in XEIGTPW_11987_BAT that come from known issues: ### IGT changes ### #### Issues hit #### * igt@xe_exec_fault_mode@twice-invalid-fault: - bat-lnl-2: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#3230]) [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-2/igt@xe_exec_fault_mode@twice-invalid-fault.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-2/igt@xe_exec_fault_mode@twice-invalid-fault.html * igt@xe_exec_reset@cm-close-fd-no-exec: - bat-lnl-1: [PASS][3] -> [DMESG-WARN][4] ([Intel XE#3230]) [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-1/igt@xe_exec_reset@cm-close-fd-no-exec.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-1/igt@xe_exec_reset@cm-close-fd-no-exec.html - bat-adlp-7: [PASS][5] -> [DMESG-WARN][6] ([Intel XE#3230]) [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-adlp-7/igt@xe_exec_reset@cm-close-fd-no-exec.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-adlp-7/igt@xe_exec_reset@cm-close-fd-no-exec.html * igt@xe_exec_threads@threads-mixed-basic: - bat-dg2-oem2: [PASS][7] -> [DMESG-WARN][8] ([Intel XE#3230]) [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-dg2-oem2/igt@xe_exec_threads@threads-mixed-basic.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-dg2-oem2/igt@xe_exec_threads@threads-mixed-basic.html - bat-atsm-2: [PASS][9] -> [DMESG-WARN][10] ([Intel XE#3230]) [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-atsm-2/igt@xe_exec_threads@threads-mixed-basic.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-atsm-2/igt@xe_exec_threads@threads-mixed-basic.html - bat-pvc-2: [PASS][11] -> [DMESG-WARN][12] ([Intel XE#3230]) [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-pvc-2/igt@xe_exec_threads@threads-mixed-basic.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-pvc-2/igt@xe_exec_threads@threads-mixed-basic.html * igt@xe_live_ktest@xe_bo: - bat-lnl-1: [PASS][13] -> [SKIP][14] ([Intel XE#1192]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-1/igt@xe_live_ktest@xe_bo.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-1/igt@xe_live_ktest@xe_bo.html * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit: - bat-lnl-2: NOTRUN -> [SKIP][15] ([Intel XE#2229]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-2/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html * igt@xe_live_ktest@xe_migrate: - bat-adlp-7: [PASS][16] -> [SKIP][17] ([Intel XE#1192]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-adlp-7/igt@xe_live_ktest@xe_migrate.html [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-adlp-7/igt@xe_live_ktest@xe_migrate.html * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit: - bat-atsm-2: NOTRUN -> [SKIP][18] ([Intel XE#2229]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html - bat-adlp-vf: NOTRUN -> [SKIP][19] ([Intel XE#2229]) +2 other tests skip [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-adlp-vf/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html - bat-pvc-2: NOTRUN -> [SKIP][20] ([Intel XE#2229]) +2 other tests skip [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-pvc-2/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html #### Possible fixes #### * igt@xe_exec_compute_mode@twice-preempt-fence-early: - bat-pvc-2: [DMESG-WARN][21] -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-pvc-2/igt@xe_exec_compute_mode@twice-preempt-fence-early.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-pvc-2/igt@xe_exec_compute_mode@twice-preempt-fence-early.html * igt@xe_exec_fault_mode@twice-invalid-fault: - bat-lnl-1: [DMESG-WARN][23] ([Intel XE#3230]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-1/igt@xe_exec_fault_mode@twice-invalid-fault.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-1/igt@xe_exec_fault_mode@twice-invalid-fault.html * igt@xe_exec_reset@cm-close-fd-no-exec: - bat-adlp-vf: [DMESG-WARN][25] ([Intel XE#3230]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-adlp-vf/igt@xe_exec_reset@cm-close-fd-no-exec.html [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-adlp-vf/igt@xe_exec_reset@cm-close-fd-no-exec.html - bat-lnl-2: [DMESG-WARN][27] ([Intel XE#3230]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-2/igt@xe_exec_reset@cm-close-fd-no-exec.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-2/igt@xe_exec_reset@cm-close-fd-no-exec.html - bat-atsm-2: [DMESG-WARN][29] ([Intel XE#3230]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-atsm-2/igt@xe_exec_reset@cm-close-fd-no-exec.html [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-atsm-2/igt@xe_exec_reset@cm-close-fd-no-exec.html * igt@xe_exec_threads@threads-mixed-shared-vm-basic: - bat-dg2-oem2: [DMESG-WARN][31] ([Intel XE#3230]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-dg2-oem2/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-dg2-oem2/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html * igt@xe_live_ktest@xe_bo: - bat-adlp-vf: [SKIP][33] ([Intel XE#1192]) -> [PASS][34] +2 other tests pass [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html - bat-pvc-2: [SKIP][35] ([Intel XE#1192]) -> [PASS][36] +2 other tests pass [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-pvc-2/igt@xe_live_ktest@xe_bo.html [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-pvc-2/igt@xe_live_ktest@xe_bo.html * igt@xe_live_ktest@xe_migrate: - bat-lnl-2: [SKIP][37] ([Intel XE#1192]) -> [PASS][38] +2 other tests pass [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-lnl-2/igt@xe_live_ktest@xe_migrate.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-lnl-2/igt@xe_live_ktest@xe_migrate.html - bat-atsm-2: [SKIP][39] ([Intel XE#1192]) -> [PASS][40] +2 other tests pass [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/bat-atsm-2/igt@xe_live_ktest@xe_migrate.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/bat-atsm-2/igt@xe_live_ktest@xe_migrate.html [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192 [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229 [Intel XE#3230]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3230 Build changes ------------- * IGT: IGT_8086 -> IGTPW_11987 * Linux: xe-2132-263b21a91964ddc599f4f85cf3511b0aafd2028e -> xe-2133-3ec61d11c7429a65dcc3ac46b9e845f13891a306 IGTPW_11987: 690bba0c6a9a345ec062cba6ba7b6e1e4f71f6b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git IGT_8086: 18939acec2446c6644644186b090d16e366af8bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-2132-263b21a91964ddc599f4f85cf3511b0aafd2028e: 263b21a91964ddc599f4f85cf3511b0aafd2028e xe-2133-3ec61d11c7429a65dcc3ac46b9e845f13891a306: 3ec61d11c7429a65dcc3ac46b9e845f13891a306 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/index.html [-- Attachment #2: Type: text/html, Size: 10659 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ CI.xeFULL: failure for tests/intel/oa: Tests for OA syncs (rev4) 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit ` (3 preceding siblings ...) 2024-10-25 22:28 ` ✓ CI.xeBAT: " Patchwork @ 2024-10-27 12:56 ` Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2024-10-27 12:56 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 70485 bytes --] == Series Details == Series: tests/intel/oa: Tests for OA syncs (rev4) URL : https://patchwork.freedesktop.org/series/137482/ State : failure == Summary == CI Bug Log - changes from XEIGT_8086_full -> XEIGTPW_11987_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_11987_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_11987_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_11987_full: ### IGT changes ### #### Possible regressions #### * igt@kms_vblank@wait-busy: - shard-dg2-set2: [PASS][1] -> [FAIL][2] +1 other test fail [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-463/igt@kms_vblank@wait-busy.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_vblank@wait-busy.html * igt@xe_exec_balancer@many-cm-parallel-basic: - shard-dg2-set2: NOTRUN -> [DMESG-WARN][3] [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_exec_balancer@many-cm-parallel-basic.html * igt@xe_exec_fault_mode@many-execqueues-invalid-userptr-fault: - shard-bmg: [PASS][4] -> [DMESG-WARN][5] +6 other tests dmesg-warn [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-invalid-userptr-fault.html [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-invalid-userptr-fault.html * igt@xe_exec_fault_mode@many-invalid-fault: - shard-lnl: [PASS][6] -> [DMESG-WARN][7] +7 other tests dmesg-warn [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-1/igt@xe_exec_fault_mode@many-invalid-fault.html [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-2/igt@xe_exec_fault_mode@many-invalid-fault.html * igt@xe_exec_fault_mode@many-userptr-invalidate-race: - shard-lnl: [PASS][8] -> [FAIL][9] +2 other tests fail [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-3/igt@xe_exec_fault_mode@many-userptr-invalidate-race.html [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-4/igt@xe_exec_fault_mode@many-userptr-invalidate-race.html * igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm: - shard-bmg: [PASS][10] -> [FAIL][11] +4 other tests fail [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-6/igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm.html [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_exec_fault_mode@many-userptr-invalidate-race-imm.html * {igt@xe_oa@syncs-ufence-cfg@rcs-0} (NEW): - shard-lnl: NOTRUN -> [DMESG-WARN][12] +3 other tests dmesg-warn [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@xe_oa@syncs-ufence-cfg@rcs-0.html * {igt@xe_oa@syncs-ufence-none@rcs-0} (NEW): - shard-bmg: NOTRUN -> [DMESG-WARN][13] +3 other tests dmesg-warn [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_oa@syncs-ufence-none@rcs-0.html * igt@xe_oa@syncs-userptr-cfg (NEW): - shard-dg2-set2: NOTRUN -> [SKIP][14] +9 other tests skip [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_oa@syncs-userptr-cfg.html #### Warnings #### * igt@xe_evict@evict-beng-mixed-many-threads-large: - shard-bmg: [INCOMPLETE][15] ([Intel XE#1473]) -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-large.html [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-large.html * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race: - shard-bmg: [SKIP][17] ([Intel XE#1130]) -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html * igt@xe_live_ktest@xe_eudebug: - shard-dg2-set2: [SKIP][19] ([Intel XE#455]) -> [SKIP][20] [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@xe_live_ktest@xe_eudebug.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_live_ktest@xe_eudebug.html New tests --------- New tests have been introduced between XEIGT_8086_full and XEIGTPW_11987_full: ### New IGT tests (24) ### * igt@xe_oa@syncs-syncobj-cfg: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.02] s * igt@xe_oa@syncs-syncobj-cfg@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.01, 0.02] s * igt@xe_oa@syncs-syncobj-none: - Statuses : 1 pass(s) - Exec time: [0.01] s * igt@xe_oa@syncs-syncobj-none@rcs-0: - Statuses : 1 pass(s) - Exec time: [0.01] s * igt@xe_oa@syncs-syncobj-wait: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.02] s * igt@xe_oa@syncs-syncobj-wait-cfg: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.03] s * igt@xe_oa@syncs-syncobj-wait-cfg@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.02, 0.03] s * igt@xe_oa@syncs-syncobj-wait@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.01, 0.02] s * igt@xe_oa@syncs-ufence-cfg: - Statuses : 2 dmesg-warn(s) 1 skip(s) - Exec time: [0.0, 0.02] s * igt@xe_oa@syncs-ufence-cfg@rcs-0: - Statuses : 2 dmesg-warn(s) - Exec time: [0.02] s * igt@xe_oa@syncs-ufence-none: - Statuses : 2 dmesg-warn(s) 1 skip(s) - Exec time: [0.0, 0.01] s * igt@xe_oa@syncs-ufence-none@rcs-0: - Statuses : 2 dmesg-warn(s) - Exec time: [0.01] s * igt@xe_oa@syncs-ufence-wait: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.02] s * igt@xe_oa@syncs-ufence-wait-cfg: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.03] s * igt@xe_oa@syncs-ufence-wait-cfg@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.03] s * igt@xe_oa@syncs-ufence-wait@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.01, 0.02] s * igt@xe_oa@syncs-userptr-cfg: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.02] s * igt@xe_oa@syncs-userptr-cfg@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.02] s * igt@xe_oa@syncs-userptr-none: - Statuses : 2 pass(s) - Exec time: [0.01] s * igt@xe_oa@syncs-userptr-none@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.01] s * igt@xe_oa@syncs-userptr-wait: - Statuses : 1 pass(s) 1 skip(s) - Exec time: [0.0, 0.01] s * igt@xe_oa@syncs-userptr-wait-cfg: - Statuses : 2 pass(s) 1 skip(s) - Exec time: [0.0, 0.03] s * igt@xe_oa@syncs-userptr-wait-cfg@rcs-0: - Statuses : 2 pass(s) - Exec time: [0.02, 0.03] s * igt@xe_oa@syncs-userptr-wait@rcs-0: - Statuses : 1 pass(s) - Exec time: [0.01] s Known issues ------------ Here are the changes found in XEIGTPW_11987_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing: - shard-lnl: [PASS][21] -> [FAIL][22] ([Intel XE#1701]) +1 other test fail [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html * igt@kms_big_fb@linear-64bpp-rotate-180: - shard-dg2-set2: [PASS][23] -> [DMESG-WARN][24] ([Intel XE#877]) [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@kms_big_fb@linear-64bpp-rotate-180.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@kms_big_fb@linear-64bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#1124]) [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_bw@linear-tiling-1-displays-2560x1440p: - shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#367]) [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs: - shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#2231]) [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [FAIL][29] ([Intel XE#616]) +8 other tests fail [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc: - shard-dg2-set2: [PASS][30] -> [INCOMPLETE][31] ([Intel XE#1195] / [Intel XE#1727]) +1 other test incomplete [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6: - shard-dg2-set2: [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1195] / [Intel XE#3113]) +1 other test incomplete [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-b-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][34] ([Intel XE#787]) +20 other tests skip [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-b-dp-4.html * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#455] / [Intel XE#787]) +4 other tests skip [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4.html * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k: - shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#373]) [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html * igt@kms_color@ctm-0-75@pipe-a-edp-1: - shard-lnl: [PASS][37] -> [DMESG-WARN][38] ([Intel XE#2929]) +1 other test dmesg-warn [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_color@ctm-0-75@pipe-a-edp-1.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_color@ctm-0-75@pipe-a-edp-1.html * igt@kms_content_protection@srm@pipe-a-dp-2: - shard-bmg: NOTRUN -> [DMESG-FAIL][39] ([Intel XE#3177]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_content_protection@srm@pipe-a-dp-2.html * igt@kms_content_protection@srm@pipe-a-dp-4: - shard-dg2-set2: NOTRUN -> [FAIL][40] ([Intel XE#1178]) [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_content_protection@srm@pipe-a-dp-4.html * igt@kms_fbcon_fbt@psr: - shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#776]) [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_fbcon_fbt@psr.html * igt@kms_feature_discovery@dp-mst: - shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#1137]) [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_feature_discovery@dp-mst.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4: - shard-dg2-set2: [PASS][43] -> [FAIL][44] ([Intel XE#301]) +6 other tests fail [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible: - shard-lnl: [PASS][45] -> [FAIL][46] ([Intel XE#3149] / [Intel XE#886]) [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1: - shard-lnl: [PASS][47] -> [FAIL][48] ([Intel XE#886]) +7 other tests fail [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2: - shard-bmg: [PASS][49] -> [FAIL][50] ([Intel XE#301]) +4 other tests fail [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-dg2-set2: [PASS][51] -> [INCOMPLETE][52] ([Intel XE#1195] / [Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-suspend@c-dp4: - shard-dg2-set2: [PASS][53] -> [INCOMPLETE][54] ([Intel XE#1195] / [Intel XE#2049]) +1 other test incomplete [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_flip@flip-vs-suspend@c-dp4.html [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@kms_flip@flip-vs-suspend@c-dp4.html * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff: - shard-dg2-set2: NOTRUN -> [SKIP][55] ([Intel XE#651]) +3 other tests skip [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff: - shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#653]) +9 other tests skip [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html * igt@kms_invalid_mode@bad-vsync-start: - shard-dg2-set2: [PASS][57] -> [SKIP][58] ([Intel XE#2423] / [i915#2575]) +1 other test skip [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-435/igt@kms_invalid_mode@bad-vsync-start.html [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_invalid_mode@bad-vsync-start.html * igt@kms_plane_lowres@tiling-none: - shard-bmg: [PASS][59] -> [SKIP][60] ([Intel XE#3007]) +1 other test skip [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-5/igt@kms_plane_lowres@tiling-none.html [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@kms_plane_lowres@tiling-none.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4: - shard-dg2-set2: [PASS][61] -> [FAIL][62] ([Intel XE#361]) [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c: - shard-bmg: NOTRUN -> [DMESG-WARN][63] ([Intel XE#3177]) +3 other tests dmesg-warn [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c.html * igt@kms_pm_backlight@fade-with-dpms: - shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#870]) [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_pm_backlight@fade-with-dpms.html * igt@kms_pm_dc@dc5-dpms: - shard-lnl: [PASS][65] -> [FAIL][66] ([Intel XE#718]) +1 other test fail [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-6/igt@kms_pm_dc@dc5-dpms.html [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-6/igt@kms_pm_dc@dc5-dpms.html * igt@kms_pm_dc@dc6-psr: - shard-lnl: [PASS][67] -> [FAIL][68] ([Intel XE#1430]) [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-6/igt@kms_pm_dc@dc6-psr.html * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf: - shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#1489]) +2 other tests skip [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html * igt@kms_psr@fbc-psr2-cursor-blt@edp-1: - shard-lnl: [PASS][70] -> [FAIL][71] ([Intel XE#2948]) +1 other test fail [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_psr@fbc-psr2-cursor-blt@edp-1.html [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-4/igt@kms_psr@fbc-psr2-cursor-blt@edp-1.html * igt@kms_psr@fbc-psr2-primary-render: - shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@kms_psr@fbc-psr2-primary-render.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270: - shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#327]) [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1: - shard-lnl: [PASS][74] -> [FAIL][75] ([Intel XE#899]) +1 other test fail [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html * igt@kms_vrr@cmrr@pipe-a-edp-1: - shard-lnl: [PASS][76] -> [FAIL][77] ([Intel XE#2159]) +1 other test fail [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html * igt@kms_vrr@flip-basic-fastset: - shard-lnl: [PASS][78] -> [FAIL][79] ([Intel XE#2443]) +1 other test fail [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-3/igt@kms_vrr@flip-basic-fastset.html [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_vrr@flip-basic-fastset.html * igt@kms_writeback@writeback-check-output: - shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#756]) [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@kms_writeback@writeback-check-output.html * igt@xe_compute@ccs-mode-basic: - shard-dg2-set2: NOTRUN -> [FAIL][81] ([Intel XE#1050]) [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@xe_compute@ccs-mode-basic.html * igt@xe_copy_basic@mem-copy-linear-0x3fff: - shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#1123]) [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0x3fff.html * igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue: - shard-lnl: [PASS][83] -> [FAIL][84] ([Intel XE#2667]) [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-7/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-1/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html * igt@xe_eudebug_online@interrupt-other-debuggable: - shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#2905]) +2 other tests skip [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@xe_eudebug_online@interrupt-other-debuggable.html * igt@xe_evict@evict-beng-large-multi-vm-cm: - shard-dg2-set2: [PASS][86] -> [FAIL][87] ([Intel XE#1600]) [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@xe_evict@evict-beng-large-multi-vm-cm.html [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html * igt@xe_evict@evict-mixed-threads-large: - shard-bmg: [PASS][88] -> [INCOMPLETE][89] ([Intel XE#1473]) [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-2/igt@xe_evict@evict-mixed-threads-large.html [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-5/igt@xe_evict@evict-mixed-threads-large.html * igt@xe_exec_fault_mode@twice-invalid-fault: - shard-lnl: [PASS][90] -> [DMESG-WARN][91] ([Intel XE#3230]) [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-4/igt@xe_exec_fault_mode@twice-invalid-fault.html [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-7/igt@xe_exec_fault_mode@twice-invalid-fault.html * igt@xe_exec_fault_mode@twice-userptr-rebind-imm: - shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#288]) +5 other tests skip [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html * igt@xe_exec_mix_modes@exec-simple-batch-store-lr: - shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#2360]) [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html * igt@xe_exec_reset@cm-close-fd-no-exec: - shard-dg2-set2: [PASS][94] -> [DMESG-WARN][95] ([Intel XE#3230]) [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_exec_reset@cm-close-fd-no-exec.html [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@xe_exec_reset@cm-close-fd-no-exec.html * igt@xe_exec_threads@threads-hang-shared-vm-rebind: - shard-dg2-set2: [PASS][96] -> [DMESG-WARN][97] ([Intel XE#358]) +2 other tests dmesg-warn [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-466/igt@xe_exec_threads@threads-hang-shared-vm-rebind.html [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@xe_exec_threads@threads-hang-shared-vm-rebind.html * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit: - shard-dg2-set2: NOTRUN -> [SKIP][98] ([Intel XE#2229]) [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p: - shard-dg2-set2: NOTRUN -> [FAIL][99] ([Intel XE#1173]) [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html * igt@xe_pm@s4-vm-bind-unbind-all: - shard-lnl: [PASS][100] -> [ABORT][101] ([Intel XE#1794]) [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-1/igt@xe_pm@s4-vm-bind-unbind-all.html [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html * igt@xe_pm_residency@toggle-gt-c6: - shard-lnl: [PASS][102] -> [FAIL][103] ([Intel XE#958]) [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-1/igt@xe_pm_residency@toggle-gt-c6.html [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-8/igt@xe_pm_residency@toggle-gt-c6.html * igt@xe_query@multigpu-query-config: - shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#944]) [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@xe_query@multigpu-query-config.html * igt@xe_vm@large-userptr-split-misaligned-binds-536870912: - shard-bmg: [PASS][105] -> [SKIP][106] ([Intel XE#1130]) +2 other tests skip [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_vm@large-userptr-split-misaligned-binds-536870912.html [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@xe_vm@large-userptr-split-misaligned-binds-536870912.html - shard-dg2-set2: [PASS][107] -> [SKIP][108] ([Intel XE#1130]) +1 other test skip [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@xe_vm@large-userptr-split-misaligned-binds-536870912.html [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@xe_vm@large-userptr-split-misaligned-binds-536870912.html #### Possible fixes #### * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear: - shard-lnl: [FAIL][109] ([Intel XE#911]) -> [PASS][110] +3 other tests pass [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html * igt@kms_atomic_transition@modeset-transition-nonblocking: - shard-lnl: [FAIL][111] ([Intel XE#1701]) -> [PASS][112] +1 other test pass [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking.html [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-4/igt@kms_atomic_transition@modeset-transition-nonblocking.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6: - shard-dg2-set2: [FAIL][113] ([Intel XE#1426]) -> [PASS][114] +1 other test pass [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-6.html * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0: - shard-bmg: [SKIP][115] ([Intel XE#2231]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs: - shard-dg2-set2: [INCOMPLETE][117] ([Intel XE#1195] / [Intel XE#1727]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4: - shard-dg2-set2: [INCOMPLETE][119] ([Intel XE#1195] / [Intel XE#3113]) -> [PASS][120] [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size: - shard-bmg: [DMESG-WARN][121] ([Intel XE#877]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-lnl: [FAIL][123] ([Intel XE#1541]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt@kms_fb_coherency@memset-crc: - shard-dg2-set2: [SKIP][125] ([Intel XE#2351] / [Intel XE#2890]) -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_fb_coherency@memset-crc.html [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_fb_coherency@memset-crc.html * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3: - shard-bmg: [FAIL][127] ([Intel XE#2882]) -> [PASS][128] +1 other test pass [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3.html [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-dp2-hdmi-a3.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3: - shard-bmg: [FAIL][129] ([Intel XE#301]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3.html [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-dp2-hdmi-a3.html * igt@kms_flip@blocking-wf_vblank: - shard-lnl: [FAIL][131] ([Intel XE#886]) -> [PASS][132] +5 other tests pass [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-2/igt@kms_flip@blocking-wf_vblank.html [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-8/igt@kms_flip@blocking-wf_vblank.html * igt@kms_flip@dpms-vs-vblank-race: - shard-lnl: [FAIL][133] ([Intel XE#3097]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-6/igt@kms_flip@dpms-vs-vblank-race.html [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-2/igt@kms_flip@dpms-vs-vblank-race.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6: - shard-dg2-set2: [FAIL][135] ([Intel XE#301]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html * igt@kms_lease@lease-invalid-connector: - shard-dg2-set2: [SKIP][137] ([Intel XE#2423] / [i915#2575]) -> [PASS][138] +14 other tests pass [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_lease@lease-invalid-connector.html [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@kms_lease@lease-invalid-connector.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6: - shard-dg2-set2: [FAIL][139] ([Intel XE#361]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html * igt@kms_pm_dc@dc5-dpms-negative: - shard-bmg: [SKIP][141] ([Intel XE#2231] / [Intel XE#2890]) -> [PASS][142] +5 other tests pass [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_pm_dc@dc5-dpms-negative.html [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_pm_dc@dc5-dpms-negative.html - shard-dg2-set2: [SKIP][143] ([Intel XE#2890]) -> [PASS][144] +6 other tests pass [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_pm_dc@dc5-dpms-negative.html [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_pm_dc@dc5-dpms-negative.html * igt@kms_pm_rpm@universal-planes-dpms: - shard-lnl: [DMESG-WARN][145] ([Intel XE#2042]) -> [PASS][146] [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-5/igt@kms_pm_rpm@universal-planes-dpms.html [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-1/igt@kms_pm_rpm@universal-planes-dpms.html * igt@kms_psr@fbc-psr2-cursor-plane-move: - shard-lnl: [FAIL][147] ([Intel XE#2948]) -> [PASS][148] +1 other test pass [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-3/igt@kms_psr@fbc-psr2-cursor-plane-move.html [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-6/igt@kms_psr@fbc-psr2-cursor-plane-move.html * igt@kms_sequence@get-busy: - shard-bmg: [SKIP][149] ([Intel XE#3007]) -> [PASS][150] +14 other tests pass [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_sequence@get-busy.html [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-5/igt@kms_sequence@get-busy.html * igt@kms_setmode@basic@pipe-b-edp-1: - shard-lnl: [FAIL][151] ([Intel XE#2883]) -> [PASS][152] +2 other tests pass [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_setmode@basic@pipe-b-edp-1.html * igt@kms_vrr@flip-basic: - shard-lnl: [FAIL][153] ([Intel XE#2443]) -> [PASS][154] +3 other tests pass [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-8/igt@kms_vrr@flip-basic.html [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-3/igt@kms_vrr@flip-basic.html * igt@testdisplay: - shard-dg2-set2: [SKIP][155] ([Intel XE#2423]) -> [PASS][156] [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@testdisplay.html [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@testdisplay.html * igt@xe_evict@evict-beng-mixed-many-threads-small: - shard-dg2-set2: [TIMEOUT][157] ([Intel XE#1473] / [Intel XE#402]) -> [PASS][158] [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@xe_evict@evict-beng-mixed-many-threads-small.html [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@xe_evict@evict-beng-mixed-many-threads-small.html * igt@xe_exec_basic@many-execqueues-bindexecqueue-userptr: - shard-dg2-set2: [SKIP][159] ([Intel XE#1130]) -> [PASS][160] +17 other tests pass [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_exec_basic@many-execqueues-bindexecqueue-userptr.html [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@xe_exec_basic@many-execqueues-bindexecqueue-userptr.html * igt@xe_exec_compute_mode@many-bindexecqueue-userptr: - shard-dg2-set2: [DMESG-WARN][161] -> [PASS][162] +5 other tests pass [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-434/igt@xe_exec_compute_mode@many-bindexecqueue-userptr.html [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_exec_compute_mode@many-bindexecqueue-userptr.html * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race: - shard-lnl: [FAIL][163] -> [PASS][164] +3 other tests pass [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-5/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-1/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race.html * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm: - shard-lnl: [FAIL][165] ([Intel XE#3160]) -> [PASS][166] [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-6/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-8/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html * igt@xe_exec_fault_mode@once-invalid-fault: - shard-lnl: [DMESG-WARN][167] -> [PASS][168] +5 other tests pass [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-5/igt@xe_exec_fault_mode@once-invalid-fault.html [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-5/igt@xe_exec_fault_mode@once-invalid-fault.html * igt@xe_exec_reset@parallel-close-fd: - shard-bmg: [FAIL][169] ([Intel XE#1081]) -> [PASS][170] [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-7/igt@xe_exec_reset@parallel-close-fd.html [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_exec_reset@parallel-close-fd.html - shard-dg2-set2: [FAIL][171] ([Intel XE#1081]) -> [PASS][172] [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-435/igt@xe_exec_reset@parallel-close-fd.html [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_exec_reset@parallel-close-fd.html * igt@xe_exec_threads@threads-hang-fd-rebind: - shard-dg2-set2: [DMESG-WARN][173] ([Intel XE#358]) -> [PASS][174] [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-466/igt@xe_exec_threads@threads-hang-fd-rebind.html [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@xe_exec_threads@threads-hang-fd-rebind.html * igt@xe_exec_threads@threads-hang-fd-userptr-rebind: - shard-bmg: [DMESG-WARN][175] -> [PASS][176] +4 other tests pass [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-7/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html * igt@xe_exec_threads@threads-mixed-fd-basic: - shard-bmg: [DMESG-WARN][177] ([Intel XE#3230]) -> [PASS][178] [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-4/igt@xe_exec_threads@threads-mixed-fd-basic.html [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@xe_exec_threads@threads-mixed-fd-basic.html * igt@xe_intel_bb@lot-of-buffers: - shard-bmg: [SKIP][179] ([Intel XE#1130]) -> [PASS][180] +27 other tests pass [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_intel_bb@lot-of-buffers.html [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@xe_intel_bb@lot-of-buffers.html * igt@xe_live_ktest@xe_migrate: - shard-dg2-set2: [SKIP][181] ([Intel XE#1192]) -> [PASS][182] [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@xe_live_ktest@xe_migrate.html [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_live_ktest@xe_migrate.html * igt@xe_oa@oa-exponents@rcs-0: - shard-lnl: [FAIL][183] ([Intel XE#2976]) -> [PASS][184] [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-7/igt@xe_oa@oa-exponents@rcs-0.html [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-1/igt@xe_oa@oa-exponents@rcs-0.html * igt@xe_pm@d3hot-multiple-execs: - shard-lnl: [DMESG-WARN][185] ([Intel XE#3184]) -> [PASS][186] [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-4/igt@xe_pm@d3hot-multiple-execs.html [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-1/igt@xe_pm@d3hot-multiple-execs.html #### Warnings #### * igt@kms_big_fb@4-tiled-16bpp-rotate-270: - shard-bmg: [SKIP][187] ([Intel XE#2231]) -> [SKIP][188] ([Intel XE#2327]) [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-5/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html - shard-dg2-set2: [SKIP][189] ([Intel XE#2351] / [Intel XE#2890]) -> [SKIP][190] ([Intel XE#316]) [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-90: - shard-bmg: [SKIP][191] ([Intel XE#1124]) -> [SKIP][192] ([Intel XE#2231] / [Intel XE#2890]) [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html - shard-dg2-set2: [SKIP][193] ([Intel XE#1124]) -> [SKIP][194] ([Intel XE#2890]) [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0: - shard-bmg: [SKIP][195] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][196] ([Intel XE#1124]) +1 other test skip [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html - shard-dg2-set2: [SKIP][197] ([Intel XE#2890]) -> [SKIP][198] ([Intel XE#1124]) +1 other test skip [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs: - shard-bmg: [SKIP][199] ([Intel XE#2231]) -> [SKIP][200] ([Intel XE#2887]) [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs.html * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs: - shard-bmg: [SKIP][201] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][202] ([Intel XE#2887]) [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html - shard-dg2-set2: [SKIP][203] ([Intel XE#2890]) -> [SKIP][204] ([Intel XE#455] / [Intel XE#787]) [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs: - shard-dg2-set2: [SKIP][205] ([Intel XE#2907]) -> [SKIP][206] ([Intel XE#2890]) [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-433/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html * igt@kms_chamelium_color@ctm-green-to-red: - shard-bmg: [SKIP][207] ([Intel XE#3007]) -> [SKIP][208] ([Intel XE#2325]) +1 other test skip [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_chamelium_color@ctm-green-to-red.html [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_chamelium_color@ctm-green-to-red.html * igt@kms_chamelium_color@gamma: - shard-dg2-set2: [SKIP][209] ([Intel XE#2423] / [i915#2575]) -> [SKIP][210] ([Intel XE#306]) +1 other test skip [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_chamelium_color@gamma.html [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@kms_chamelium_color@gamma.html * igt@kms_chamelium_hpd@dp-hpd: - shard-bmg: [SKIP][211] ([Intel XE#3007]) -> [SKIP][212] ([Intel XE#2252]) [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd.html [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd.html - shard-dg2-set2: [SKIP][213] ([Intel XE#2423] / [i915#2575]) -> [SKIP][214] ([Intel XE#373]) [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_chamelium_hpd@dp-hpd.html [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_chamelium_hpd@dp-hpd.html * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend: - shard-bmg: [SKIP][215] ([Intel XE#2252]) -> [SKIP][216] ([Intel XE#3007]) [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html - shard-dg2-set2: [SKIP][217] ([Intel XE#373]) -> [SKIP][218] ([Intel XE#2423] / [i915#2575]) [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-464/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html * igt@kms_content_protection@srm: - shard-bmg: [SKIP][219] ([Intel XE#3007]) -> [DMESG-FAIL][220] ([Intel XE#3177]) [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_content_protection@srm.html [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_content_protection@srm.html - shard-dg2-set2: [SKIP][221] ([Intel XE#2423] / [i915#2575]) -> [FAIL][222] ([Intel XE#1178]) [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_content_protection@srm.html [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@kms_content_protection@srm.html * igt@kms_cursor_crc@cursor-random-64x21: - shard-bmg: [SKIP][223] ([Intel XE#3007]) -> [SKIP][224] ([Intel XE#2320]) [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_cursor_crc@cursor-random-64x21.html [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@kms_cursor_crc@cursor-random-64x21.html * igt@kms_cursor_crc@cursor-sliding-512x170: - shard-dg2-set2: [SKIP][225] ([Intel XE#2423] / [i915#2575]) -> [SKIP][226] ([Intel XE#308]) [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_cursor_crc@cursor-sliding-512x170.html [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_cursor_crc@cursor-sliding-512x170.html - shard-bmg: [SKIP][227] ([Intel XE#3007]) -> [SKIP][228] ([Intel XE#2321]) [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-512x170.html [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-512x170.html * igt@kms_flip@bo-too-big-interruptible@a-edp1: - shard-lnl: [INCOMPLETE][229] ([Intel XE#1504]) -> [TIMEOUT][230] ([Intel XE#1504]) +1 other test timeout [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-lnl-5/igt@kms_flip@bo-too-big-interruptible@a-edp1.html [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-lnl-4/igt@kms_flip@bo-too-big-interruptible@a-edp1.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt: - shard-bmg: [SKIP][231] ([Intel XE#2231]) -> [SKIP][232] ([Intel XE#2311]) +1 other test skip [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html - shard-dg2-set2: [SKIP][233] ([Intel XE#2351] / [Intel XE#2890]) -> [SKIP][234] ([Intel XE#651]) [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-bmg: [SKIP][235] ([Intel XE#2231] / [Intel XE#2890]) -> [FAIL][236] ([Intel XE#2333]) [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary: - shard-dg2-set2: [SKIP][237] ([Intel XE#2890]) -> [SKIP][238] ([Intel XE#651]) +1 other test skip [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html - shard-bmg: [SKIP][239] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][240] ([Intel XE#2311]) [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt: - shard-bmg: [SKIP][241] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][242] ([Intel XE#2313]) +4 other tests skip [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html - shard-dg2-set2: [SKIP][243] ([Intel XE#2890]) -> [SKIP][244] ([Intel XE#653]) +5 other tests skip [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-bmg: [SKIP][245] ([Intel XE#2231]) -> [SKIP][246] ([Intel XE#2313]) [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75: - shard-bmg: [SKIP][247] ([Intel XE#3007]) -> [DMESG-WARN][248] ([Intel XE#2566] / [Intel XE#3177]) [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf: - shard-bmg: [SKIP][249] ([Intel XE#2231]) -> [SKIP][250] ([Intel XE#1489]) [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html - shard-dg2-set2: [SKIP][251] ([Intel XE#2890]) -> [SKIP][252] ([Intel XE#1489]) [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html * igt@kms_psr@fbc-psr-no-drrs: - shard-dg2-set2: [SKIP][253] ([Intel XE#2351] / [Intel XE#2890]) -> [SKIP][254] ([Intel XE#2850] / [Intel XE#929]) [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_psr@fbc-psr-no-drrs.html [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@kms_psr@fbc-psr-no-drrs.html * igt@kms_psr@pr-sprite-blt: - shard-dg2-set2: [SKIP][255] ([Intel XE#2890]) -> [SKIP][256] ([Intel XE#2850] / [Intel XE#929]) [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_psr@pr-sprite-blt.html [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@kms_psr@pr-sprite-blt.html - shard-bmg: [SKIP][257] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][258] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_psr@pr-sprite-blt.html [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_psr@pr-sprite-blt.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-dg2-set2: [SKIP][259] ([Intel XE#1500]) -> [SKIP][260] ([Intel XE#362]) [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-bmg: [SKIP][261] ([Intel XE#3007]) -> [SKIP][262] ([Intel XE#756]) [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-dg2-set2: [SKIP][263] ([Intel XE#2423] / [i915#2575]) -> [SKIP][264] ([Intel XE#756]) [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@kms_writeback@writeback-check-output-xrgb2101010.html [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@xe_copy_basic@mem-set-linear-0xfd: - shard-dg2-set2: [SKIP][265] ([Intel XE#1130]) -> [SKIP][266] ([Intel XE#1126]) [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_copy_basic@mem-set-linear-0xfd.html [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0xfd.html * igt@xe_eudebug@basic-vm-bind-vm-destroy: - shard-bmg: [SKIP][267] ([Intel XE#1130]) -> [SKIP][268] ([Intel XE#2905]) [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_eudebug@basic-vm-bind-vm-destroy.html [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-3/igt@xe_eudebug@basic-vm-bind-vm-destroy.html - shard-dg2-set2: [SKIP][269] ([Intel XE#1130]) -> [SKIP][270] ([Intel XE#2905]) [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_eudebug@basic-vm-bind-vm-destroy.html [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-434/igt@xe_eudebug@basic-vm-bind-vm-destroy.html * igt@xe_evict@evict-beng-mixed-many-threads-large: - shard-dg2-set2: [TIMEOUT][271] ([Intel XE#1473]) -> [INCOMPLETE][272] ([Intel XE#1195] / [Intel XE#1473]) [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_evict@evict-beng-mixed-many-threads-large.html [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-433/igt@xe_evict@evict-beng-mixed-many-threads-large.html * igt@xe_evict@evict-large-multi-vm-cm: - shard-bmg: [DMESG-FAIL][273] -> [FAIL][274] ([Intel XE#2364]) [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-3/igt@xe_evict@evict-large-multi-vm-cm.html [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@xe_evict@evict-large-multi-vm-cm.html * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap: - shard-bmg: [SKIP][275] ([Intel XE#1130]) -> [SKIP][276] ([Intel XE#2322]) [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race-prefetch: - shard-bmg: [FAIL][277] -> [SKIP][278] ([Intel XE#1130]) [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-4/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race-prefetch.html [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-4/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race-prefetch.html * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-rebind-imm: - shard-dg2-set2: [SKIP][279] ([Intel XE#1130]) -> [SKIP][280] ([Intel XE#288]) +4 other tests skip [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-rebind-imm.html [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-464/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-rebind-imm.html * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-imm: - shard-dg2-set2: [SKIP][281] ([Intel XE#288]) -> [SKIP][282] ([Intel XE#1130]) +1 other test skip [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-435/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-imm.html [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-466/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-imm.html * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence: - shard-dg2-set2: [SKIP][283] ([Intel XE#1130]) -> [SKIP][284] ([Intel XE#2360]) [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html * igt@xe_live_ktest@xe_mocs: - shard-dg2-set2: [FAIL][285] ([Intel XE#1999]) -> [SKIP][286] ([Intel XE#1192]) [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-464/igt@xe_live_ktest@xe_mocs.html [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-436/igt@xe_live_ktest@xe_mocs.html * igt@xe_oa@invalid-oa-format-id: - shard-dg2-set2: [SKIP][287] ([Intel XE#1130]) -> [SKIP][288] ([Intel XE#2541]) +1 other test skip [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_oa@invalid-oa-format-id.html [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-435/igt@xe_oa@invalid-oa-format-id.html * igt@xe_peer2peer@write: - shard-bmg: [SKIP][289] ([Intel XE#2557]) -> [SKIP][290] ([Intel XE#2427]) [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-bmg-8/igt@xe_peer2peer@write.html [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-bmg-7/igt@xe_peer2peer@write.html - shard-dg2-set2: [SKIP][291] ([Intel XE#1061]) -> [FAIL][292] ([Intel XE#1173]) [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8086/shard-dg2-436/igt@xe_peer2peer@write.html [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/shard-dg2-463/igt@xe_peer2peer@write.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1050 [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061 [Intel XE#1081]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1081 [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123 [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126 [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130 [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137 [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173 [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178 [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192 [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195 [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426 [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430 [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500 [Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504 [Intel XE#1541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1541 [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600 [Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701 [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727 [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794 [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999 [Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042 [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049 [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159 [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229 [Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231 [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234 [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252 [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311 [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313 [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320 [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321 [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322 [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325 [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327 [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333 [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351 [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360 [Intel XE#2364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2364 [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423 [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427 [Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443 [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541 [Intel XE#2557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2557 [Intel XE#2566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2566 [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597 [Intel XE#2667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2667 [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882 [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883 [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887 [Intel XE#2890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2890 [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905 [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907 [Intel XE#2929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2929 [Intel XE#2948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2948 [Intel XE#2976]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2976 [Intel XE#3007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3007 [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301 [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 [Intel XE#3097]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3097 [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113 [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#3160]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3160 [Intel XE#3177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3177 [Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184 [Intel XE#3230]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3230 [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327 [Intel XE#358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/358 [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361 [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362 [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718 [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756 [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870 [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877 [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886 [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899 [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958 [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 Build changes ------------- * IGT: IGT_8086 -> IGTPW_11987 * Linux: xe-2132-263b21a91964ddc599f4f85cf3511b0aafd2028e -> xe-2133-3ec61d11c7429a65dcc3ac46b9e845f13891a306 IGTPW_11987: 690bba0c6a9a345ec062cba6ba7b6e1e4f71f6b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git IGT_8086: 18939acec2446c6644644186b090d16e366af8bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-2132-263b21a91964ddc599f4f85cf3511b0aafd2028e: 263b21a91964ddc599f4f85cf3511b0aafd2028e xe-2133-3ec61d11c7429a65dcc3ac46b9e845f13891a306: 3ec61d11c7429a65dcc3ac46b9e845f13891a306 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_11987/index.html [-- Attachment #2: Type: text/html, Size: 84483 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH i-g-t v5 0/2] tests/intel/oa: Tests for OA syncs @ 2024-10-30 2:53 Ashutosh Dixit 2024-10-30 2:53 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: " Ashutosh Dixit 0 siblings, 1 reply; 14+ messages in thread From: Ashutosh Dixit @ 2024-10-30 2:53 UTC (permalink / raw) To: igt-dev Ashutosh Dixit (2): drm-uapi/xe: Sync with OA syncs uapi update tests/intel/xe_oa: Tests for OA syncs include/drm-uapi/xe_drm.h | 23 +++- lib/xe/xe_oa.c | 6 +- lib/xe/xe_oa.h | 2 + tests/intel/xe_oa.c | 282 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 308 insertions(+), 5 deletions(-) -- 2.41.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-30 2:53 [PATCH i-g-t v5 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit @ 2024-10-30 2:53 ` Ashutosh Dixit 2024-10-30 12:54 ` Kamil Konieczny 0 siblings, 1 reply; 14+ messages in thread From: Ashutosh Dixit @ 2024-10-30 2:53 UTC (permalink / raw) To: igt-dev Verify OA syncs signal correctly in open and change config code paths. Verify with different types of sync objects as well as by both waiting and skipping the wait for syncs to signal. v2: Significantly expand oa syncs testing as described above v3: Always wait in userptr/ufence cases to avoid -EFAULT errors Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- lib/xe/xe_oa.c | 6 +- lib/xe/xe_oa.h | 2 + tests/intel/xe_oa.c | 282 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 287 insertions(+), 3 deletions(-) diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c index 4fdd0b8c95..c168669c5d 100644 --- a/lib/xe/xe_oa.c +++ b/lib/xe/xe_oa.c @@ -1025,8 +1025,8 @@ const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, return "unknown"; } -static void xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, - struct drm_xe_ext_set_property *extn) +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, + struct drm_xe_ext_set_property *extn) { __u64 *prop = from_user_pointer(properties->properties_ptr); struct drm_xe_ext_set_property *ext = extn; @@ -1063,7 +1063,7 @@ int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg) struct intel_xe_oa_open_prop *oprop = (struct intel_xe_oa_open_prop *)arg; igt_assert_lte(oprop->num_properties, XE_OA_MAX_SET_PROPERTIES); - xe_oa_prop_to_ext(oprop, ext); + intel_xe_oa_prop_to_ext(oprop, ext); } return igt_ioctl(fd, DRM_IOCTL_XE_OBSERVATION, &p); diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h index 962f9dddcc..7d3d074560 100644 --- a/lib/xe/xe_oa.h +++ b/lib/xe/xe_oa.h @@ -398,6 +398,8 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, const struct intel_xe_perf_record_header *record); +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, + struct drm_xe_ext_set_property *extn); int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg); void intel_xe_perf_ioctl_err(int fd, enum drm_xe_observation_op op, void *arg, int err); diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c index 92f5828c79..33e978a488 100644 --- a/tests/intel/xe_oa.c +++ b/tests/intel/xe_oa.c @@ -22,6 +22,7 @@ #include "drm.h" #include "igt.h" #include "igt_device.h" +#include "igt_syncobj.h" #include "igt_sysfs.h" #include "xe/xe_ioctl.h" #include "xe/xe_query.h" @@ -4463,6 +4464,255 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open, __perf_close(stream_fd); } + +/* Return alternative config_id if available, else just return config_id */ +static void find_alt_oa_config(u32 config_id, u32 *alt_config_id) +{ + struct dirent *entry; + int metrics_fd, dir_fd; + DIR *metrics_dir; + bool ret; + + metrics_fd = openat(sysfs, "metrics", O_DIRECTORY); + igt_assert_lte(0, metrics_fd); + + metrics_dir = fdopendir(metrics_fd); + igt_assert(metrics_dir); + + while ((entry = readdir(metrics_dir))) { + if (entry->d_type != DT_DIR) + continue; + + dir_fd = openat(metrics_fd, entry->d_name, O_RDONLY); + ret = __igt_sysfs_get_u32(dir_fd, "id", alt_config_id); + close(dir_fd); + if (!ret) + continue; + + if (config_id != *alt_config_id) + goto exit; + } + + *alt_config_id = config_id; +exit: + closedir(metrics_dir); +} + +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + +#define WAIT (0x1 << 0) +#define CONFIG (0x1 << 1) + +enum oa_sync_type { + OA_SYNC_TYPE_SYNCOBJ, + OA_SYNC_TYPE_USERPTR, + OA_SYNC_TYPE_UFENCE, +}; + +struct oa_sync { + enum oa_sync_type sync_type; + u32 syncobj; + u32 vm; + u32 bo; + size_t bo_size; + struct { + uint64_t vm_sync; + uint64_t pad; + uint64_t oa_sync; + } *data; +}; + +static void +oa_sync_init(enum oa_sync_type sync_type, const struct drm_xe_engine_class_instance *hwe, + struct oa_sync *osync, struct drm_xe_sync *sync) +{ + uint64_t addr = 0x1a0000; + + osync->sync_type = sync_type; + sync->flags = DRM_XE_SYNC_FLAG_SIGNAL; + + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + osync->syncobj = syncobj_create(drm_fd, 0); + sync->handle = osync->syncobj; + sync->type = DRM_XE_SYNC_TYPE_SYNCOBJ; + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + sync->type = DRM_XE_SYNC_TYPE_USER_FENCE; + sync->timeline_value = USER_FENCE_VALUE; + + osync->vm = xe_vm_create(drm_fd, 0, 0); + osync->bo_size = xe_bb_size(drm_fd, sizeof(*osync->data)); + if (osync->sync_type == OA_SYNC_TYPE_USERPTR) { + osync->data = aligned_alloc(xe_get_default_alignment(drm_fd), + osync->bo_size); + igt_assert(osync->data); + } else { + osync->bo = xe_bo_create(drm_fd, osync->vm, osync->bo_size, + vram_if_possible(drm_fd, hwe->gt_id), + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); + osync->data = xe_bo_map(drm_fd, osync->bo, osync->bo_size); + } + memset(osync->data, 0, osync->bo_size); + + sync->addr = to_user_pointer(&osync->data[0].vm_sync); + if (osync->bo) + xe_vm_bind_async(drm_fd, osync->vm, 0, osync->bo, 0, + addr, osync->bo_size, sync, 1); + else + xe_vm_bind_userptr_async(drm_fd, osync->vm, 0, + to_user_pointer(osync->data), + addr, osync->bo_size, sync, 1); + xe_wait_ufence(drm_fd, &osync->data[0].vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + + sync->addr = to_user_pointer(&osync->data[0].oa_sync); + break; + default: + igt_assert(false); + } +} + +static void oa_sync_wait(struct oa_sync *osync) +{ + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + igt_assert(syncobj_wait(drm_fd, &osync->syncobj, 1, INT64_MAX, 0, NULL)); + syncobj_reset(drm_fd, &osync->syncobj, 1); + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + xe_wait_ufence(drm_fd, &osync->data[0].oa_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + osync->data[0].oa_sync = 0; + break; + default: + igt_assert(false); + } +} + +static void oa_sync_free(struct oa_sync *osync) +{ + switch (osync->sync_type) { + case OA_SYNC_TYPE_SYNCOBJ: + syncobj_destroy(drm_fd, osync->syncobj); + break; + case OA_SYNC_TYPE_USERPTR: + case OA_SYNC_TYPE_UFENCE: + if (osync->bo) { + munmap(osync->data, osync->bo_size); + gem_close(drm_fd, osync->bo); + } else { + free(osync->data); + } + xe_vm_destroy(drm_fd, osync->vm); + break; + default: + igt_assert(false); + } +} + +/** + * SUBTEST: syncs-%s-%s + * + * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and + * reconfig flags) signal correctly in open and reconfig code + * paths + * + * arg[1]: + * + * @syncobj: sync type syncobj + * + * arg[2]: + * + * @wait-cfg: Exercise reconfig path and wait for syncs to signal + * @wait: Don't exercise reconfig path and wait for syncs to signal + * @cfg: Exercise reconfig path but don't wait for syncs to signal + * @none: Don't exercise reconfig path and don't wait for syncs to signal + */ + +/** + * SUBTEST: syncs-%s-%s + * + * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and + * reconfig flags) signal correctly in open and reconfig code + * paths + * + * arg[1]: + * + * @userptr: sync type userptr + * @ufence: sync type ufence + * + * arg[2]: + * + * @wait-cfg: Exercise reconfig path and wait for syncs to signal + * @wait: Don't exercise reconfig path and wait for syncs to signal + */ +static void test_syncs(const struct drm_xe_engine_class_instance *hwe, + enum oa_sync_type sync_type, int flags) +{ + struct drm_xe_ext_set_property extn[XE_OA_MAX_SET_PROPERTIES] = {}; + struct intel_xe_perf_metric_set *test_set = metric_set(hwe); + struct drm_xe_sync sync = {}; + struct oa_sync osync = {}; + uint64_t open_properties[] = { + DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0, + DRM_XE_OA_PROPERTY_SAMPLE_OA, true, + DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set, + DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format), + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), + }; + struct intel_xe_oa_open_prop open_param = { + .num_properties = ARRAY_SIZE(open_properties) / 2, + .properties_ptr = to_user_pointer(open_properties), + }; + uint64_t config_properties[] = { + DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0, /* Filled later */ + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), + }; + struct intel_xe_oa_open_prop config_param = { + .num_properties = ARRAY_SIZE(config_properties) / 2, + .properties_ptr = to_user_pointer(config_properties), + }; + uint32_t alt_config_id; + int ret; + + /* + * Necessarily wait in userptr/ufence cases, otherwise IGT process can exit + * after calling oa_sync_free, which results in -EFAULT when kernel signals + * the userptr/ufence + */ + if (sync_type == OA_SYNC_TYPE_USERPTR || sync_type == OA_SYNC_TYPE_UFENCE) + flags |= WAIT; + + oa_sync_init(sync_type, hwe, &osync, &sync); + + stream_fd = __perf_open(drm_fd, &open_param, false); + + /* Reset the sync object if we are going to reconfig the stream */ + if (flags & (WAIT | CONFIG)) + oa_sync_wait(&osync); + + if (!(flags & CONFIG)) + goto exit; + + /* Change stream configuration */ + find_alt_oa_config(test_set->perf_oa_metrics_set, &alt_config_id); + + config_properties[1] = alt_config_id; + intel_xe_oa_prop_to_ext(&config_param, extn); + + ret = igt_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_CONFIG, extn); + igt_assert_eq(ret, test_set->perf_oa_metrics_set); + + if (flags & WAIT) + oa_sync_wait(&osync); +exit: + __perf_close(stream_fd); + oa_sync_free(&osync); +} + static const char *xe_engine_class_name(uint32_t engine_class) { switch (engine_class) { @@ -4511,6 +4761,22 @@ static const char *xe_engine_class_name(uint32_t engine_class) igt_main { + const struct sync_section { + const char *name; + enum oa_sync_type sync_type; + unsigned int flags; + } sync_sections[] = { + { "syncobj-wait-cfg", OA_SYNC_TYPE_SYNCOBJ, WAIT | CONFIG}, + { "syncobj-wait", OA_SYNC_TYPE_SYNCOBJ, WAIT }, + { "syncobj-cfg", OA_SYNC_TYPE_SYNCOBJ, CONFIG }, + { "syncobj-none", OA_SYNC_TYPE_SYNCOBJ, 0 }, + /* userptr/ufence cases always set WAIT (see test_syncs) */ + { "userptr-wait-cfg", OA_SYNC_TYPE_USERPTR, WAIT | CONFIG}, + { "userptr-wait", OA_SYNC_TYPE_USERPTR, WAIT }, + { "ufence-wait-cfg", OA_SYNC_TYPE_UFENCE, WAIT | CONFIG}, + { "ufence-wait", OA_SYNC_TYPE_UFENCE, WAIT }, + { NULL }, + }; struct drm_xe_engine_class_instance *hwe = NULL; struct xe_device *xe_dev; @@ -4713,6 +4979,22 @@ igt_main } } + igt_subtest_group { + igt_fixture { + struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd); + struct drm_xe_oa_unit *oau = (struct drm_xe_oa_unit *)&qoa->oa_units[0]; + + igt_require(oau->capabilities & DRM_XE_OA_CAPS_SYNCS); + } + + for (const struct sync_section *s = sync_sections; s->name; s++) { + igt_subtest_with_dynamic_f("syncs-%s", s->name) + __for_one_render_engine(hwe) + test_syncs(hwe, s->sync_type, s->flags); + + } + } + igt_fixture { /* leave sysctl options in their default state... */ write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1); -- 2.41.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-30 2:53 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: " Ashutosh Dixit @ 2024-10-30 12:54 ` Kamil Konieczny 2024-10-31 2:11 ` Dixit, Ashutosh 0 siblings, 1 reply; 14+ messages in thread From: Kamil Konieczny @ 2024-10-30 12:54 UTC (permalink / raw) To: igt-dev; +Cc: Ashutosh Dixit Hi Ashutosh, On 2024-10-29 at 19:53:27 -0700, Ashutosh Dixit wrote: > Verify OA syncs signal correctly in open and change config code > paths. Verify with different types of sync objects as well as by both > waiting and skipping the wait for syncs to signal. > > v2: Significantly expand oa syncs testing as described above > v3: Always wait in userptr/ufence cases to avoid -EFAULT errors > > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > --- > lib/xe/xe_oa.c | 6 +- > lib/xe/xe_oa.h | 2 + > tests/intel/xe_oa.c | 282 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 287 insertions(+), 3 deletions(-) > > diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c > index 4fdd0b8c95..c168669c5d 100644 > --- a/lib/xe/xe_oa.c > +++ b/lib/xe/xe_oa.c > @@ -1025,8 +1025,8 @@ const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, > return "unknown"; > } > Please describe public lib function here. Regards, Kamil > -static void xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, > - struct drm_xe_ext_set_property *extn) > +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, > + struct drm_xe_ext_set_property *extn) > { > __u64 *prop = from_user_pointer(properties->properties_ptr); > struct drm_xe_ext_set_property *ext = extn; > @@ -1063,7 +1063,7 @@ int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg) > struct intel_xe_oa_open_prop *oprop = (struct intel_xe_oa_open_prop *)arg; > > igt_assert_lte(oprop->num_properties, XE_OA_MAX_SET_PROPERTIES); > - xe_oa_prop_to_ext(oprop, ext); > + intel_xe_oa_prop_to_ext(oprop, ext); > } > > return igt_ioctl(fd, DRM_IOCTL_XE_OBSERVATION, &p); > diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h > index 962f9dddcc..7d3d074560 100644 > --- a/lib/xe/xe_oa.h > +++ b/lib/xe/xe_oa.h > @@ -398,6 +398,8 @@ uint64_t intel_xe_perf_read_record_timestamp_raw(const struct intel_xe_perf *per > const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, > const struct intel_xe_perf_record_header *record); > > +void intel_xe_oa_prop_to_ext(struct intel_xe_oa_open_prop *properties, > + struct drm_xe_ext_set_property *extn); > int intel_xe_perf_ioctl(int fd, enum drm_xe_observation_op op, void *arg); > void intel_xe_perf_ioctl_err(int fd, enum drm_xe_observation_op op, void *arg, int err); > > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > index 92f5828c79..33e978a488 100644 > --- a/tests/intel/xe_oa.c > +++ b/tests/intel/xe_oa.c > @@ -22,6 +22,7 @@ > #include "drm.h" > #include "igt.h" > #include "igt_device.h" > +#include "igt_syncobj.h" > #include "igt_sysfs.h" > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" > @@ -4463,6 +4464,255 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open, > __perf_close(stream_fd); > } > > + > +/* Return alternative config_id if available, else just return config_id */ > +static void find_alt_oa_config(u32 config_id, u32 *alt_config_id) > +{ > + struct dirent *entry; > + int metrics_fd, dir_fd; > + DIR *metrics_dir; > + bool ret; > + > + metrics_fd = openat(sysfs, "metrics", O_DIRECTORY); > + igt_assert_lte(0, metrics_fd); > + > + metrics_dir = fdopendir(metrics_fd); > + igt_assert(metrics_dir); > + > + while ((entry = readdir(metrics_dir))) { > + if (entry->d_type != DT_DIR) > + continue; > + > + dir_fd = openat(metrics_fd, entry->d_name, O_RDONLY); > + ret = __igt_sysfs_get_u32(dir_fd, "id", alt_config_id); > + close(dir_fd); > + if (!ret) > + continue; > + > + if (config_id != *alt_config_id) > + goto exit; > + } > + > + *alt_config_id = config_id; > +exit: > + closedir(metrics_dir); > +} > + > +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull > + > +#define WAIT (0x1 << 0) > +#define CONFIG (0x1 << 1) > + > +enum oa_sync_type { > + OA_SYNC_TYPE_SYNCOBJ, > + OA_SYNC_TYPE_USERPTR, > + OA_SYNC_TYPE_UFENCE, > +}; > + > +struct oa_sync { > + enum oa_sync_type sync_type; > + u32 syncobj; > + u32 vm; > + u32 bo; > + size_t bo_size; > + struct { > + uint64_t vm_sync; > + uint64_t pad; > + uint64_t oa_sync; > + } *data; > +}; > + > +static void > +oa_sync_init(enum oa_sync_type sync_type, const struct drm_xe_engine_class_instance *hwe, > + struct oa_sync *osync, struct drm_xe_sync *sync) > +{ > + uint64_t addr = 0x1a0000; > + > + osync->sync_type = sync_type; > + sync->flags = DRM_XE_SYNC_FLAG_SIGNAL; > + > + switch (osync->sync_type) { > + case OA_SYNC_TYPE_SYNCOBJ: > + osync->syncobj = syncobj_create(drm_fd, 0); > + sync->handle = osync->syncobj; > + sync->type = DRM_XE_SYNC_TYPE_SYNCOBJ; > + break; > + case OA_SYNC_TYPE_USERPTR: > + case OA_SYNC_TYPE_UFENCE: > + sync->type = DRM_XE_SYNC_TYPE_USER_FENCE; > + sync->timeline_value = USER_FENCE_VALUE; > + > + osync->vm = xe_vm_create(drm_fd, 0, 0); > + osync->bo_size = xe_bb_size(drm_fd, sizeof(*osync->data)); > + if (osync->sync_type == OA_SYNC_TYPE_USERPTR) { > + osync->data = aligned_alloc(xe_get_default_alignment(drm_fd), > + osync->bo_size); > + igt_assert(osync->data); > + } else { > + osync->bo = xe_bo_create(drm_fd, osync->vm, osync->bo_size, > + vram_if_possible(drm_fd, hwe->gt_id), > + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); > + osync->data = xe_bo_map(drm_fd, osync->bo, osync->bo_size); > + } > + memset(osync->data, 0, osync->bo_size); > + > + sync->addr = to_user_pointer(&osync->data[0].vm_sync); > + if (osync->bo) > + xe_vm_bind_async(drm_fd, osync->vm, 0, osync->bo, 0, > + addr, osync->bo_size, sync, 1); > + else > + xe_vm_bind_userptr_async(drm_fd, osync->vm, 0, > + to_user_pointer(osync->data), > + addr, osync->bo_size, sync, 1); > + xe_wait_ufence(drm_fd, &osync->data[0].vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); > + > + sync->addr = to_user_pointer(&osync->data[0].oa_sync); > + break; > + default: > + igt_assert(false); > + } > +} > + > +static void oa_sync_wait(struct oa_sync *osync) > +{ > + switch (osync->sync_type) { > + case OA_SYNC_TYPE_SYNCOBJ: > + igt_assert(syncobj_wait(drm_fd, &osync->syncobj, 1, INT64_MAX, 0, NULL)); > + syncobj_reset(drm_fd, &osync->syncobj, 1); > + break; > + case OA_SYNC_TYPE_USERPTR: > + case OA_SYNC_TYPE_UFENCE: > + xe_wait_ufence(drm_fd, &osync->data[0].oa_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); > + osync->data[0].oa_sync = 0; > + break; > + default: > + igt_assert(false); > + } > +} > + > +static void oa_sync_free(struct oa_sync *osync) > +{ > + switch (osync->sync_type) { > + case OA_SYNC_TYPE_SYNCOBJ: > + syncobj_destroy(drm_fd, osync->syncobj); > + break; > + case OA_SYNC_TYPE_USERPTR: > + case OA_SYNC_TYPE_UFENCE: > + if (osync->bo) { > + munmap(osync->data, osync->bo_size); > + gem_close(drm_fd, osync->bo); > + } else { > + free(osync->data); > + } > + xe_vm_destroy(drm_fd, osync->vm); > + break; > + default: > + igt_assert(false); > + } > +} > + > +/** > + * SUBTEST: syncs-%s-%s > + * > + * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and > + * reconfig flags) signal correctly in open and reconfig code > + * paths > + * > + * arg[1]: > + * > + * @syncobj: sync type syncobj > + * > + * arg[2]: > + * > + * @wait-cfg: Exercise reconfig path and wait for syncs to signal > + * @wait: Don't exercise reconfig path and wait for syncs to signal > + * @cfg: Exercise reconfig path but don't wait for syncs to signal > + * @none: Don't exercise reconfig path and don't wait for syncs to signal > + */ > + > +/** > + * SUBTEST: syncs-%s-%s > + * > + * Description: Test OA syncs (with %arg[1] sync types and %arg[2] wait and > + * reconfig flags) signal correctly in open and reconfig code > + * paths > + * > + * arg[1]: > + * > + * @userptr: sync type userptr > + * @ufence: sync type ufence > + * > + * arg[2]: > + * > + * @wait-cfg: Exercise reconfig path and wait for syncs to signal > + * @wait: Don't exercise reconfig path and wait for syncs to signal > + */ > +static void test_syncs(const struct drm_xe_engine_class_instance *hwe, > + enum oa_sync_type sync_type, int flags) > +{ > + struct drm_xe_ext_set_property extn[XE_OA_MAX_SET_PROPERTIES] = {}; > + struct intel_xe_perf_metric_set *test_set = metric_set(hwe); > + struct drm_xe_sync sync = {}; > + struct oa_sync osync = {}; > + uint64_t open_properties[] = { > + DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0, > + DRM_XE_OA_PROPERTY_SAMPLE_OA, true, > + DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set, > + DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format), > + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, > + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), > + }; > + struct intel_xe_oa_open_prop open_param = { > + .num_properties = ARRAY_SIZE(open_properties) / 2, > + .properties_ptr = to_user_pointer(open_properties), > + }; > + uint64_t config_properties[] = { > + DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0, /* Filled later */ > + DRM_XE_OA_PROPERTY_NUM_SYNCS, 1, > + DRM_XE_OA_PROPERTY_SYNCS, to_user_pointer(&sync), > + }; > + struct intel_xe_oa_open_prop config_param = { > + .num_properties = ARRAY_SIZE(config_properties) / 2, > + .properties_ptr = to_user_pointer(config_properties), > + }; > + uint32_t alt_config_id; > + int ret; > + > + /* > + * Necessarily wait in userptr/ufence cases, otherwise IGT process can exit > + * after calling oa_sync_free, which results in -EFAULT when kernel signals > + * the userptr/ufence > + */ > + if (sync_type == OA_SYNC_TYPE_USERPTR || sync_type == OA_SYNC_TYPE_UFENCE) > + flags |= WAIT; > + > + oa_sync_init(sync_type, hwe, &osync, &sync); > + > + stream_fd = __perf_open(drm_fd, &open_param, false); > + > + /* Reset the sync object if we are going to reconfig the stream */ > + if (flags & (WAIT | CONFIG)) > + oa_sync_wait(&osync); > + > + if (!(flags & CONFIG)) > + goto exit; > + > + /* Change stream configuration */ > + find_alt_oa_config(test_set->perf_oa_metrics_set, &alt_config_id); > + > + config_properties[1] = alt_config_id; > + intel_xe_oa_prop_to_ext(&config_param, extn); > + > + ret = igt_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_CONFIG, extn); > + igt_assert_eq(ret, test_set->perf_oa_metrics_set); > + > + if (flags & WAIT) > + oa_sync_wait(&osync); > +exit: > + __perf_close(stream_fd); > + oa_sync_free(&osync); > +} > + > static const char *xe_engine_class_name(uint32_t engine_class) > { > switch (engine_class) { > @@ -4511,6 +4761,22 @@ static const char *xe_engine_class_name(uint32_t engine_class) > > igt_main > { > + const struct sync_section { > + const char *name; > + enum oa_sync_type sync_type; > + unsigned int flags; > + } sync_sections[] = { > + { "syncobj-wait-cfg", OA_SYNC_TYPE_SYNCOBJ, WAIT | CONFIG}, > + { "syncobj-wait", OA_SYNC_TYPE_SYNCOBJ, WAIT }, > + { "syncobj-cfg", OA_SYNC_TYPE_SYNCOBJ, CONFIG }, > + { "syncobj-none", OA_SYNC_TYPE_SYNCOBJ, 0 }, > + /* userptr/ufence cases always set WAIT (see test_syncs) */ > + { "userptr-wait-cfg", OA_SYNC_TYPE_USERPTR, WAIT | CONFIG}, > + { "userptr-wait", OA_SYNC_TYPE_USERPTR, WAIT }, > + { "ufence-wait-cfg", OA_SYNC_TYPE_UFENCE, WAIT | CONFIG}, > + { "ufence-wait", OA_SYNC_TYPE_UFENCE, WAIT }, > + { NULL }, > + }; > struct drm_xe_engine_class_instance *hwe = NULL; > struct xe_device *xe_dev; > > @@ -4713,6 +4979,22 @@ igt_main > } > } > > + igt_subtest_group { > + igt_fixture { > + struct drm_xe_query_oa_units *qoa = xe_oa_units(drm_fd); > + struct drm_xe_oa_unit *oau = (struct drm_xe_oa_unit *)&qoa->oa_units[0]; > + > + igt_require(oau->capabilities & DRM_XE_OA_CAPS_SYNCS); > + } > + > + for (const struct sync_section *s = sync_sections; s->name; s++) { > + igt_subtest_with_dynamic_f("syncs-%s", s->name) > + __for_one_render_engine(hwe) > + test_syncs(hwe, s->sync_type, s->flags); > + > + } > + } > + > igt_fixture { > /* leave sysctl options in their default state... */ > write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1); > -- > 2.41.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs 2024-10-30 12:54 ` Kamil Konieczny @ 2024-10-31 2:11 ` Dixit, Ashutosh 0 siblings, 0 replies; 14+ messages in thread From: Dixit, Ashutosh @ 2024-10-31 2:11 UTC (permalink / raw) To: Kamil Konieczny, igt-dev, Ashutosh Dixit On Wed, 30 Oct 2024 05:54:11 -0700, Kamil Konieczny wrote: > > > diff --git a/lib/xe/xe_oa.c b/lib/xe/xe_oa.c > > index 4fdd0b8c95..c168669c5d 100644 > > --- a/lib/xe/xe_oa.c > > +++ b/lib/xe/xe_oa.c > > @@ -1025,8 +1025,8 @@ const char *intel_xe_perf_read_report_reason(const struct intel_xe_perf *perf, > > return "unknown"; > > } > > > > Please describe public lib function here. Done. I also went ahead and merged this series. Thanks. ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2024-10-31 2:11 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-10-25 18:52 [PATCH i-g-t 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit 2024-10-25 18:52 ` [PATCH i-g-t 1/2] drm-uapi/xe: Sync with OA syncs uapi update Ashutosh Dixit 2024-10-25 19:36 ` Umesh Nerlige Ramappa 2024-10-28 15:16 ` Kamil Konieczny 2024-10-29 19:38 ` Dixit, Ashutosh 2024-10-25 18:52 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: Tests for OA syncs Ashutosh Dixit 2024-10-25 19:35 ` Umesh Nerlige Ramappa 2024-10-25 19:45 ` Dixit, Ashutosh 2024-10-25 22:02 ` ✓ Fi.CI.BAT: success for tests/intel/oa: Tests for OA syncs (rev4) Patchwork 2024-10-25 22:28 ` ✓ CI.xeBAT: " Patchwork 2024-10-27 12:56 ` ✗ CI.xeFULL: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2024-10-30 2:53 [PATCH i-g-t v5 0/2] tests/intel/oa: Tests for OA syncs Ashutosh Dixit 2024-10-30 2:53 ` [PATCH i-g-t 2/2] tests/intel/xe_oa: " Ashutosh Dixit 2024-10-30 12:54 ` Kamil Konieczny 2024-10-31 2:11 ` Dixit, Ashutosh
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