[PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check

[PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check

[Pravalika Gurram]

check the ctx_timestamp register post gt reset for each engine.

V2: move spinner code to lib avoid code redundancy
    use flags to maintain the readability
    use READ_ONCE to prevent compiler from optimizing it out [Lucas]

Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_spin_batch.c | 118 ++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 9314e229e..72dcf20f9 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -309,6 +309,118 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
 	put_ahnd(ahnd);
 }
 
+static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
+		       bool hang)
+{
+	uint64_t ahnd, bb_size, bb_addr;
+	uint32_t vm, exec_queue, bb;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync syncobj = {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&syncobj),
+	};
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint32_t data;
+		uint64_t vm_sync;
+		uint64_t exec_sync;
+	} *data;
+	uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
+	int64_t timeout = NSEC_PER_SEC;
+	int i, ret;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	vm = xe_vm_create(fd, 0, 0);
+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+	bb_size = xe_bb_size(fd, sizeof(*data));
+	bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
+	bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
+						      ALLOC_STRATEGY_LOW_TO_HIGH);
+	data = xe_bo_map(fd, bb, bb_size);
+	syncobj.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
+
+	batch_offset = (char *)&data->batch - (char *)data;
+	batch_addr = bb_addr + batch_offset;
+	sdi_offset = (char *)&data->data - (char *)data;
+	sdi_addr = bb_addr + sdi_offset;
+
+	i = 0;
+
+	data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
+	data->batch[i++] = sdi_addr;
+	data->batch[i++] = sdi_addr >> 32;
+	data->batch[i++] = 0;
+	if (!hang)
+		data->batch[i++] = MI_BATCH_BUFFER_END;
+	igt_assert(i <= ARRAY_SIZE(data->batch));
+
+	syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
+	exec.exec_queue_id = exec_queue;
+	exec.address = batch_addr;
+	xe_exec(fd, &exec);
+	ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
+	igt_assert(hang ? ret < 0 : ret == 0);
+
+	munmap(data, bb_size);
+	gem_close(fd, bb);
+
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+
+	put_ahnd(ahnd);
+}
+
+static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	struct spin_ctx *ctx = NULL;
+	uint32_t vm;
+	uint32_t ts_1, ts_2;
+
+	vm = xe_vm_create(fd, 0, 0);
+	ctx = xe_spin_ctx_init(fd, eci, vm, 1, 1);
+	xe_spin_sync_start(fd, ctx);
+
+	/* Collect and check timestamps before stopping the spinner */
+	usleep(50000);
+	ts_1 = READ_ONCE(ctx->spin->timestamp);
+	usleep(50000);
+	ts_2 = READ_ONCE(ctx->spin->timestamp);
+	igt_assert_neq_u32(ts_1, ts_2);
+
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
+
+	xe_vm_destroy(fd, vm);
+}
+
+#define TRUE 1
+#define FALSE 0
+/**
+ * SUBTEST: spin-timestamp-check
+ * Description: Intiate gt reset then check the timestamp register for each engine.
+ * Test category: functionality test
+ */
+static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
+{
+
+	exec_store(fd, eci, FALSE);
+
+	exec_store(fd, eci, TRUE);
+
+	run_spinner(fd, eci);
+}
+
 igt_main
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -343,6 +455,12 @@ igt_main
 			xe_for_each_engine_class(class)
 				xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
 
+	igt_subtest_with_dynamic("spin-timestamp-check")
+		xe_for_each_engine(fd, hwe) {
+			igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
+				xe_spin_timestamp_check(fd, hwe);
+		}
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.34.1

[PATCH 0/2] tests/xe_spin_batch: Add spin-timestamp-check

[Pravalika Gurram]

move the spinner related functions to lib
check the ctx_timestamp register post gt reset for each engine.

Pravalika Gurram (2):
  lib/xe/xe_spin: move the spinner related functions to lib
  tests/xe_spin_batch: Add spin-timestamp-check

 lib/xe/xe_spin.c            | 115 +++++++++++++++++++++
 lib/xe/xe_spin.h            |  22 ++++
 tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
 tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++
 4 files changed, 293 insertions(+), 162 deletions(-)

-- 
2.34.1

[PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib

[Pravalika Gurram]

move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
to xe spin lib to avoid code redundancy.

v2: use allocator based on developer preference.
    change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]

Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
---
 lib/xe/xe_spin.c            | 115 +++++++++++++++++++++
 lib/xe/xe_spin.h            |  22 ++++
 tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
 3 files changed, 172 insertions(+), 162 deletions(-)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 3adacc3a8..b611ac5c1 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
 	free(spin);
 }
 
+struct xe_spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
+	      uint16_t width, uint16_t num_placements)
+{
+	struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
+
+	igt_assert(width && num_placements &&
+		   (width == 1 || num_placements == 1));
+	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
+
+	ctx->class = hwe->engine_class;
+	ctx->width = width;
+	ctx->num_placements = num_placements;
+	ctx->vm = vm;
+
+	ctx->exec.num_batch_buffer = width;
+	ctx->exec.num_syncs = 2;
+	ctx->exec.syncs = to_user_pointer(ctx->sync);
+
+	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+	ctx->sync[0].handle = syncobj_create(fd, 0);
+
+	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
+	ctx->sync[1].handle = syncobj_create(fd, 0);
+
+	ctx->bo_size = sizeof(struct xe_spin);
+	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
+	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
+			       vram_if_possible(fd, hwe->gt_id),
+			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+	if (ahnd) {
+		for (unsigned int i = 0; i < width; i++)
+			ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
+					ctx->bo, ctx->bo_size, 0,
+					ALLOC_STRATEGY_LOW_TO_HIGH);
+	} else {
+		for (unsigned int i = 0; i < width; i++)
+			ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
+	}
+
+	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
+
+	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
+					     hwe, 0, &ctx->exec_queue), 0);
+
+	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
+			 ctx->sync, 1);
+
+	return ctx;
+}
+
+void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
+{
+	if (!ctx)
+		return;
+
+	ctx->spin_opts.addr = ctx->addr[0];
+	ctx->spin_opts.write_timestamp = true;
+	ctx->spin_opts.preempt = true;
+	xe_spin_init(ctx->spin, &ctx->spin_opts);
+
+	/* re-use sync[0] for exec */
+	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+
+	ctx->exec.exec_queue_id = ctx->exec_queue;
+
+	if (ctx->width > 1)
+		ctx->exec.address = to_user_pointer(ctx->addr);
+	else
+		ctx->exec.address = ctx->addr[0];
+
+	xe_exec(fd, &ctx->exec);
+
+	xe_spin_wait_started(ctx->spin);
+	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
+
+	igt_debug("%d: spinner started\n", ctx->class);
+}
+
+void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
+{
+	if (!ctx || ctx->ended)
+		return;
+
+	xe_spin_end(ctx->spin);
+
+	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
+	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
+	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
+
+	ctx->ended = true;
+	igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
+		  ctx->spin->timestamp);
+}
+
+void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
+{
+	if (!ctx)
+		return;
+
+	syncobj_destroy(fd, ctx->sync[0].handle);
+	syncobj_destroy(fd, ctx->sync[1].handle);
+	xe_exec_queue_destroy(fd, ctx->exec_queue);
+
+	munmap(ctx->spin, ctx->bo_size);
+	gem_close(fd, ctx->bo);
+
+	free(ctx);
+}
+
 void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
 		  struct xe_cork *cork)
 {
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index d65adb05c..18706dcdf 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -43,9 +43,29 @@ struct xe_spin {
 	uint32_t timestamp;
 };
 
+struct xe_spin_ctx {
+	uint32_t vm;
+	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
+	struct drm_xe_sync sync[2];
+	struct drm_xe_exec exec;
+	uint32_t exec_queue;
+	size_t bo_size;
+	uint32_t bo;
+	struct xe_spin *spin;
+	struct xe_spin_opts spin_opts;
+	bool ended;
+	uint16_t class;
+	uint16_t width;
+	uint16_t num_placements;
+};
+
 igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
 uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
 void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
+struct xe_spin_ctx *
+xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
+	      uint16_t width, uint16_t num_placements);
+void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
 
 #define xe_spin_init_opts(fd, ...) \
 	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
@@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
 void xe_spin_wait_started(struct xe_spin *spin);
 void xe_spin_end(struct xe_spin *spin);
 void xe_spin_free(int fd, struct igt_spin *spin);
+void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
+void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
 
 struct xe_cork {
 	struct xe_spin *spin;
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 5fd7c0416..91ff4a5af 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
 	igt_require(info.num_engines);
 }
 
-struct spin_ctx {
-	uint32_t vm;
-	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
-	struct drm_xe_sync sync[2];
-	struct drm_xe_exec exec;
-	uint32_t exec_queue;
-	size_t bo_size;
-	uint32_t bo;
-	struct xe_spin *spin;
-	struct xe_spin_opts spin_opts;
-	bool ended;
-	uint16_t class;
-	uint16_t width;
-	uint16_t num_placements;
-};
-
-static struct spin_ctx *
-spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
-	      uint16_t width, uint16_t num_placements)
-{
-	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
-
-	igt_assert(width && num_placements &&
-		   (width == 1 || num_placements == 1));
-	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
-
-	ctx->class = hwe->engine_class;
-	ctx->width = width;
-	ctx->num_placements = num_placements;
-	ctx->vm = vm;
-
-	for (unsigned int i = 0; i < width; i++)
-		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
-
-	ctx->exec.num_batch_buffer = width;
-	ctx->exec.num_syncs = 2;
-	ctx->exec.syncs = to_user_pointer(ctx->sync);
-
-	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
-	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
-	ctx->sync[0].handle = syncobj_create(fd, 0);
-
-	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
-	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
-	ctx->sync[1].handle = syncobj_create(fd, 0);
-
-	ctx->bo_size = sizeof(struct xe_spin);
-	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
-	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
-			       vram_if_possible(fd, hwe->gt_id),
-			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
-	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
-
-	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
-					     hwe, 0, &ctx->exec_queue), 0);
-
-	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
-			 ctx->sync, 1);
-
-	return ctx;
-}
-
-static void
-spin_sync_start(int fd, struct spin_ctx *ctx)
-{
-	if (!ctx)
-		return;
-
-	ctx->spin_opts.addr = ctx->addr[0];
-	ctx->spin_opts.write_timestamp = true;
-	ctx->spin_opts.preempt = true;
-	xe_spin_init(ctx->spin, &ctx->spin_opts);
-
-	/* re-use sync[0] for exec */
-	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
-
-	ctx->exec.exec_queue_id = ctx->exec_queue;
-
-	if (ctx->width > 1)
-		ctx->exec.address = to_user_pointer(ctx->addr);
-	else
-		ctx->exec.address = ctx->addr[0];
-
-	xe_exec(fd, &ctx->exec);
-
-	xe_spin_wait_started(ctx->spin);
-	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
-
-	igt_debug("%s: spinner started\n", engine_map[ctx->class]);
-}
-
-static void
-spin_sync_end(int fd, struct spin_ctx *ctx)
-{
-	if (!ctx || ctx->ended)
-		return;
-
-	xe_spin_end(ctx->spin);
-
-	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
-	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
-	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
-	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
-	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
-
-	ctx->ended = true;
-	igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
-		  ctx->spin->timestamp);
-}
-
-static void
-spin_ctx_destroy(int fd, struct spin_ctx *ctx)
-{
-	if (!ctx)
-		return;
-
-	syncobj_destroy(fd, ctx->sync[0].handle);
-	syncobj_destroy(fd, ctx->sync[1].handle);
-	xe_exec_queue_destroy(fd, ctx->exec_queue);
-
-	munmap(ctx->spin, ctx->bo_size);
-	gem_close(fd, ctx->bo);
-
-	free(ctx);
-}
-
 static void
 check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
 	      int class, int width, enum expected_load expected_load)
@@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 {
 	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct spin_ctx *ctx = NULL;
+	struct xe_spin_ctx *ctx = NULL;
 	enum expected_load expected_load;
 	uint32_t vm;
 	int new_fd;
@@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	vm = xe_vm_create(fd, 0, 0);
 	if (flags & TEST_BUSY) {
-		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
-		spin_sync_start(fd, ctx);
+		ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+		xe_spin_sync_start(fd, ctx);
 	}
 
 	read_engine_cycles(fd, pceu1[0]);
@@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 
 	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
-		spin_sync_end(fd, ctx);
+		xe_spin_sync_end(fd, ctx);
 
 	read_engine_cycles(fd, pceu2[0]);
 	if (flags & TEST_ISOLATION)
@@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
 		close(new_fd);
 	}
 
-	spin_sync_end(fd, ctx);
-	spin_ctx_destroy(fd, ctx);
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
 	xe_vm_destroy(fd, vm);
 }
 
@@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct spin_ctx *ctx = NULL;
+	struct xe_spin_ctx *ctx = NULL;
 	uint32_t vm;
 
 	vm = xe_vm_create(fd, 0, 0);
-	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
-	spin_sync_start(fd, ctx);
+	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+	xe_spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 
 	/* destroy queue before sampling again */
-	spin_sync_end(fd, ctx);
-	spin_ctx_destroy(fd, ctx);
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
 
 	read_engine_cycles(fd, pceu2);
 
@@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct spin_ctx *ctx = NULL;
+	struct xe_spin_ctx *ctx = NULL;
 	uint32_t vm;
 	int class;
 
 	vm = xe_vm_create(fd, 0, 0);
 
-	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
-	spin_sync_start(fd, ctx);
+	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+	xe_spin_sync_start(fd, ctx);
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
-	spin_sync_end(fd, ctx);
+	xe_spin_sync_end(fd, ctx);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
@@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
 		check_results(pceu1, pceu2, class, 1, expected_load);
 	}
 
-	spin_sync_end(fd, ctx);
-	spin_ctx_destroy(fd, ctx);
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
 	xe_vm_destroy(fd, vm);
 }
 
@@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
 	struct drm_xe_engine_class_instance *_hwe;
 	uint32_t vm;
 	int class;
@@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 		if (_class == hwe->engine_class || ctx[_class])
 			continue;
 
-		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
-		spin_sync_start(fd, ctx[_class]);
+		ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
+		xe_spin_sync_start(fd, ctx[_class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 	xe_for_each_engine_class(class)
-		spin_sync_end(fd, ctx[class]);
+		xe_spin_sync_end(fd, ctx[class]);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
@@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
 			continue;
 
 		check_results(pceu1, pceu2, class, 1, expected_load);
-		spin_sync_end(fd, ctx[class]);
-		spin_ctx_destroy(fd, ctx[class]);
+		xe_spin_sync_end(fd, ctx[class]);
+		xe_spin_ctx_destroy(fd, ctx[class]);
 	}
 
 	xe_vm_destroy(fd, vm);
@@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
 {
 	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
-	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
+	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
 	struct drm_xe_engine_class_instance *hwe;
 	uint32_t vm;
 	int class;
@@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
 		if (ctx[class])
 			continue;
 
-		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
-		spin_sync_start(fd, ctx[class]);
+		ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
+		xe_spin_sync_start(fd, ctx[class]);
 	}
 
 	read_engine_cycles(fd, pceu1);
 	usleep(batch_duration_usec);
 	xe_for_each_engine_class(class)
-		spin_sync_end(fd, ctx[class]);
+		xe_spin_sync_end(fd, ctx[class]);
 	read_engine_cycles(fd, pceu2);
 
 	xe_for_each_engine_class(class) {
@@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
 			continue;
 
 		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
-		spin_sync_end(fd, ctx[class]);
-		spin_ctx_destroy(fd, ctx[class]);
+		xe_spin_sync_end(fd, ctx[class]);
+		xe_spin_ctx_destroy(fd, ctx[class]);
 	}
 
 	xe_vm_destroy(fd, vm);
@@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
 	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
-	struct spin_ctx *ctx = NULL;
+	struct xe_spin_ctx *ctx = NULL;
 	enum expected_load expected_load;
 	int fd_spill, num_placements;
 	uint32_t vm;
@@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 
 	vm = xe_vm_create(fd, 0, 0);
 	if (flags & TEST_BUSY) {
-		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
-		spin_sync_start(fd, ctx);
+		ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
+		xe_spin_sync_start(fd, ctx);
 	}
 
 	read_engine_cycles(fd, pceu[0]);
@@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 
 	usleep(batch_duration_usec);
 	if (flags & TEST_TRAILING_IDLE)
-		spin_sync_end(fd, ctx);
+		xe_spin_sync_end(fd, ctx);
 
 	read_engine_cycles(fd, pceu[1]);
 	if (flags & TEST_ISOLATION)
@@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
 		close(fd_spill);
 	}
 
-	spin_sync_end(fd, ctx);
-	spin_ctx_destroy(fd, ctx);
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
 
 	xe_vm_destroy(fd, vm);
 }
-- 
2.34.1

[PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check

[Pravalika Gurram]

check the ctx_timestamp register post gt reset for each engine.

V2: move spinner code to lib avoid code redundancy
    use flags to maintain the readability
    use READ_ONCE to prevent compiler from optimizing it out [Lucas]

V3: call allocator in run_spinner and pass to spinner ctx [Zbigniew]

Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 9314e229e..90817d5e4 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -309,6 +309,121 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
 	put_ahnd(ahnd);
 }
 
+static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
+		       bool hang)
+{
+	uint64_t ahnd, bb_size, bb_addr;
+	uint32_t vm, exec_queue, bb;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync syncobj = {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&syncobj),
+	};
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint32_t data;
+		uint64_t vm_sync;
+		uint64_t exec_sync;
+	} *data;
+	uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
+	int64_t timeout = NSEC_PER_SEC;
+	int i, ret;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	vm = xe_vm_create(fd, 0, 0);
+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+	bb_size = xe_bb_size(fd, sizeof(*data));
+	bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
+	bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
+						      ALLOC_STRATEGY_LOW_TO_HIGH);
+	data = xe_bo_map(fd, bb, bb_size);
+	syncobj.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
+
+	batch_offset = (char *)&data->batch - (char *)data;
+	batch_addr = bb_addr + batch_offset;
+	sdi_offset = (char *)&data->data - (char *)data;
+	sdi_addr = bb_addr + sdi_offset;
+
+	i = 0;
+
+	data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
+	data->batch[i++] = sdi_addr;
+	data->batch[i++] = sdi_addr >> 32;
+	data->batch[i++] = 0;
+	if (!hang)
+		data->batch[i++] = MI_BATCH_BUFFER_END;
+	igt_assert(i <= ARRAY_SIZE(data->batch));
+
+	syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
+	exec.exec_queue_id = exec_queue;
+	exec.address = batch_addr;
+	xe_exec(fd, &exec);
+	ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
+	igt_assert(hang ? ret < 0 : ret == 0);
+
+	munmap(data, bb_size);
+	gem_close(fd, bb);
+
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+
+	put_ahnd(ahnd);
+}
+
+static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	struct xe_spin_ctx *ctx = NULL;
+	uint32_t vm;
+	uint32_t ts_1, ts_2;
+	uint64_t ahnd;
+
+	vm = xe_vm_create(fd, 0, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+	ctx = xe_spin_ctx_init(fd, eci, ahnd, vm, 1, 1);
+	xe_spin_sync_start(fd, ctx);
+
+	/* Collect and check timestamps before stopping the spinner */
+	usleep(50000);
+	ts_1 = READ_ONCE(ctx->spin->timestamp);
+	usleep(50000);
+	ts_2 = READ_ONCE(ctx->spin->timestamp);
+	igt_assert_neq_u32(ts_1, ts_2);
+
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
+
+	xe_vm_destroy(fd, vm);
+	put_ahnd(ahnd);
+}
+
+#define TRUE 1
+#define FALSE 0
+/**
+ * SUBTEST: spin-timestamp-check
+ * Description: Intiate gt reset then check the timestamp register for each engine.
+ * Test category: functionality test
+ */
+static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	/*sanity check for exec submission*/
+	exec_store(fd, eci, FALSE);
+
+	exec_store(fd, eci, TRUE);
+
+	run_spinner(fd, eci);
+}
+
 igt_main
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -343,6 +458,12 @@ igt_main
 			xe_for_each_engine_class(class)
 				xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
 
+	igt_subtest_with_dynamic("spin-timestamp-check")
+		xe_for_each_engine(fd, hwe) {
+			igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
+				xe_spin_timestamp_check(fd, hwe);
+		}
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.34.1

✓ CI.xeBAT: success for tests/xe_spin_batch: Add spin-timestamp-check (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3981 bytes --]

== Series Details ==

Series: tests/xe_spin_batch: Add spin-timestamp-check (rev3)
URL   : https://patchwork.freedesktop.org/series/140933/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8100_BAT -> XEIGTPW_12069_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_12069_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_evict@evict-beng-small:
    - bat-adlp-7:         NOTRUN -> [SKIP][1] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-adlp-7/igt@xe_evict@evict-beng-small.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr:
    - bat-dg2-oem2:       NOTRUN -> [SKIP][2] ([Intel XE#288]) +32 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-dg2-oem2/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch:
    - bat-adlp-7:         NOTRUN -> [SKIP][3] ([Intel XE#288]) +32 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - bat-dg2-oem2:       NOTRUN -> [SKIP][4] ([Intel XE#2229])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-dg2-oem2/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
    - bat-adlp-7:         NOTRUN -> [SKIP][5] ([Intel XE#2229])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-adlp-7/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  
#### Possible fixes ####

  * igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit:
    - bat-bmg-1:          [INCOMPLETE][6] ([Intel XE#2874] / [Intel XE#2998]) -> [PASS][7] +1 other test pass
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/bat-bmg-1/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-bmg-1/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
    - bat-adlp-7:         [INCOMPLETE][8] ([Intel XE#2874]) -> [PASS][9] +1 other test pass
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
    - bat-dg2-oem2:       [INCOMPLETE][10] ([Intel XE#2874]) -> [PASS][11] +1 other test pass
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/bat-dg2-oem2/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/bat-dg2-oem2/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html

  
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2874
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2998]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2998
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688


Build changes
-------------

  * IGT: IGT_8100 -> IGTPW_12069
  * Linux: xe-2179-438ef86a725b59a171dba81fc258bb23a0ff536c -> xe-2188-5f445c6723de9ac7087170f4ee8fcb2050ab8346

  IGTPW_12069: 12069
  IGT_8100: 84e42580f918da926481fd2fb37be01451d6ee9a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2179-438ef86a725b59a171dba81fc258bb23a0ff536c: 438ef86a725b59a171dba81fc258bb23a0ff536c
  xe-2188-5f445c6723de9ac7087170f4ee8fcb2050ab8346: 5f445c6723de9ac7087170f4ee8fcb2050ab8346

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/index.html

[-- Attachment #2: Type: text/html, Size: 4949 bytes --]

✗ Fi.CI.BAT: failure for tests/xe_spin_batch: Add spin-timestamp-check (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10776 bytes --]

== Series Details ==

Series: tests/xe_spin_batch: Add spin-timestamp-check (rev3)
URL   : https://patchwork.freedesktop.org/series/140933/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8100 -> IGTPW_12069
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_12069 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_12069, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/index.html

Participating hosts (45 -> 44)
------------------------------

  Additional (2): bat-arls-6 bat-arls-5 
  Missing    (3): bat-arls-2 bat-arls-1 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_12069:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_dsc@dsc-basic:
    - bat-arls-5:         NOTRUN -> [SKIP][1] +16 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_dsc@dsc-basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_12069 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-arls-5:         NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@eof:
    - bat-arls-5:         NOTRUN -> [SKIP][3] ([i915#11191] / [i915#11345]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@fbdev@eof.html

  * igt@fbdev@info:
    - bat-arls-5:         NOTRUN -> [SKIP][4] ([i915#1849])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@fbdev@info.html

  * igt@gem_lmem_swapping@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][5] ([i915#10213] / [i915#11671]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@gem_lmem_swapping@basic.html

  * igt@gem_mmap@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][6] ([i915#11343] / [i915#4083])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][7] ([i915#10197] / [i915#10211] / [i915#4079])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][8] ([i915#12637] / [i915#4077]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-arls-5:         NOTRUN -> [SKIP][9] ([i915#10206] / [i915#4079])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-arls-5:         NOTRUN -> [SKIP][10] ([i915#10209] / [i915#11681])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][11] ([i915#12727]) +33 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][12] ([i915#10341] / [i915#12727])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@sanitycheck:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][13] ([i915#10341]) +6 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-arls-5:         NOTRUN -> [SKIP][14] ([i915#10200] / [i915#12203])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@clobberred-modifier:
    - bat-arls-5:         NOTRUN -> [SKIP][15] ([i915#10200]) +8 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_addfb_basic@clobberred-modifier.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-arls-5:         NOTRUN -> [SKIP][16] ([i915#3637]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-arls-5:         NOTRUN -> [SKIP][17] ([i915#10207])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][18] ([i915#4342] / [i915#5354])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-arls-5:         NOTRUN -> [SKIP][19] ([i915#9812])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-arls-5:         NOTRUN -> [SKIP][20] ([i915#9732]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-arls-5:         NOTRUN -> [SKIP][21] ([i915#10208] / [i915#8809])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-arls-5:         NOTRUN -> [SKIP][22] ([i915#3708])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - bat-arls-5:         NOTRUN -> [SKIP][23] ([i915#10212] / [i915#3708])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-arls-5:         NOTRUN -> [SKIP][24] ([i915#12637] / [i915#3708] / [i915#4077]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - bat-arls-5:         NOTRUN -> [SKIP][25] ([i915#10214] / [i915#3708])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-arls-5:         NOTRUN -> [SKIP][26] ([i915#10216] / [i915#3708])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arls-5/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-arlh-3:         [INCOMPLETE][27] ([i915#10341]) -> [PASS][28] +1 other test pass
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8100/bat-arlh-3/igt@i915_selftest@live.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/bat-arlh-3/igt@i915_selftest@live.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
  [i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
  [i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
  [i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
  [i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
  [i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
  [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
  [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#11191]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11191
  [i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
  [i915#11345]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11345
  [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12203]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12203
  [i915#12637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12637
  [i915#12727]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12727
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8100 -> IGTPW_12069
  * Linux: CI_DRM_15647 -> CI_DRM_15656

  CI-20190529: 20190529
  CI_DRM_15647: 438ef86a725b59a171dba81fc258bb23a0ff536c @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_15656: 5f445c6723de9ac7087170f4ee8fcb2050ab8346 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12069: 12069
  IGT_8100: 84e42580f918da926481fd2fb37be01451d6ee9a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12069/index.html

[-- Attachment #2: Type: text/html, Size: 12717 bytes --]

Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib

[Zbigniew Kempczyński]

+Lucas

On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> to xe spin lib to avoid code redundancy.
> 
> v2: use allocator based on developer preference.
>     change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
> 
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> ---
>  lib/xe/xe_spin.c            | 115 +++++++++++++++++++++
>  lib/xe/xe_spin.h            |  22 ++++
>  tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
>  3 files changed, 172 insertions(+), 162 deletions(-)
> 
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 3adacc3a8..b611ac5c1 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
>  	free(spin);
>  }
>  
> +struct xe_spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
> +	      uint16_t width, uint16_t num_placements)
> +{
> +	struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
> +
> +	igt_assert(width && num_placements &&
> +		   (width == 1 || num_placements == 1));
> +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> +
> +	ctx->class = hwe->engine_class;
> +	ctx->width = width;
> +	ctx->num_placements = num_placements;
> +	ctx->vm = vm;
> +
> +	ctx->exec.num_batch_buffer = width;
> +	ctx->exec.num_syncs = 2;
> +	ctx->exec.syncs = to_user_pointer(ctx->sync);
> +
> +	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> +	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> +	ctx->sync[0].handle = syncobj_create(fd, 0);
> +
> +	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> +	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> +	ctx->sync[1].handle = syncobj_create(fd, 0);
> +
> +	ctx->bo_size = sizeof(struct xe_spin);
> +	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> +	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> +			       vram_if_possible(fd, hwe->gt_id),
> +			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +	if (ahnd) {
> +		for (unsigned int i = 0; i < width; i++)
> +			ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
> +					ctx->bo, ctx->bo_size, 0,
> +					ALLOC_STRATEGY_LOW_TO_HIGH);
> +	} else {
> +		for (unsigned int i = 0; i < width; i++)
> +			ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> +	}
> +
> +	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> +
> +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> +					     hwe, 0, &ctx->exec_queue), 0);
> +
> +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> +			 ctx->sync, 1);

@Lucas

I'm looking here and I've doubts what's going on in 'utilization_multi'
subtest where width > 1. I mean we bind only addr[0], but according
to exec with width > 1 I assume addr[1] should be bound as well.

What I'm missing here?

--
Zbigniew

> +
> +	return ctx;
> +}
> +
> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
> +{
> +	if (!ctx)
> +		return;
> +
> +	ctx->spin_opts.addr = ctx->addr[0];
> +	ctx->spin_opts.write_timestamp = true;
> +	ctx->spin_opts.preempt = true;
> +	xe_spin_init(ctx->spin, &ctx->spin_opts);
> +
> +	/* re-use sync[0] for exec */
> +	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +
> +	ctx->exec.exec_queue_id = ctx->exec_queue;
> +
> +	if (ctx->width > 1)
> +		ctx->exec.address = to_user_pointer(ctx->addr);
> +	else
> +		ctx->exec.address = ctx->addr[0];
> +
> +	xe_exec(fd, &ctx->exec);
> +
> +	xe_spin_wait_started(ctx->spin);
> +	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> +
> +	igt_debug("%d: spinner started\n", ctx->class);
> +}
> +
> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
> +{
> +	if (!ctx || ctx->ended)
> +		return;
> +
> +	xe_spin_end(ctx->spin);
> +
> +	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> +	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> +
> +	ctx->ended = true;
> +	igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> +		  ctx->spin->timestamp);
> +}
> +
> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
> +{
> +	if (!ctx)
> +		return;
> +
> +	syncobj_destroy(fd, ctx->sync[0].handle);
> +	syncobj_destroy(fd, ctx->sync[1].handle);
> +	xe_exec_queue_destroy(fd, ctx->exec_queue);
> +
> +	munmap(ctx->spin, ctx->bo_size);
> +	gem_close(fd, ctx->bo);
> +
> +	free(ctx);
> +}
> +
>  void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>  		  struct xe_cork *cork)
>  {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index d65adb05c..18706dcdf 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -43,9 +43,29 @@ struct xe_spin {
>  	uint32_t timestamp;
>  };
>  
> +struct xe_spin_ctx {
> +	uint32_t vm;
> +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> +	struct drm_xe_sync sync[2];
> +	struct drm_xe_exec exec;
> +	uint32_t exec_queue;
> +	size_t bo_size;
> +	uint32_t bo;
> +	struct xe_spin *spin;
> +	struct xe_spin_opts spin_opts;
> +	bool ended;
> +	uint16_t class;
> +	uint16_t width;
> +	uint16_t num_placements;
> +};
> +
>  igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
>  uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
>  void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
> +struct xe_spin_ctx *
> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
> +	      uint16_t width, uint16_t num_placements);
> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
>  
>  #define xe_spin_init_opts(fd, ...) \
>  	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
> @@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>  void xe_spin_wait_started(struct xe_spin *spin);
>  void xe_spin_end(struct xe_spin *spin);
>  void xe_spin_free(int fd, struct igt_spin *spin);
> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
>  
>  struct xe_cork {
>  	struct xe_spin *spin;
> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
> index 5fd7c0416..91ff4a5af 100644
> --- a/tests/intel/xe_drm_fdinfo.c
> +++ b/tests/intel/xe_drm_fdinfo.c
> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
>  	igt_require(info.num_engines);
>  }
>  
> -struct spin_ctx {
> -	uint32_t vm;
> -	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> -	struct drm_xe_sync sync[2];
> -	struct drm_xe_exec exec;
> -	uint32_t exec_queue;
> -	size_t bo_size;
> -	uint32_t bo;
> -	struct xe_spin *spin;
> -	struct xe_spin_opts spin_opts;
> -	bool ended;
> -	uint16_t class;
> -	uint16_t width;
> -	uint16_t num_placements;
> -};
> -
> -static struct spin_ctx *
> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
> -	      uint16_t width, uint16_t num_placements)
> -{
> -	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> -
> -	igt_assert(width && num_placements &&
> -		   (width == 1 || num_placements == 1));
> -	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> -
> -	ctx->class = hwe->engine_class;
> -	ctx->width = width;
> -	ctx->num_placements = num_placements;
> -	ctx->vm = vm;
> -
> -	for (unsigned int i = 0; i < width; i++)
> -		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> -
> -	ctx->exec.num_batch_buffer = width;
> -	ctx->exec.num_syncs = 2;
> -	ctx->exec.syncs = to_user_pointer(ctx->sync);
> -
> -	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> -	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> -	ctx->sync[0].handle = syncobj_create(fd, 0);
> -
> -	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> -	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> -	ctx->sync[1].handle = syncobj_create(fd, 0);
> -
> -	ctx->bo_size = sizeof(struct xe_spin);
> -	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> -	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> -			       vram_if_possible(fd, hwe->gt_id),
> -			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> -	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> -
> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
> -					     hwe, 0, &ctx->exec_queue), 0);
> -
> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
> -			 ctx->sync, 1);
> -
> -	return ctx;
> -}
> -
> -static void
> -spin_sync_start(int fd, struct spin_ctx *ctx)
> -{
> -	if (!ctx)
> -		return;
> -
> -	ctx->spin_opts.addr = ctx->addr[0];
> -	ctx->spin_opts.write_timestamp = true;
> -	ctx->spin_opts.preempt = true;
> -	xe_spin_init(ctx->spin, &ctx->spin_opts);
> -
> -	/* re-use sync[0] for exec */
> -	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> -
> -	ctx->exec.exec_queue_id = ctx->exec_queue;
> -
> -	if (ctx->width > 1)
> -		ctx->exec.address = to_user_pointer(ctx->addr);
> -	else
> -		ctx->exec.address = ctx->addr[0];
> -
> -	xe_exec(fd, &ctx->exec);
> -
> -	xe_spin_wait_started(ctx->spin);
> -	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> -
> -	igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> -}
> -
> -static void
> -spin_sync_end(int fd, struct spin_ctx *ctx)
> -{
> -	if (!ctx || ctx->ended)
> -		return;
> -
> -	xe_spin_end(ctx->spin);
> -
> -	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> -	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
> -
> -	ctx->ended = true;
> -	igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
> -		  ctx->spin->timestamp);
> -}
> -
> -static void
> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
> -{
> -	if (!ctx)
> -		return;
> -
> -	syncobj_destroy(fd, ctx->sync[0].handle);
> -	syncobj_destroy(fd, ctx->sync[1].handle);
> -	xe_exec_queue_destroy(fd, ctx->exec_queue);
> -
> -	munmap(ctx->spin, ctx->bo_size);
> -	gem_close(fd, ctx->bo);
> -
> -	free(ctx);
> -}
> -
>  static void
>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>  	      int class, int width, enum expected_load expected_load)
> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  {
>  	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct spin_ctx *ctx = NULL;
> +	struct xe_spin_ctx *ctx = NULL;
>  	enum expected_load expected_load;
>  	uint32_t vm;
>  	int new_fd;
> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	if (flags & TEST_BUSY) {
> -		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> -		spin_sync_start(fd, ctx);
> +		ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> +		xe_spin_sync_start(fd, ctx);
>  	}
>  
>  	read_engine_cycles(fd, pceu1[0]);
> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  
>  	usleep(batch_duration_usec);
>  	if (flags & TEST_TRAILING_IDLE)
> -		spin_sync_end(fd, ctx);
> +		xe_spin_sync_end(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu2[0]);
>  	if (flags & TEST_ISOLATION)
> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>  		close(new_fd);
>  	}
>  
> -	spin_sync_end(fd, ctx);
> -	spin_ctx_destroy(fd, ctx);
> +	xe_spin_sync_end(fd, ctx);
> +	xe_spin_ctx_destroy(fd, ctx);
>  	xe_vm_destroy(fd, vm);
>  }
>  
> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct spin_ctx *ctx = NULL;
> +	struct xe_spin_ctx *ctx = NULL;
>  	uint32_t vm;
>  
>  	vm = xe_vm_create(fd, 0, 0);
> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> -	spin_sync_start(fd, ctx);
> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> +	xe_spin_sync_start(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  
>  	/* destroy queue before sampling again */
> -	spin_sync_end(fd, ctx);
> -	spin_ctx_destroy(fd, ctx);
> +	xe_spin_sync_end(fd, ctx);
> +	xe_spin_ctx_destroy(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu2);
>  
> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct spin_ctx *ctx = NULL;
> +	struct xe_spin_ctx *ctx = NULL;
>  	uint32_t vm;
>  	int class;
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  
> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> -	spin_sync_start(fd, ctx);
> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> +	xe_spin_sync_start(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
> -	spin_sync_end(fd, ctx);
> +	xe_spin_sync_end(fd, ctx);
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>  		check_results(pceu1, pceu2, class, 1, expected_load);
>  	}
>  
> -	spin_sync_end(fd, ctx);
> -	spin_ctx_destroy(fd, ctx);
> +	xe_spin_sync_end(fd, ctx);
> +	xe_spin_ctx_destroy(fd, ctx);
>  	xe_vm_destroy(fd, vm);
>  }
>  
> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>  	struct drm_xe_engine_class_instance *_hwe;
>  	uint32_t vm;
>  	int class;
> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  		if (_class == hwe->engine_class || ctx[_class])
>  			continue;
>  
> -		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> -		spin_sync_start(fd, ctx[_class]);
> +		ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
> +		xe_spin_sync_start(fd, ctx[_class]);
>  	}
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  	xe_for_each_engine_class(class)
> -		spin_sync_end(fd, ctx[class]);
> +		xe_spin_sync_end(fd, ctx[class]);
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>  			continue;
>  
>  		check_results(pceu1, pceu2, class, 1, expected_load);
> -		spin_sync_end(fd, ctx[class]);
> -		spin_ctx_destroy(fd, ctx[class]);
> +		xe_spin_sync_end(fd, ctx[class]);
> +		xe_spin_ctx_destroy(fd, ctx[class]);
>  	}
>  
>  	xe_vm_destroy(fd, vm);
> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
>  {
>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>  	struct drm_xe_engine_class_instance *hwe;
>  	uint32_t vm;
>  	int class;
> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
>  		if (ctx[class])
>  			continue;
>  
> -		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> -		spin_sync_start(fd, ctx[class]);
> +		ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> +		xe_spin_sync_start(fd, ctx[class]);
>  	}
>  
>  	read_engine_cycles(fd, pceu1);
>  	usleep(batch_duration_usec);
>  	xe_for_each_engine_class(class)
> -		spin_sync_end(fd, ctx[class]);
> +		xe_spin_sync_end(fd, ctx[class]);
>  	read_engine_cycles(fd, pceu2);
>  
>  	xe_for_each_engine_class(class) {
> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
>  			continue;
>  
>  		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
> -		spin_sync_end(fd, ctx[class]);
> -		spin_ctx_destroy(fd, ctx[class]);
> +		xe_spin_sync_end(fd, ctx[class]);
> +		xe_spin_ctx_destroy(fd, ctx[class]);
>  	}
>  
>  	xe_vm_destroy(fd, vm);
> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>  	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
> -	struct spin_ctx *ctx = NULL;
> +	struct xe_spin_ctx *ctx = NULL;
>  	enum expected_load expected_load;
>  	int fd_spill, num_placements;
>  	uint32_t vm;
> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  
>  	vm = xe_vm_create(fd, 0, 0);
>  	if (flags & TEST_BUSY) {
> -		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> -		spin_sync_start(fd, ctx);
> +		ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
> +		xe_spin_sync_start(fd, ctx);
>  	}
>  
>  	read_engine_cycles(fd, pceu[0]);
> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  
>  	usleep(batch_duration_usec);
>  	if (flags & TEST_TRAILING_IDLE)
> -		spin_sync_end(fd, ctx);
> +		xe_spin_sync_end(fd, ctx);
>  
>  	read_engine_cycles(fd, pceu[1]);
>  	if (flags & TEST_ISOLATION)
> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>  		close(fd_spill);
>  	}
>  
> -	spin_sync_end(fd, ctx);
> -	spin_ctx_destroy(fd, ctx);
> +	xe_spin_sync_end(fd, ctx);
> +	xe_spin_ctx_destroy(fd, ctx);
>  
>  	xe_vm_destroy(fd, vm);
>  }
> -- 
> 2.34.1
> 

Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib

[Lucas De Marchi]

On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
>+Lucas

Pravalika, please keep me in Cc. I don't watch the igt mailing list
close enough, particularly when it's a follow up to a suggestion I gave.

>
>On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
>> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
>> to xe spin lib to avoid code redundancy.
>>
>> v2: use allocator based on developer preference.
>>     change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]

but we already have another thing named ctx there, the rename doesn't
improve it.

 From lib/xe/xe_spin.h, what should be added on is

struct xe_cork {                    
	struct xe_spin *spin;       
	int fd;                     
	uint32_t vm;                
	uint32_t bo;                
	uint32_t exec_queue;        
	uint32_t syncobj;           
};                                  

I don't really like that name, but we can do a rename on top... or we
can rename it now and then move things.

>>
>> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
>> ---
>>  lib/xe/xe_spin.c            | 115 +++++++++++++++++++++
>>  lib/xe/xe_spin.h            |  22 ++++
>>  tests/intel/xe_drm_fdinfo.c | 197 +++++++-----------------------------
>>  3 files changed, 172 insertions(+), 162 deletions(-)
>>
>> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
>> index 3adacc3a8..b611ac5c1 100644
>> --- a/lib/xe/xe_spin.c
>> +++ b/lib/xe/xe_spin.c
>> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
>>  	free(spin);
>>  }
>>
>> +struct xe_spin_ctx *
>> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
>> +	      uint16_t width, uint16_t num_placements)
>> +{
>> +	struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
>> +
>> +	igt_assert(width && num_placements &&
>> +		   (width == 1 || num_placements == 1));
>> +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);

I think those asserts are fine for a lib since it would be a programming
error.

>> +
>> +	ctx->class = hwe->engine_class;
>> +	ctx->width = width;
>> +	ctx->num_placements = num_placements;
>> +	ctx->vm = vm;
>> +
>> +	ctx->exec.num_batch_buffer = width;
>> +	ctx->exec.num_syncs = 2;
>> +	ctx->exec.syncs = to_user_pointer(ctx->sync);
>> +
>> +	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> +	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> +	ctx->sync[0].handle = syncobj_create(fd, 0);
>> +
>> +	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> +	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> +	ctx->sync[1].handle = syncobj_create(fd, 0);
>> +
>> +	ctx->bo_size = sizeof(struct xe_spin);
>> +	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
>> +	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
>> +			       vram_if_possible(fd, hwe->gt_id),
>> +			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> +	if (ahnd) {

we need a better set of functions for handling an optional arg like
this.

>> +		for (unsigned int i = 0; i < width; i++)
>> +			ctx->addr[i] = intel_allocator_alloc_with_strategy(ahnd,
>> +					ctx->bo, ctx->bo_size, 0,
>> +					ALLOC_STRATEGY_LOW_TO_HIGH);
>> +	} else {
>> +		for (unsigned int i = 0; i < width; i++)
>> +			ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>> +	}
>> +
>> +	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>> +
>> +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>> +					     hwe, 0, &ctx->exec_queue), 0);

this assert should probably be handled as an error, and let the test do
the assert. This way this can be easily used by others libs and tools. I
was chatting recently with other people that it'd be good to have a
gpu-stress (whatever the name, may be xe-spinner if not generalized) so
we can easily exercise the engines.

>> +
>> +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>> +			 ctx->sync, 1);
>
>@Lucas
>
>I'm looking here and I've doubts what's going on in 'utilization_multi'
>subtest where width > 1. I mean we bind only addr[0], but according
>to exec with width > 1 I assume addr[1] should be bound as well.

we may need to change that to generalize in the lib. In the case of that
specific test we setup the addr per class:

	num_placements = xe_gt_fill_engines_by_class()
	if TEST_PARALLEL {
		width = num_placements
		num_placements = 1
	}
	...
	for (unsigned int i = 0; i < width; i++)
		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;

So if width > 1, all of them point to the same address.
To make it generic I think we will have to change that, yes.

+Matt Brost

Lucas De Marchi

>
>What I'm missing here?
>
>--
>Zbigniew
>
>> +
>> +	return ctx;
>> +}
>> +
>> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx)
>> +{
>> +	if (!ctx)
>> +		return;
>> +
>> +	ctx->spin_opts.addr = ctx->addr[0];
>> +	ctx->spin_opts.write_timestamp = true;
>> +	ctx->spin_opts.preempt = true;
>> +	xe_spin_init(ctx->spin, &ctx->spin_opts);
>> +
>> +	/* re-use sync[0] for exec */
>> +	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> +
>> +	ctx->exec.exec_queue_id = ctx->exec_queue;
>> +
>> +	if (ctx->width > 1)
>> +		ctx->exec.address = to_user_pointer(ctx->addr);
>> +	else
>> +		ctx->exec.address = ctx->addr[0];
>> +
>> +	xe_exec(fd, &ctx->exec);
>> +
>> +	xe_spin_wait_started(ctx->spin);
>> +	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
>> +
>> +	igt_debug("%d: spinner started\n", ctx->class);
>> +}
>> +
>> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx)
>> +{
>> +	if (!ctx || ctx->ended)
>> +		return;
>> +
>> +	xe_spin_end(ctx->spin);
>> +
>> +	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
>> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> +	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> +
>> +	ctx->ended = true;
>> +	igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
>> +		  ctx->spin->timestamp);
>> +}
>> +
>> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx)
>> +{
>> +	if (!ctx)
>> +		return;
>> +
>> +	syncobj_destroy(fd, ctx->sync[0].handle);
>> +	syncobj_destroy(fd, ctx->sync[1].handle);
>> +	xe_exec_queue_destroy(fd, ctx->exec_queue);
>> +
>> +	munmap(ctx->spin, ctx->bo_size);
>> +	gem_close(fd, ctx->bo);
>> +
>> +	free(ctx);
>> +}
>> +
>>  void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>>  		  struct xe_cork *cork)
>>  {
>> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
>> index d65adb05c..18706dcdf 100644
>> --- a/lib/xe/xe_spin.h
>> +++ b/lib/xe/xe_spin.h
>> @@ -43,9 +43,29 @@ struct xe_spin {
>>  	uint32_t timestamp;
>>  };
>>
>> +struct xe_spin_ctx {
>> +	uint32_t vm;
>> +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>> +	struct drm_xe_sync sync[2];
>> +	struct drm_xe_exec exec;
>> +	uint32_t exec_queue;
>> +	size_t bo_size;
>> +	uint32_t bo;
>> +	struct xe_spin *spin;
>> +	struct xe_spin_opts spin_opts;
>> +	bool ended;
>> +	uint16_t class;
>> +	uint16_t width;
>> +	uint16_t num_placements;
>> +};
>> +
>>  igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
>>  uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t ns);
>>  void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
>> +struct xe_spin_ctx *
>> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint64_t ahnd, uint32_t vm,
>> +	      uint16_t width, uint16_t num_placements);
>> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
>>
>>  #define xe_spin_init_opts(fd, ...) \
>>  	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__}))
>> @@ -55,6 +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);
>>  void xe_spin_wait_started(struct xe_spin *spin);
>>  void xe_spin_end(struct xe_spin *spin);
>>  void xe_spin_free(int fd, struct igt_spin *spin);
>> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx);
>> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
>>
>>  struct xe_cork {
>>  	struct xe_spin *spin;
>> diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>> index 5fd7c0416..91ff4a5af 100644
>> --- a/tests/intel/xe_drm_fdinfo.c
>> +++ b/tests/intel/xe_drm_fdinfo.c
>> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
>>  	igt_require(info.num_engines);
>>  }
>>
>> -struct spin_ctx {
>> -	uint32_t vm;
>> -	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
>> -	struct drm_xe_sync sync[2];
>> -	struct drm_xe_exec exec;
>> -	uint32_t exec_queue;
>> -	size_t bo_size;
>> -	uint32_t bo;
>> -	struct xe_spin *spin;
>> -	struct xe_spin_opts spin_opts;
>> -	bool ended;
>> -	uint16_t class;
>> -	uint16_t width;
>> -	uint16_t num_placements;
>> -};
>> -
>> -static struct spin_ctx *
>> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe, uint32_t vm,
>> -	      uint16_t width, uint16_t num_placements)
>> -{
>> -	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
>> -
>> -	igt_assert(width && num_placements &&
>> -		   (width == 1 || num_placements == 1));
>> -	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
>> -
>> -	ctx->class = hwe->engine_class;
>> -	ctx->width = width;
>> -	ctx->num_placements = num_placements;
>> -	ctx->vm = vm;
>> -
>> -	for (unsigned int i = 0; i < width; i++)
>> -		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
>> -
>> -	ctx->exec.num_batch_buffer = width;
>> -	ctx->exec.num_syncs = 2;
>> -	ctx->exec.syncs = to_user_pointer(ctx->sync);
>> -
>> -	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> -	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> -	ctx->sync[0].handle = syncobj_create(fd, 0);
>> -
>> -	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> -	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> -	ctx->sync[1].handle = syncobj_create(fd, 0);
>> -
>> -	ctx->bo_size = sizeof(struct xe_spin);
>> -	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
>> -	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
>> -			       vram_if_possible(fd, hwe->gt_id),
>> -			       DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> -	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
>> -
>> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width, num_placements,
>> -					     hwe, 0, &ctx->exec_queue), 0);
>> -
>> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx->bo_size,
>> -			 ctx->sync, 1);
>> -
>> -	return ctx;
>> -}
>> -
>> -static void
>> -spin_sync_start(int fd, struct spin_ctx *ctx)
>> -{
>> -	if (!ctx)
>> -		return;
>> -
>> -	ctx->spin_opts.addr = ctx->addr[0];
>> -	ctx->spin_opts.write_timestamp = true;
>> -	ctx->spin_opts.preempt = true;
>> -	xe_spin_init(ctx->spin, &ctx->spin_opts);
>> -
>> -	/* re-use sync[0] for exec */
>> -	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>> -
>> -	ctx->exec.exec_queue_id = ctx->exec_queue;
>> -
>> -	if (ctx->width > 1)
>> -		ctx->exec.address = to_user_pointer(ctx->addr);
>> -	else
>> -		ctx->exec.address = ctx->addr[0];
>> -
>> -	xe_exec(fd, &ctx->exec);
>> -
>> -	xe_spin_wait_started(ctx->spin);
>> -	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
>> -
>> -	igt_debug("%s: spinner started\n", engine_map[ctx->class]);
>> -}
>> -
>> -static void
>> -spin_sync_end(int fd, struct spin_ctx *ctx)
>> -{
>> -	if (!ctx || ctx->ended)
>> -		return;
>> -
>> -	xe_spin_end(ctx->spin);
>> -
>> -	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0, NULL));
>> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> -
>> -	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size, ctx->sync, 1);
>> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0, NULL));
>> -
>> -	ctx->ended = true;
>> -	igt_debug("%s: spinner ended (timestamp=%u)\n", engine_map[ctx->class],
>> -		  ctx->spin->timestamp);
>> -}
>> -
>> -static void
>> -spin_ctx_destroy(int fd, struct spin_ctx *ctx)
>> -{
>> -	if (!ctx)
>> -		return;
>> -
>> -	syncobj_destroy(fd, ctx->sync[0].handle);
>> -	syncobj_destroy(fd, ctx->sync[1].handle);
>> -	xe_exec_queue_destroy(fd, ctx->exec_queue);
>> -
>> -	munmap(ctx->spin, ctx->bo_size);
>> -	gem_close(fd, ctx->bo);
>> -
>> -	free(ctx);
>> -}
>> -
>>  static void
>>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
>>  	      int class, int width, enum expected_load expected_load)
>> @@ -535,7 +408,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>  {
>>  	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> -	struct spin_ctx *ctx = NULL;
>> +	struct xe_spin_ctx *ctx = NULL;
>>  	enum expected_load expected_load;
>>  	uint32_t vm;
>>  	int new_fd;
>> @@ -545,8 +418,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>>  	if (flags & TEST_BUSY) {
>> -		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> -		spin_sync_start(fd, ctx);
>> +		ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> +		xe_spin_sync_start(fd, ctx);
>>  	}
>>
>>  	read_engine_cycles(fd, pceu1[0]);
>> @@ -555,7 +428,7 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>
>>  	usleep(batch_duration_usec);
>>  	if (flags & TEST_TRAILING_IDLE)
>> -		spin_sync_end(fd, ctx);
>> +		xe_spin_sync_end(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu2[0]);
>>  	if (flags & TEST_ISOLATION)
>> @@ -574,8 +447,8 @@ utilization_single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned in
>>  		close(new_fd);
>>  	}
>>
>> -	spin_sync_end(fd, ctx);
>> -	spin_ctx_destroy(fd, ctx);
>> +	xe_spin_sync_end(fd, ctx);
>> +	xe_spin_ctx_destroy(fd, ctx);
>>  	xe_vm_destroy(fd, vm);
>>  }
>>
>> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hw
>>  {
>>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> -	struct spin_ctx *ctx = NULL;
>> +	struct xe_spin_ctx *ctx = NULL;
>>  	uint32_t vm;
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> -	spin_sync_start(fd, ctx);
>> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> +	xe_spin_sync_start(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu1);
>>  	usleep(batch_duration_usec);
>>
>>  	/* destroy queue before sampling again */
>> -	spin_sync_end(fd, ctx);
>> -	spin_ctx_destroy(fd, ctx);
>> +	xe_spin_sync_end(fd, ctx);
>> +	xe_spin_ctx_destroy(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu2);
>>
>> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>>  {
>>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> -	struct spin_ctx *ctx = NULL;
>> +	struct xe_spin_ctx *ctx = NULL;
>>  	uint32_t vm;
>>  	int class;
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>>
>> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
>> -	spin_sync_start(fd, ctx);
>> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> +	xe_spin_sync_start(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu1);
>>  	usleep(batch_duration_usec);
>> -	spin_sync_end(fd, ctx);
>> +	xe_spin_sync_end(fd, ctx);
>>  	read_engine_cycles(fd, pceu2);
>>
>>  	xe_for_each_engine_class(class) {
>> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		check_results(pceu1, pceu2, class, 1, expected_load);
>>  	}
>>
>> -	spin_sync_end(fd, ctx);
>> -	spin_ctx_destroy(fd, ctx);
>> +	xe_spin_sync_end(fd, ctx);
>> +	xe_spin_ctx_destroy(fd, ctx);
>>  	xe_vm_destroy(fd, vm);
>>  }
>>
>> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  {
>>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>>  	struct drm_xe_engine_class_instance *_hwe;
>>  	uint32_t vm;
>>  	int class;
>> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  		if (_class == hwe->engine_class || ctx[_class])
>>  			continue;
>>
>> -		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
>> -		spin_sync_start(fd, ctx[_class]);
>> +		ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
>> +		xe_spin_sync_start(fd, ctx[_class]);
>>  	}
>>
>>  	read_engine_cycles(fd, pceu1);
>>  	usleep(batch_duration_usec);
>>  	xe_for_each_engine_class(class)
>> -		spin_sync_end(fd, ctx[class]);
>> +		xe_spin_sync_end(fd, ctx[class]);
>>  	read_engine_cycles(fd, pceu2);
>>
>>  	xe_for_each_engine_class(class) {
>> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct drm_xe_engine_class_instance *hwe)
>>  			continue;
>>
>>  		check_results(pceu1, pceu2, class, 1, expected_load);
>> -		spin_sync_end(fd, ctx[class]);
>> -		spin_ctx_destroy(fd, ctx[class]);
>> +		xe_spin_sync_end(fd, ctx[class]);
>> +		xe_spin_ctx_destroy(fd, ctx[class]);
>>  	}
>>
>>  	xe_vm_destroy(fd, vm);
>> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd)
>>  {
>>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>>  	struct drm_xe_engine_class_instance *hwe;
>>  	uint32_t vm;
>>  	int class;
>> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
>>  		if (ctx[class])
>>  			continue;
>>
>> -		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
>> -		spin_sync_start(fd, ctx[class]);
>> +		ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
>> +		xe_spin_sync_start(fd, ctx[class]);
>>  	}
>>
>>  	read_engine_cycles(fd, pceu1);
>>  	usleep(batch_duration_usec);
>>  	xe_for_each_engine_class(class)
>> -		spin_sync_end(fd, ctx[class]);
>> +		xe_spin_sync_end(fd, ctx[class]);
>>  	read_engine_cycles(fd, pceu2);
>>
>>  	xe_for_each_engine_class(class) {
>> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
>>  			continue;
>>
>>  		check_results(pceu1, pceu2, class, 1, EXPECTED_LOAD_FULL);
>> -		spin_sync_end(fd, ctx[class]);
>> -		spin_ctx_destroy(fd, ctx[class]);
>> +		xe_spin_sync_end(fd, ctx[class]);
>> +		xe_spin_ctx_destroy(fd, ctx[class]);
>>  	}
>>
>>  	xe_vm_destroy(fd, vm);
>> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>  	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct pceu_cycles pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
>>  	struct drm_xe_engine_class_instance eci[XE_MAX_ENGINE_INSTANCE];
>> -	struct spin_ctx *ctx = NULL;
>> +	struct xe_spin_ctx *ctx = NULL;
>>  	enum expected_load expected_load;
>>  	int fd_spill, num_placements;
>>  	uint32_t vm;
>> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>
>>  	vm = xe_vm_create(fd, 0, 0);
>>  	if (flags & TEST_BUSY) {
>> -		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
>> -		spin_sync_start(fd, ctx);
>> +		ctx = xe_spin_ctx_init(fd, eci, 0, vm, width, num_placements);
>> +		xe_spin_sync_start(fd, ctx);
>>  	}
>>
>>  	read_engine_cycles(fd, pceu[0]);
>> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>
>>  	usleep(batch_duration_usec);
>>  	if (flags & TEST_TRAILING_IDLE)
>> -		spin_sync_end(fd, ctx);
>> +		xe_spin_sync_end(fd, ctx);
>>
>>  	read_engine_cycles(fd, pceu[1]);
>>  	if (flags & TEST_ISOLATION)
>> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int flags)
>>  		close(fd_spill);
>>  	}
>>
>> -	spin_sync_end(fd, ctx);
>> -	spin_ctx_destroy(fd, ctx);
>> +	xe_spin_sync_end(fd, ctx);
>> +	xe_spin_ctx_destroy(fd, ctx);
>>
>>  	xe_vm_destroy(fd, vm);
>>  }
>> --
>> 2.34.1
>>

✗ CI.xeFULL: failure for tests/xe_spin_batch: Add spin-timestamp-check (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 75001 bytes --]

== Series Details ==

Series: tests/xe_spin_batch: Add spin-timestamp-check (rev3)
URL   : https://patchwork.freedesktop.org/series/140933/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8100_full -> XEIGTPW_12069_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12069_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12069_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12069_full:

### IGT changes ###

#### Possible regressions ####

  * igt@core_getversion@all-cards:
    - shard-dg2-set2:     [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@core_getversion@all-cards.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@core_getversion@all-cards.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_flip@flip-vs-rmfb@c-dp2:
    - shard-bmg:          [PASS][4] -> [INCOMPLETE][5] +1 other test incomplete
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-7/igt@kms_flip@flip-vs-rmfb@c-dp2.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-7/igt@kms_flip@flip-vs-rmfb@c-dp2.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  
New tests
---------

  New tests have been introduced between XEIGT_8100_full and XEIGTPW_12069_full:

### New IGT tests (8) ###

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@d-dp5:
    - Statuses : 1 pass(s)
    - Exec time: [4.31] s

  * igt@kms_vblank@wait-forked-busy-hang@pipe-d-dp-5:
    - Statuses : 1 pass(s)
    - Exec time: [2.41] s

  * igt@xe_spin_batch@spin-timestamp-check:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 8.03] s

  * igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_compute:
    - Statuses : 2 pass(s)
    - Exec time: [1.14, 1.15] s

  * igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_copy:
    - Statuses : 2 pass(s)
    - Exec time: [1.15, 1.16] s

  * igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_render:
    - Statuses : 2 pass(s)
    - Exec time: [1.12, 1.14] s

  * igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_video_decode:
    - Statuses : 2 pass(s)
    - Exec time: [1.16, 2.30] s

  * igt@xe_spin_batch@spin-timestamp-check@engine-drm_xe_engine_class_video_enhance:
    - Statuses : 2 pass(s)
    - Exec time: [1.15, 2.30] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_12069_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotreplug:
    - shard-dg2-set2:     [PASS][7] -> [SKIP][8] ([Intel XE#1885])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@core_hotunplug@hotreplug.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@core_hotunplug@hotreplug.html

  * igt@core_hotunplug@hotreplug-lateclose:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#1885])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@core_hotunplug@hotreplug-lateclose.html

  * igt@fbdev@write:
    - shard-dg2-set2:     [PASS][10] -> [SKIP][11] ([Intel XE#2134]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@fbdev@write.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@fbdev@write.html

  * igt@kms_async_flips@crc:
    - shard-bmg:          [PASS][12] -> [DMESG-WARN][13] ([Intel XE#877]) +1 other test dmesg-warn
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-7/igt@kms_async_flips@crc.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-2/igt@kms_async_flips@crc.html

  * igt@kms_atomic@plane-invalid-params-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#2423] / [i915#2575]) +49 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_atomic@plane-invalid-params-fence.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-lnl:          NOTRUN -> [FAIL][15] ([Intel XE#1701]) +1 other test fail
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-lnl:          [PASS][16] -> [FAIL][17] ([Intel XE#1701]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [PASS][18] -> [FAIL][19] ([Intel XE#1426]) +1 other test fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-lnl:          NOTRUN -> [FAIL][20] ([Intel XE#1426]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#316]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#1407])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-3/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-bmg:          [PASS][23] -> [INCOMPLETE][24] ([Intel XE#3225])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-4/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#1124]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#1124]) +18 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#2191])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#2191])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#367])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-6/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#367]) +7 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#787]) +106 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-dp-5:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#455] / [Intel XE#787]) +31 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-dp-5.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#2887]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2:
    - shard-bmg:          [PASS][35] -> [FAIL][36] ([Intel XE#2436]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-dp-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#2669]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][38] ([Intel XE#1195])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#2907]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#314])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#373]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2325])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-5/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#306]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#373]) +10 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2252])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-6/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_color@ctm-0-75@pipe-b-edp-1:
    - shard-lnl:          [PASS][46] -> [DMESG-WARN][47] ([Intel XE#2929]) +1 other test dmesg-warn
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-5/igt@kms_color@ctm-0-75@pipe-b-edp-1.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-3/igt@kms_color@ctm-0-75@pipe-b-edp-1.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][48] ([Intel XE#3304])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][49] ([Intel XE#1178]) +5 other tests fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1424])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-3/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#308]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2321]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#2321])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-6/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#309]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#323]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
    - shard-lnl:          [PASS][56] -> [FAIL][57] ([Intel XE#1541])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1421])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][59] ([Intel XE#886]) +1 other test fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3:
    - shard-bmg:          [PASS][60] -> [FAIL][61] ([Intel XE#301]) +4 other tests fail
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible:
    - shard-lnl:          [PASS][62] -> [FAIL][63] ([Intel XE#886]) +3 other tests fail
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-1/igt@kms_flip@wf_vblank-ts-check-interruptible.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-4/igt@kms_flip@wf_vblank-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-dg2-set2:     [PASS][64] -> [SKIP][65] ([Intel XE#2890]) +32 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#455]) +22 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-edp-1-x-to-linear:
    - shard-lnl:          [PASS][67] -> [FAIL][68] ([Intel XE#1491]) +2 other tests fail
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-edp-1-x-to-linear.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-edp-1-x-to-linear.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#651]) +35 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2311]) +6 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#651])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][72] -> [SKIP][73] ([Intel XE#2351] / [Intel XE#2890]) +10 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [FAIL][74] ([Intel XE#2333]) +1 other test fail
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#656]) +8 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2313]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#2351] / [Intel XE#2890]) +15 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#653]) +32 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#605])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][80] ([Intel XE#3312]) +1 other test fail
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-6.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][81] -> [ABORT][82] ([Intel XE#2625]) +1 other test abort
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][83] ([Intel XE#2927])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#346])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][85] ([Intel XE#616]) +3 other tests fail
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats:
    - shard-dg2-set2:     [PASS][86] -> [SKIP][87] ([Intel XE#2423] / [i915#2575]) +77 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#870])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][89] -> [FAIL][90] ([Intel XE#718])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          [PASS][91] -> [FAIL][92] ([Intel XE#1430])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#2446]) +4 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2-set2:     [PASS][94] -> [SKIP][95] ([Intel XE#2446]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#1489])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#2893])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-6/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][98] ([Intel XE#1489]) +5 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#1122])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][100] ([Intel XE#2890]) +44 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@pr-sprite-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1406]) +2 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-4/igt@kms_psr@pr-sprite-plane-move.html

  * igt@kms_psr@psr2-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#2850] / [Intel XE#929]) +19 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@kms_psr@psr2-basic.html

  * igt@kms_psr@psr2-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-4/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][104] ([Intel XE#1127])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     NOTRUN -> [FAIL][105] ([Intel XE#1729])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-lnl:          [PASS][106] -> [FAIL][107] ([Intel XE#899]) +1 other test fail
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-1/igt@kms_universal_plane@cursor-fb-leak.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][108] -> [FAIL][109] ([Intel XE#2159]) +1 other test fail
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][110] ([Intel XE#756])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_writeback@writeback-fb-id.html

  * igt@xe_ccs@ctrl-surf-copy-new-ctx:
    - shard-dg2-set2:     NOTRUN -> [SKIP][111] ([Intel XE#1130]) +76 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_ccs@ctrl-surf-copy-new-ctx.html

  * igt@xe_copy_basic@mem-copy-linear-0x369:
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#1123]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0x369.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#1126]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eudebug@basic-client:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#2905]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@xe_eudebug@basic-client.html

  * igt@xe_eudebug@multiple-sessions:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#2905]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-5/igt@xe_eudebug@multiple-sessions.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][116] ([Intel XE#2905]) +16 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_evict@evict-mixed-many-threads-large:
    - shard-dg2-set2:     NOTRUN -> [FAIL][117] ([Intel XE#1000])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@xe_evict@evict-mixed-many-threads-large.html

  * igt@xe_evict@evict-mixed-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#688]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@xe_evict@evict-mixed-threads-small-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
    - shard-bmg:          [PASS][119] -> [FAIL][120] ([Intel XE#3198])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-7/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-4/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html

  * igt@xe_exec_balancer@once-parallel-rebind:
    - shard-dg2-set2:     [PASS][121] -> [SKIP][122] ([Intel XE#1130]) +161 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@xe_exec_balancer@once-parallel-rebind.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_exec_balancer@once-parallel-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#1392])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-mmap.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][124] ([Intel XE#2322])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@xe_exec_basic@multigpu-once-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          [PASS][125] -> [FAIL][126] ([Intel XE#1630])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][127] ([Intel XE#288]) +27 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html

  * igt@xe_gt_freq@freq_reset_multiple:
    - shard-lnl:          [PASS][128] -> [DMESG-WARN][129] ([Intel XE#3184])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-2/igt@xe_gt_freq@freq_reset_multiple.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-3/igt@xe_gt_freq@freq_reset_multiple.html

  * igt@xe_oa@polling-small-buf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][130] ([Intel XE#2541]) +5 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@xe_oa@polling-small-buf.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#1337])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xe2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][132] ([Intel XE#2839] / [Intel XE#977])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][133] ([Intel XE#2284] / [Intel XE#366])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-dg2-set2:     [PASS][134] -> [ABORT][135] ([Intel XE#1794])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@xe_pm@s4-vm-bind-unbind-all.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-lnl:          NOTRUN -> [SKIP][136] ([Intel XE#944])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-4/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#944])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-2/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#944]) +3 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_wedged@basic-wedged:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][139] ([Intel XE#2919])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][140] ([Intel XE#1195]) -> [PASS][141] +1 other test pass
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][142] ([Intel XE#1195] / [Intel XE#3124]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][144] -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_color@ctm-0-50@pipe-c-edp-1:
    - shard-lnl:          [DMESG-WARN][146] ([Intel XE#2929]) -> [PASS][147] +1 other test pass
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-8/igt@kms_color@ctm-0-50@pipe-c-edp-1.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_color@ctm-0-50@pipe-c-edp-1.html

  * igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-edp-1:
    - shard-lnl:          [FAIL][148] ([Intel XE#2577]) -> [PASS][149] +1 other test pass
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-4/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-edp-1.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-1/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-edp-1.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-bmg:          [DMESG-WARN][150] ([Intel XE#877]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [FAIL][152] ([Intel XE#1475]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
    - shard-lnl:          [FAIL][154] ([Intel XE#1475]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][156] ([Intel XE#301]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-lnl:          [FAIL][158] ([Intel XE#886]) -> [PASS][159] +7 other tests pass
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-7/igt@kms_flip@blocking-wf_vblank.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-5/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_lease@lease-uevent:
    - shard-lnl:          [FAIL][160] -> [PASS][161] +1 other test pass
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-5/igt@kms_lease@lease-uevent.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_lease@lease-uevent.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race:
    - shard-lnl:          [FAIL][162] ([Intel XE#1630]) -> [PASS][163] +3 other tests pass
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-userptr-invalidate-race:
    - shard-bmg:          [FAIL][164] ([Intel XE#1630]) -> [PASS][165] +3 other tests pass
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-4/igt@xe_exec_fault_mode@many-userptr-invalidate-race.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-2/igt@xe_exec_fault_mode@many-userptr-invalidate-race.html

  * igt@xe_module_load@reload:
    - shard-dg2-set2:     [FAIL][166] ([Intel XE#2136]) -> [PASS][167]
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@xe_module_load@reload.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-466/igt@xe_module_load@reload.html
    - shard-bmg:          [FAIL][168] ([Intel XE#2136]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-bmg-6/igt@xe_module_load@reload.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-bmg-6/igt@xe_module_load@reload.html

  * igt@xe_pm@s2idle-mocs:
    - shard-lnl:          [DMESG-WARN][170] ([Intel XE#2932]) -> [PASS][171]
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-3/igt@xe_pm@s2idle-mocs.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-6/igt@xe_pm@s2idle-mocs.html

  * igt@xe_pm@s2idle-vm-bind-prefetch:
    - shard-dg2-set2:     [ABORT][172] ([Intel XE#1694]) -> [PASS][173]
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@xe_pm@s2idle-vm-bind-prefetch.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-433/igt@xe_pm@s2idle-vm-bind-prefetch.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [ABORT][174] ([Intel XE#1794]) -> [PASS][175]
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-2/igt@xe_pm@s4-mocs.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-6/igt@xe_pm@s4-mocs.html

  
#### Warnings ####

  * igt@kms_big_fb@linear-64bpp-rotate-180:
    - shard-dg2-set2:     [DMESG-WARN][176] ([Intel XE#877]) -> [SKIP][177] ([Intel XE#2351] / [Intel XE#2890])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_big_fb@linear-64bpp-rotate-180.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@linear-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][178] ([Intel XE#316]) -> [SKIP][179] ([Intel XE#2890]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][180] ([Intel XE#316]) -> [SKIP][181] ([Intel XE#2351] / [Intel XE#2890]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-dg2-set2:     [SKIP][182] ([Intel XE#1124]) -> [SKIP][183] ([Intel XE#2890]) +4 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-dg2-set2:     [SKIP][184] ([Intel XE#610]) -> [SKIP][185] ([Intel XE#2890]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][186] ([Intel XE#1124]) -> [SKIP][187] ([Intel XE#2351] / [Intel XE#2890]) +4 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-435/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-dg2-set2:     [SKIP][188] ([Intel XE#2191]) -> [SKIP][189] ([Intel XE#2423] / [i915#2575])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][190] ([Intel XE#367]) -> [SKIP][191] ([Intel XE#2423] / [i915#2575]) +6 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][192] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][193] ([Intel XE#2351] / [Intel XE#2890]) +2 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][194] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][195] ([Intel XE#2890]) +10 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][196] ([Intel XE#1195] / [Intel XE#1727]) -> [SKIP][197] ([Intel XE#2890])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#373]) -> [SKIP][199] ([Intel XE#2423] / [i915#2575]) +13 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#307]) -> [SKIP][201] ([Intel XE#2423] / [i915#2575])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_content_protection@dp-mst-type-1.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#455]) -> [SKIP][203] ([Intel XE#2351])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_dsc@dsc-basic.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#455]) -> [SKIP][205] ([Intel XE#2351] / [Intel XE#2890]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@kms_dsc@dsc-with-formats.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#776]) -> [SKIP][207] ([Intel XE#2890])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_fbcon_fbt@psr-suspend.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#701]) -> [SKIP][209] ([Intel XE#2423] / [i915#2575])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_feature_discovery@chamelium.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#1137]) -> [SKIP][211] ([Intel XE#2423] / [i915#2575])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@kms_feature_discovery@dp-mst.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-dg2-set2:     [FAIL][212] ([Intel XE#301]) -> [SKIP][213] ([Intel XE#2423] / [i915#2575])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@bo-too-big-interruptible@a-edp1:
    - shard-lnl:          [TIMEOUT][214] ([Intel XE#1504]) -> [INCOMPLETE][215] ([Intel XE#1504]) +1 other test incomplete
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-7/igt@kms_flip@bo-too-big-interruptible@a-edp1.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-7/igt@kms_flip@bo-too-big-interruptible@a-edp1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-lnl:          [FAIL][216] ([Intel XE#886]) -> [FAIL][217] ([Intel XE#3403] / [Intel XE#886])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-lnl-1/igt@kms_flip@wf_vblank-ts-check.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#651]) -> [SKIP][219] ([Intel XE#2890]) +21 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     [SKIP][220] ([Intel XE#651]) -> [SKIP][221] ([Intel XE#2351] / [Intel XE#2890]) +9 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-slowdraw:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#653]) -> [SKIP][223] ([Intel XE#2351] / [Intel XE#2890]) +6 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-dg2-set2:     [SKIP][224] ([Intel XE#658]) -> [SKIP][225] ([Intel XE#2351] / [Intel XE#2890])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][226] ([Intel XE#653]) -> [SKIP][227] ([Intel XE#2890]) +20 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2-set2:     [FAIL][228] ([Intel XE#3312]) -> [FAIL][229] ([Intel XE#3312] / [Intel XE#3404])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_hdr@brightness-with-hdr.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-464/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#2925]) -> [SKIP][231] ([Intel XE#2890])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#2927]) -> [SKIP][233] ([Intel XE#2890])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_joiner@invalid-modeset-ultra-joiner.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-dg2-set2:     [SKIP][234] ([Intel XE#455]) -> [SKIP][235] ([Intel XE#2423] / [i915#2575]) +8 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@kms_plane_lowres@tiling-y.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
    - shard-dg2-set2:     [SKIP][236] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][237] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-435/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-dg2-set2:     [SKIP][238] ([Intel XE#870]) -> [SKIP][239] ([Intel XE#2890])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_pm_backlight@basic-brightness.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2-set2:     [SKIP][240] ([Intel XE#2938]) -> [SKIP][241] ([Intel XE#2890])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_pm_backlight@brightness-with-dpms.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-set2:     [SKIP][242] ([Intel XE#1122]) -> [SKIP][243] ([Intel XE#2351] / [Intel XE#2890])
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][244] ([Intel XE#1489]) -> [SKIP][245] ([Intel XE#2890]) +10 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr@psr-cursor-plane-move:
    - shard-dg2-set2:     [SKIP][246] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][247] ([Intel XE#2351])
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_psr@psr-cursor-plane-move.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr@psr-cursor-plane-move.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     [SKIP][248] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][249] ([Intel XE#2351] / [Intel XE#2890]) +5 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@kms_psr@psr-dpms.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr2-primary-render:
    - shard-dg2-set2:     [SKIP][250] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][251] ([Intel XE#2890]) +8 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@kms_psr@psr2-primary-render.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr@psr2-primary-render.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2-set2:     [SKIP][252] ([Intel XE#2939]) -> [SKIP][253] ([Intel XE#2351] / [Intel XE#2890])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     [SKIP][254] -> [SKIP][255] ([Intel XE#2423] / [i915#2575])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_rotation_crc@bad-tiling.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     [SKIP][256] ([Intel XE#1127]) -> [SKIP][257] ([Intel XE#2423] / [i915#2575])
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][258] ([Intel XE#362]) -> [SKIP][259] ([Intel XE#1500])
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-set2:     [SKIP][260] ([Intel XE#756]) -> [SKIP][261] ([Intel XE#2423] / [i915#2575])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@kms_writeback@writeback-check-output.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@kms_writeback@writeback-check-output.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2-set2:     [SKIP][262] ([Intel XE#1091] / [Intel XE#2849]) -> [SKIP][263] ([Intel XE#2423] / [i915#2575])
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt:
    - shard-dg2-set2:     [SKIP][264] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][265] ([Intel XE#1130])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@xe_compute_preempt@compute-threadgroup-preempt.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_compute_preempt@compute-threadgroup-preempt.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#1123]) -> [SKIP][267] ([Intel XE#1130])
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-464/igt@xe_copy_basic@mem-copy-linear-0x3fff.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_eudebug_online@resume-dss:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#2905]) -> [SKIP][269] ([Intel XE#1130]) +11 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@xe_eudebug_online@resume-dss.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_eudebug_online@resume-dss.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][270] ([Intel XE#1600]) -> [SKIP][271] ([Intel XE#1130]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#288]) -> [SKIP][273] ([Intel XE#1130]) +25 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     [SKIP][274] ([Intel XE#2360]) -> [SKIP][275] ([Intel XE#1130])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-dg2-set2:     [ABORT][276] ([Intel XE#2625]) -> [SKIP][277] ([Intel XE#1130])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@xe_gt_freq@freq_suspend.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#512]) -> [SKIP][279] ([Intel XE#1130])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-466/igt@xe_mmap@small-bar.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_mmap@small-bar.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     [SKIP][280] ([Intel XE#2541]) -> [SKIP][281] ([Intel XE#1130]) +5 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [FAIL][282] ([Intel XE#1173]) -> [SKIP][283] ([Intel XE#1061])
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-433/igt@xe_peer2peer@write.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_peer2peer@write.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][285] ([Intel XE#1130]) +1 other test skip
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s2idle-basic:
    - shard-dg2-set2:     [ABORT][286] ([Intel XE#1358] / [Intel XE#1794]) -> [SKIP][287] ([Intel XE#1130])
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-432/igt@xe_pm@s2idle-basic.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_pm@s2idle-basic.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-dg2-set2:     [SKIP][288] ([Intel XE#944]) -> [SKIP][289] ([Intel XE#1130]) +1 other test skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-463/igt@xe_query@multigpu-query-invalid-extension.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     [SKIP][290] ([Intel XE#3342]) -> [SKIP][291] ([Intel XE#1130])
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8100/shard-dg2-434/igt@xe_sriov_flr@flr-each-isolation.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/shard-dg2-434/igt@xe_sriov_flr@flr-each-isolation.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1491]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1491
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
  [Intel XE#1541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1541
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1630]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1630
  [Intel XE#1694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1694
  [Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2436]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2436
  [Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2577
  [Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2839]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2839
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2890
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2919]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2919
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2929
  [Intel XE#2932]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2932
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
  [Intel XE#3198]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3198
  [Intel XE#3225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3225
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3312
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3403]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3403
  [Intel XE#3404]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3404
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * IGT: IGT_8100 -> IGTPW_12069
  * Linux: xe-2179-438ef86a725b59a171dba81fc258bb23a0ff536c -> xe-2188-5f445c6723de9ac7087170f4ee8fcb2050ab8346

  IGTPW_12069: 12069
  IGT_8100: 84e42580f918da926481fd2fb37be01451d6ee9a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2179-438ef86a725b59a171dba81fc258bb23a0ff536c: 438ef86a725b59a171dba81fc258bb23a0ff536c
  xe-2188-5f445c6723de9ac7087170f4ee8fcb2050ab8346: 5f445c6723de9ac7087170f4ee8fcb2050ab8346

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12069/index.html

[-- Attachment #2: Type: text/html, Size: 91272 bytes --]

RE: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib

[Gurram, Pravalika]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Friday, November 8, 2024 9:09 PM
> To: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Cc: Gurram, Pravalika <pravalika.gurram@intel.com>; igt-
> dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
> Subject: Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions
> to lib
> 
> On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
> >+Lucas
> 
> Pravalika, please keep me in Cc. I don't watch the igt mailing list close
> enough, particularly when it's a follow up to a suggestion I gave.
> 
> >
> >On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
> >> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
> >> to xe spin lib to avoid code redundancy.
> >>
> >> v2: use allocator based on developer preference.
> >>     change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
> 
> but we already have another thing named ctx there, the rename doesn't
> improve it.
> 
>  From lib/xe/xe_spin.h, what should be added on is
> 
> struct xe_cork {
> 	struct xe_spin *spin;
> 	int fd;
> 	uint32_t vm;
> 	uint32_t bo;
> 	uint32_t exec_queue;
> 	uint32_t syncobj;
> };
> 
> I don't really like that name, but we can do a rename on top... or we can
> rename it now and then move things.
> 

could you please suggest the name in place of xe_cork

-- Pravalika
> >>
> >> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> >> ---
> >>  lib/xe/xe_spin.c            | 115 +++++++++++++++++++++
> >>  lib/xe/xe_spin.h            |  22 ++++
> >>  tests/intel/xe_drm_fdinfo.c | 197
> >> +++++++-----------------------------
> >>  3 files changed, 172 insertions(+), 162 deletions(-)
> >>
> >> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index
> >> 3adacc3a8..b611ac5c1 100644
> >> --- a/lib/xe/xe_spin.c
> >> +++ b/lib/xe/xe_spin.c
> >> @@ -292,6 +292,121 @@ void xe_spin_free(int fd, struct igt_spin *spin)
> >>  	free(spin);
> >>  }
> >>
> >> +struct xe_spin_ctx *
> >> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint64_t ahnd, uint32_t vm,
> >> +	      uint16_t width, uint16_t num_placements) {
> >> +	struct xe_spin_ctx *ctx = calloc(1, sizeof(*ctx));
> >> +
> >> +	igt_assert(width && num_placements &&
> >> +		   (width == 1 || num_placements == 1));
> >> +	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> 
> I think those asserts are fine for a lib since it would be a programming error.
> 
> >> +
> >> +	ctx->class = hwe->engine_class;
> >> +	ctx->width = width;
> >> +	ctx->num_placements = num_placements;
> >> +	ctx->vm = vm;
> >> +
> >> +	ctx->exec.num_batch_buffer = width;
> >> +	ctx->exec.num_syncs = 2;
> >> +	ctx->exec.syncs = to_user_pointer(ctx->sync);
> >> +
> >> +	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> +	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> +	ctx->sync[0].handle = syncobj_create(fd, 0);
> >> +
> >> +	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> +	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> +	ctx->sync[1].handle = syncobj_create(fd, 0);
> >> +
> >> +	ctx->bo_size = sizeof(struct xe_spin);
> >> +	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> >> +	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> >> +			       vram_if_possible(fd, hwe->gt_id),
> >> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> >> +	if (ahnd) {
> 
> we need a better set of functions for handling an optional arg like this.
> 
> >> +		for (unsigned int i = 0; i < width; i++)
> >> +			ctx->addr[i] =
> intel_allocator_alloc_with_strategy(ahnd,
> >> +					ctx->bo, ctx->bo_size, 0,
> >> +					ALLOC_STRATEGY_LOW_TO_HIGH);
> >> +	} else {
> >> +		for (unsigned int i = 0; i < width; i++)
> >> +			ctx->addr[i] = 0x100000 + 0x100000 * hwe-
> >engine_class;
> >> +	}
> >> +
> >> +	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> >> +
> >> +	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width,
> num_placements,
> >> +					     hwe, 0, &ctx->exec_queue), 0);
> 
> this assert should probably be handled as an error, and let the test do the
> assert. This way this can be easily used by others libs and tools. I was chatting
> recently with other people that it'd be good to have a gpu-stress (whatever
> the name, may be xe-spinner if not generalized) so we can easily exercise
> the engines.
> 
> >> +
> >> +	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx-
> >bo_size,
> >> +			 ctx->sync, 1);
> >
> >@Lucas
> >
> >I'm looking here and I've doubts what's going on in 'utilization_multi'
> >subtest where width > 1. I mean we bind only addr[0], but according to
> >exec with width > 1 I assume addr[1] should be bound as well.
> 
> we may need to change that to generalize in the lib. In the case of that
> specific test we setup the addr per class:
> 
> 	num_placements = xe_gt_fill_engines_by_class()
> 	if TEST_PARALLEL {
> 		width = num_placements
> 		num_placements = 1
> 	}
> 	...
> 	for (unsigned int i = 0; i < width; i++)
> 		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> 
> So if width > 1, all of them point to the same address.
> To make it generic I think we will have to change that, yes.
> 
> +Matt Brost
> 
> Lucas De Marchi
> 
> >
> >What I'm missing here?
> >
> >--
> >Zbigniew
> >
> >> +
> >> +	return ctx;
> >> +}
> >> +
> >> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx) {
> >> +	if (!ctx)
> >> +		return;
> >> +
> >> +	ctx->spin_opts.addr = ctx->addr[0];
> >> +	ctx->spin_opts.write_timestamp = true;
> >> +	ctx->spin_opts.preempt = true;
> >> +	xe_spin_init(ctx->spin, &ctx->spin_opts);
> >> +
> >> +	/* re-use sync[0] for exec */
> >> +	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >> +
> >> +	ctx->exec.exec_queue_id = ctx->exec_queue;
> >> +
> >> +	if (ctx->width > 1)
> >> +		ctx->exec.address = to_user_pointer(ctx->addr);
> >> +	else
> >> +		ctx->exec.address = ctx->addr[0];
> >> +
> >> +	xe_exec(fd, &ctx->exec);
> >> +
> >> +	xe_spin_wait_started(ctx->spin);
> >> +	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> >> +
> >> +	igt_debug("%d: spinner started\n", ctx->class); }
> >> +
> >> +void xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx) {
> >> +	if (!ctx || ctx->ended)
> >> +		return;
> >> +
> >> +	xe_spin_end(ctx->spin);
> >> +
> >> +	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0,
> NULL));
> >> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> >> +NULL));
> >> +
> >> +	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >> +	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size,
> ctx->sync, 1);
> >> +	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> >> +NULL));
> >> +
> >> +	ctx->ended = true;
> >> +	igt_debug("%d: spinner ended (timestamp=%u)\n", ctx->class,
> >> +		  ctx->spin->timestamp);
> >> +}
> >> +
> >> +void xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx) {
> >> +	if (!ctx)
> >> +		return;
> >> +
> >> +	syncobj_destroy(fd, ctx->sync[0].handle);
> >> +	syncobj_destroy(fd, ctx->sync[1].handle);
> >> +	xe_exec_queue_destroy(fd, ctx->exec_queue);
> >> +
> >> +	munmap(ctx->spin, ctx->bo_size);
> >> +	gem_close(fd, ctx->bo);
> >> +
> >> +	free(ctx);
> >> +}
> >> +
> >>  void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> >>  		  struct xe_cork *cork)
> >>  {
> >> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index
> >> d65adb05c..18706dcdf 100644
> >> --- a/lib/xe/xe_spin.h
> >> +++ b/lib/xe/xe_spin.h
> >> @@ -43,9 +43,29 @@ struct xe_spin {
> >>  	uint32_t timestamp;
> >>  };
> >>
> >> +struct xe_spin_ctx {
> >> +	uint32_t vm;
> >> +	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> >> +	struct drm_xe_sync sync[2];
> >> +	struct drm_xe_exec exec;
> >> +	uint32_t exec_queue;
> >> +	size_t bo_size;
> >> +	uint32_t bo;
> >> +	struct xe_spin *spin;
> >> +	struct xe_spin_opts spin_opts;
> >> +	bool ended;
> >> +	uint16_t class;
> >> +	uint16_t width;
> >> +	uint16_t num_placements;
> >> +};
> >> +
> >>  igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory
> >> *opt);  uint32_t duration_to_ctx_ticks(int fd, int gt_id, uint64_t
> >> ns);  void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts
> >> *opts);
> >> +struct xe_spin_ctx *
> >> +xe_spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint64_t ahnd, uint32_t vm,
> >> +	      uint16_t width, uint16_t num_placements); void
> >> +xe_spin_ctx_destroy(int fd, struct xe_spin_ctx *ctx);
> >>
> >>  #define xe_spin_init_opts(fd, ...) \
> >>  	xe_spin_init(fd, &((struct xe_spin_opts){__VA_ARGS__})) @@ -55,6
> >> +75,8 @@ void xe_spin_sync_wait(int fd, struct igt_spin *spin);  void
> >> xe_spin_wait_started(struct xe_spin *spin);  void xe_spin_end(struct
> >> xe_spin *spin);  void xe_spin_free(int fd, struct igt_spin *spin);
> >> +void xe_spin_sync_start(int fd, struct xe_spin_ctx *ctx); void
> >> +xe_spin_sync_end(int fd, struct xe_spin_ctx *ctx);
> >>
> >>  struct xe_cork {
> >>  	struct xe_spin *spin;
> >> diff --git a/tests/intel/xe_drm_fdinfo.c
> >> b/tests/intel/xe_drm_fdinfo.c index 5fd7c0416..91ff4a5af 100644
> >> --- a/tests/intel/xe_drm_fdinfo.c
> >> +++ b/tests/intel/xe_drm_fdinfo.c
> >> @@ -367,133 +367,6 @@ static void basic_engine_utilization(int xe)
> >>  	igt_require(info.num_engines);
> >>  }
> >>
> >> -struct spin_ctx {
> >> -	uint32_t vm;
> >> -	uint64_t addr[XE_MAX_ENGINE_INSTANCE];
> >> -	struct drm_xe_sync sync[2];
> >> -	struct drm_xe_exec exec;
> >> -	uint32_t exec_queue;
> >> -	size_t bo_size;
> >> -	uint32_t bo;
> >> -	struct xe_spin *spin;
> >> -	struct xe_spin_opts spin_opts;
> >> -	bool ended;
> >> -	uint16_t class;
> >> -	uint16_t width;
> >> -	uint16_t num_placements;
> >> -};
> >> -
> >> -static struct spin_ctx *
> >> -spin_ctx_init(int fd, struct drm_xe_engine_class_instance *hwe,
> uint32_t vm,
> >> -	      uint16_t width, uint16_t num_placements)
> >> -{
> >> -	struct spin_ctx *ctx = calloc(1, sizeof(*ctx));
> >> -
> >> -	igt_assert(width && num_placements &&
> >> -		   (width == 1 || num_placements == 1));
> >> -	igt_assert_lt(width, XE_MAX_ENGINE_INSTANCE);
> >> -
> >> -	ctx->class = hwe->engine_class;
> >> -	ctx->width = width;
> >> -	ctx->num_placements = num_placements;
> >> -	ctx->vm = vm;
> >> -
> >> -	for (unsigned int i = 0; i < width; i++)
> >> -		ctx->addr[i] = 0x100000 + 0x100000 * hwe->engine_class;
> >> -
> >> -	ctx->exec.num_batch_buffer = width;
> >> -	ctx->exec.num_syncs = 2;
> >> -	ctx->exec.syncs = to_user_pointer(ctx->sync);
> >> -
> >> -	ctx->sync[0].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> -	ctx->sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> -	ctx->sync[0].handle = syncobj_create(fd, 0);
> >> -
> >> -	ctx->sync[1].type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> >> -	ctx->sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> >> -	ctx->sync[1].handle = syncobj_create(fd, 0);
> >> -
> >> -	ctx->bo_size = sizeof(struct xe_spin);
> >> -	ctx->bo_size = xe_bb_size(fd, ctx->bo_size);
> >> -	ctx->bo = xe_bo_create(fd, ctx->vm, ctx->bo_size,
> >> -			       vram_if_possible(fd, hwe->gt_id),
> >> -
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> >> -	ctx->spin = xe_bo_map(fd, ctx->bo, ctx->bo_size);
> >> -
> >> -	igt_assert_eq(__xe_exec_queue_create(fd, ctx->vm, width,
> num_placements,
> >> -					     hwe, 0, &ctx->exec_queue), 0);
> >> -
> >> -	xe_vm_bind_async(fd, ctx->vm, 0, ctx->bo, 0, ctx->addr[0], ctx-
> >bo_size,
> >> -			 ctx->sync, 1);
> >> -
> >> -	return ctx;
> >> -}
> >> -
> >> -static void
> >> -spin_sync_start(int fd, struct spin_ctx *ctx) -{
> >> -	if (!ctx)
> >> -		return;
> >> -
> >> -	ctx->spin_opts.addr = ctx->addr[0];
> >> -	ctx->spin_opts.write_timestamp = true;
> >> -	ctx->spin_opts.preempt = true;
> >> -	xe_spin_init(ctx->spin, &ctx->spin_opts);
> >> -
> >> -	/* re-use sync[0] for exec */
> >> -	ctx->sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> >> -
> >> -	ctx->exec.exec_queue_id = ctx->exec_queue;
> >> -
> >> -	if (ctx->width > 1)
> >> -		ctx->exec.address = to_user_pointer(ctx->addr);
> >> -	else
> >> -		ctx->exec.address = ctx->addr[0];
> >> -
> >> -	xe_exec(fd, &ctx->exec);
> >> -
> >> -	xe_spin_wait_started(ctx->spin);
> >> -	igt_assert(!syncobj_wait(fd, &ctx->sync[1].handle, 1, 1, 0, NULL));
> >> -
> >> -	igt_debug("%s: spinner started\n", engine_map[ctx->class]);
> >> -}
> >> -
> >> -static void
> >> -spin_sync_end(int fd, struct spin_ctx *ctx) -{
> >> -	if (!ctx || ctx->ended)
> >> -		return;
> >> -
> >> -	xe_spin_end(ctx->spin);
> >> -
> >> -	igt_assert(syncobj_wait(fd, &ctx->sync[1].handle, 1, INT64_MAX, 0,
> NULL));
> >> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> >> -
> >> -	ctx->sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> >> -	xe_vm_unbind_async(fd, ctx->vm, 0, 0, ctx->addr[0], ctx->bo_size,
> ctx->sync, 1);
> >> -	igt_assert(syncobj_wait(fd, &ctx->sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> >> -
> >> -	ctx->ended = true;
> >> -	igt_debug("%s: spinner ended (timestamp=%u)\n",
> engine_map[ctx->class],
> >> -		  ctx->spin->timestamp);
> >> -}
> >> -
> >> -static void
> >> -spin_ctx_destroy(int fd, struct spin_ctx *ctx) -{
> >> -	if (!ctx)
> >> -		return;
> >> -
> >> -	syncobj_destroy(fd, ctx->sync[0].handle);
> >> -	syncobj_destroy(fd, ctx->sync[1].handle);
> >> -	xe_exec_queue_destroy(fd, ctx->exec_queue);
> >> -
> >> -	munmap(ctx->spin, ctx->bo_size);
> >> -	gem_close(fd, ctx->bo);
> >> -
> >> -	free(ctx);
> >> -}
> >> -
> >>  static void
> >>  check_results(struct pceu_cycles *s1, struct pceu_cycles *s2,
> >>  	      int class, int width, enum expected_load expected_load) @@
> >> -535,7 +408,7 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in  {
> >>  	struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE +
> 1];
> >>  	struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE +
> 1];
> >> -	struct spin_ctx *ctx = NULL;
> >> +	struct xe_spin_ctx *ctx = NULL;
> >>  	enum expected_load expected_load;
> >>  	uint32_t vm;
> >>  	int new_fd;
> >> @@ -545,8 +418,8 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in
> >>
> >>  	vm = xe_vm_create(fd, 0, 0);
> >>  	if (flags & TEST_BUSY) {
> >> -		ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> -		spin_sync_start(fd, ctx);
> >> +		ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> +		xe_spin_sync_start(fd, ctx);
> >>  	}
> >>
> >>  	read_engine_cycles(fd, pceu1[0]);
> >> @@ -555,7 +428,7 @@ utilization_single(int fd, struct
> >> drm_xe_engine_class_instance *hwe, unsigned in
> >>
> >>  	usleep(batch_duration_usec);
> >>  	if (flags & TEST_TRAILING_IDLE)
> >> -		spin_sync_end(fd, ctx);
> >> +		xe_spin_sync_end(fd, ctx);
> >>
> >>  	read_engine_cycles(fd, pceu2[0]);
> >>  	if (flags & TEST_ISOLATION)
> >> @@ -574,8 +447,8 @@ utilization_single(int fd, struct
> drm_xe_engine_class_instance *hwe, unsigned in
> >>  		close(new_fd);
> >>  	}
> >>
> >> -	spin_sync_end(fd, ctx);
> >> -	spin_ctx_destroy(fd, ctx);
> >> +	xe_spin_sync_end(fd, ctx);
> >> +	xe_spin_ctx_destroy(fd, ctx);
> >>  	xe_vm_destroy(fd, vm);
> >>  }
> >>
> >> @@ -584,19 +457,19 @@ utilization_single_destroy_queue(int fd, struct
> >> drm_xe_engine_class_instance *hw  {
> >>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> -	struct spin_ctx *ctx = NULL;
> >> +	struct xe_spin_ctx *ctx = NULL;
> >>  	uint32_t vm;
> >>
> >>  	vm = xe_vm_create(fd, 0, 0);
> >> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> -	spin_sync_start(fd, ctx);
> >> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> +	xe_spin_sync_start(fd, ctx);
> >>
> >>  	read_engine_cycles(fd, pceu1);
> >>  	usleep(batch_duration_usec);
> >>
> >>  	/* destroy queue before sampling again */
> >> -	spin_sync_end(fd, ctx);
> >> -	spin_ctx_destroy(fd, ctx);
> >> +	xe_spin_sync_end(fd, ctx);
> >> +	xe_spin_ctx_destroy(fd, ctx);
> >>
> >>  	read_engine_cycles(fd, pceu2);
> >>
> >> @@ -610,18 +483,18 @@ utilization_others_idle(int fd, struct
> >> drm_xe_engine_class_instance *hwe)  {
> >>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> -	struct spin_ctx *ctx = NULL;
> >> +	struct xe_spin_ctx *ctx = NULL;
> >>  	uint32_t vm;
> >>  	int class;
> >>
> >>  	vm = xe_vm_create(fd, 0, 0);
> >>
> >> -	ctx = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> -	spin_sync_start(fd, ctx);
> >> +	ctx = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> +	xe_spin_sync_start(fd, ctx);
> >>
> >>  	read_engine_cycles(fd, pceu1);
> >>  	usleep(batch_duration_usec);
> >> -	spin_sync_end(fd, ctx);
> >> +	xe_spin_sync_end(fd, ctx);
> >>  	read_engine_cycles(fd, pceu2);
> >>
> >>  	xe_for_each_engine_class(class) {
> >> @@ -631,8 +504,8 @@ utilization_others_idle(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >>  		check_results(pceu1, pceu2, class, 1, expected_load);
> >>  	}
> >>
> >> -	spin_sync_end(fd, ctx);
> >> -	spin_ctx_destroy(fd, ctx);
> >> +	xe_spin_sync_end(fd, ctx);
> >> +	xe_spin_ctx_destroy(fd, ctx);
> >>  	xe_vm_destroy(fd, vm);
> >>  }
> >>
> >> @@ -641,7 +514,7 @@ utilization_others_full_load(int fd, struct
> >> drm_xe_engine_class_instance *hwe)  {
> >>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> >> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] =
> {};
> >>  	struct drm_xe_engine_class_instance *_hwe;
> >>  	uint32_t vm;
> >>  	int class;
> >> @@ -655,14 +528,14 @@ utilization_others_full_load(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >>  		if (_class == hwe->engine_class || ctx[_class])
> >>  			continue;
> >>
> >> -		ctx[_class] = spin_ctx_init(fd, _hwe, vm, 1, 1);
> >> -		spin_sync_start(fd, ctx[_class]);
> >> +		ctx[_class] = xe_spin_ctx_init(fd, _hwe, 0, vm, 1, 1);
> >> +		xe_spin_sync_start(fd, ctx[_class]);
> >>  	}
> >>
> >>  	read_engine_cycles(fd, pceu1);
> >>  	usleep(batch_duration_usec);
> >>  	xe_for_each_engine_class(class)
> >> -		spin_sync_end(fd, ctx[class]);
> >> +		xe_spin_sync_end(fd, ctx[class]);
> >>  	read_engine_cycles(fd, pceu2);
> >>
> >>  	xe_for_each_engine_class(class) {
> >> @@ -673,8 +546,8 @@ utilization_others_full_load(int fd, struct
> drm_xe_engine_class_instance *hwe)
> >>  			continue;
> >>
> >>  		check_results(pceu1, pceu2, class, 1, expected_load);
> >> -		spin_sync_end(fd, ctx[class]);
> >> -		spin_ctx_destroy(fd, ctx[class]);
> >> +		xe_spin_sync_end(fd, ctx[class]);
> >> +		xe_spin_ctx_destroy(fd, ctx[class]);
> >>  	}
> >>
> >>  	xe_vm_destroy(fd, vm);
> >> @@ -685,7 +558,7 @@ utilization_all_full_load(int fd)  {
> >>  	struct pceu_cycles pceu1[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct pceu_cycles pceu2[DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >> -	struct spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
> >> +	struct xe_spin_ctx *ctx[DRM_XE_ENGINE_CLASS_COMPUTE + 1] =
> {};
> >>  	struct drm_xe_engine_class_instance *hwe;
> >>  	uint32_t vm;
> >>  	int class;
> >> @@ -698,14 +571,14 @@ utilization_all_full_load(int fd)
> >>  		if (ctx[class])
> >>  			continue;
> >>
> >> -		ctx[class] = spin_ctx_init(fd, hwe, vm, 1, 1);
> >> -		spin_sync_start(fd, ctx[class]);
> >> +		ctx[class] = xe_spin_ctx_init(fd, hwe, 0, vm, 1, 1);
> >> +		xe_spin_sync_start(fd, ctx[class]);
> >>  	}
> >>
> >>  	read_engine_cycles(fd, pceu1);
> >>  	usleep(batch_duration_usec);
> >>  	xe_for_each_engine_class(class)
> >> -		spin_sync_end(fd, ctx[class]);
> >> +		xe_spin_sync_end(fd, ctx[class]);
> >>  	read_engine_cycles(fd, pceu2);
> >>
> >>  	xe_for_each_engine_class(class) {
> >> @@ -713,8 +586,8 @@ utilization_all_full_load(int fd)
> >>  			continue;
> >>
> >>  		check_results(pceu1, pceu2, class, 1,
> EXPECTED_LOAD_FULL);
> >> -		spin_sync_end(fd, ctx[class]);
> >> -		spin_ctx_destroy(fd, ctx[class]);
> >> +		xe_spin_sync_end(fd, ctx[class]);
> >> +		xe_spin_ctx_destroy(fd, ctx[class]);
> >>  	}
> >>
> >>  	xe_vm_destroy(fd, vm);
> >> @@ -741,7 +614,7 @@ utilization_multi(int fd, int gt, int class, unsigned int
> flags)
> >>  	struct pceu_cycles pceu[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct pceu_cycles
> pceu_spill[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1];
> >>  	struct drm_xe_engine_class_instance
> eci[XE_MAX_ENGINE_INSTANCE];
> >> -	struct spin_ctx *ctx = NULL;
> >> +	struct xe_spin_ctx *ctx = NULL;
> >>  	enum expected_load expected_load;
> >>  	int fd_spill, num_placements;
> >>  	uint32_t vm;
> >> @@ -767,8 +640,8 @@ utilization_multi(int fd, int gt, int class,
> >> unsigned int flags)
> >>
> >>  	vm = xe_vm_create(fd, 0, 0);
> >>  	if (flags & TEST_BUSY) {
> >> -		ctx = spin_ctx_init(fd, eci, vm, width, num_placements);
> >> -		spin_sync_start(fd, ctx);
> >> +		ctx = xe_spin_ctx_init(fd, eci, 0, vm, width,
> num_placements);
> >> +		xe_spin_sync_start(fd, ctx);
> >>  	}
> >>
> >>  	read_engine_cycles(fd, pceu[0]);
> >> @@ -777,7 +650,7 @@ utilization_multi(int fd, int gt, int class,
> >> unsigned int flags)
> >>
> >>  	usleep(batch_duration_usec);
> >>  	if (flags & TEST_TRAILING_IDLE)
> >> -		spin_sync_end(fd, ctx);
> >> +		xe_spin_sync_end(fd, ctx);
> >>
> >>  	read_engine_cycles(fd, pceu[1]);
> >>  	if (flags & TEST_ISOLATION)
> >> @@ -797,8 +670,8 @@ utilization_multi(int fd, int gt, int class, unsigned int
> flags)
> >>  		close(fd_spill);
> >>  	}
> >>
> >> -	spin_sync_end(fd, ctx);
> >> -	spin_ctx_destroy(fd, ctx);
> >> +	xe_spin_sync_end(fd, ctx);
> >> +	xe_spin_ctx_destroy(fd, ctx);
> >>
> >>  	xe_vm_destroy(fd, vm);
> >>  }
> >> --
> >> 2.34.1
> >>

Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions to lib

[Lucas De Marchi]

On Wed, Nov 13, 2024 at 10:13:06AM -0600, Gurram, Pravalika wrote:
>
>
>> -----Original Message-----
>> From: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Sent: Friday, November 8, 2024 9:09 PM
>> To: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>> Cc: Gurram, Pravalika <pravalika.gurram@intel.com>; igt-
>> dev@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>
>> Subject: Re: [PATCH 1/2] lib/xe/xe_spin: move the spinner related functions
>> to lib
>>
>> On Fri, Nov 08, 2024 at 10:01:41AM +0100, Zbigniew Kempczyński wrote:
>> >+Lucas
>>
>> Pravalika, please keep me in Cc. I don't watch the igt mailing list close
>> enough, particularly when it's a follow up to a suggestion I gave.
>>
>> >
>> >On Fri, Nov 08, 2024 at 01:14:02PM +0530, Pravalika Gurram wrote:
>> >> move spin_ctx_init,spin_ctx_start,spin_ctx_end,spin_ctx_destroy
>> >> to xe spin lib to avoid code redundancy.
>> >>
>> >> v2: use allocator based on developer preference.
>> >>     change spin_ctx to xe_spin_ctx to avoid name clashes [Zbigniew]
>>
>> but we already have another thing named ctx there, the rename doesn't
>> improve it.
>>
>>  From lib/xe/xe_spin.h, what should be added on is
>>
>> struct xe_cork {
>> 	struct xe_spin *spin;
>> 	int fd;
>> 	uint32_t vm;
>> 	uint32_t bo;
>> 	uint32_t exec_queue;
>> 	uint32_t syncobj;
>> };
>>
>> I don't really like that name, but we can do a rename on top... or we can
>> rename it now and then move things.
>>
>
>could you please suggest the name in place of xe_cork

not sure... I think we can probably have:

Current		alternative1	alternative2	alternative3
xe_spin		xe_spin_bo	xe_spin		xe_spin
xe_cork		xe_spinner	xe_spin_ctx	xe_spinner

Or keep as is and let the rename to be done when everything is added. As
the original author of xe_cork, I'd wait on Matt Brost about a rename.

Lucas De Marchi

[PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check

[Pravalika Gurram]

check the ctx_timestamp register post gt reset for each engine.

V2: move spinner code to lib avoid code redundancy
    use flags to maintain the readability
    use READ_ONCE to prevent compiler from optimizing it out [Lucas]

V3: call allocator in run_spinner and pass to spinner ctx [Zbigniew]
v4: Integrate spin_ctx to xe_cork [Lucas]

Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 9314e229e..9a5cdb830 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -309,6 +309,121 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
 	put_ahnd(ahnd);
 }
 
+static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
+		       bool hang)
+{
+	uint64_t ahnd, bb_size, bb_addr;
+	uint32_t vm, exec_queue, bb;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync syncobj = {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&syncobj),
+	};
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint32_t data;
+		uint64_t vm_sync;
+		uint64_t exec_sync;
+	} *data;
+	uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
+	int64_t timeout = NSEC_PER_SEC;
+	int i, ret;
+
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+	vm = xe_vm_create(fd, 0, 0);
+	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
+	bb_size = xe_bb_size(fd, sizeof(*data));
+	bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
+	bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
+						      ALLOC_STRATEGY_LOW_TO_HIGH);
+	data = xe_bo_map(fd, bb, bb_size);
+	syncobj.addr = to_user_pointer(&data->vm_sync);
+	xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
+	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
+
+	batch_offset = (char *)&data->batch - (char *)data;
+	batch_addr = bb_addr + batch_offset;
+	sdi_offset = (char *)&data->data - (char *)data;
+	sdi_addr = bb_addr + sdi_offset;
+
+	i = 0;
+
+	data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
+	data->batch[i++] = sdi_addr;
+	data->batch[i++] = sdi_addr >> 32;
+	data->batch[i++] = 0;
+	if (!hang)
+		data->batch[i++] = MI_BATCH_BUFFER_END;
+	igt_assert(i <= ARRAY_SIZE(data->batch));
+
+	syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
+	exec.exec_queue_id = exec_queue;
+	exec.address = batch_addr;
+	xe_exec(fd, &exec);
+	ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
+	igt_assert(hang ? ret < 0 : ret == 0);
+
+	munmap(data, bb_size);
+	gem_close(fd, bb);
+
+	xe_exec_queue_destroy(fd, exec_queue);
+	xe_vm_destroy(fd, vm);
+
+	put_ahnd(ahnd);
+}
+
+static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	struct xe_cork *ctx = NULL;
+	uint32_t vm;
+	uint32_t ts_1, ts_2;
+	uint64_t ahnd;
+
+	vm = xe_vm_create(fd, 0, 0);
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+	ctx = xe_spin_ctx_init_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
+	xe_spin_sync_start(fd, ctx);
+
+	/* Collect and check timestamps before stopping the spinner */
+	usleep(50000);
+	ts_1 = READ_ONCE(ctx->spin->timestamp);
+	usleep(50000);
+	ts_2 = READ_ONCE(ctx->spin->timestamp);
+	igt_assert_neq_u32(ts_1, ts_2);
+
+	xe_spin_sync_end(fd, ctx);
+	xe_spin_ctx_destroy(fd, ctx);
+
+	xe_vm_destroy(fd, vm);
+	put_ahnd(ahnd);
+}
+
+#define TRUE 1
+#define FALSE 0
+/**
+ * SUBTEST: spin-timestamp-check
+ * Description: Intiate gt reset then check the timestamp register for each engine.
+ * Test category: functionality test
+ */
+static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	/*sanity check for exec submission*/
+	exec_store(fd, eci, FALSE);
+
+	exec_store(fd, eci, TRUE);
+
+	run_spinner(fd, eci);
+}
+
 igt_main
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -343,6 +458,12 @@ igt_main
 			xe_for_each_engine_class(class)
 				xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
 
+	igt_subtest_with_dynamic("spin-timestamp-check")
+		xe_for_each_engine(fd, hwe) {
+			igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
+				xe_spin_timestamp_check(fd, hwe);
+		}
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.34.1

Re: [PATCH 2/2] tests/xe_spin_batch: Add spin-timestamp-check

[Peter Senna Tschudin]

I did compile and test using igt-runner and the following test-list
with and without the two patches in this series. I found no issues.

 igt@xe_drm_fdinfo
 igt@xe_spin_batch
 igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
 igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff
 igt@core_hotunplug@hotrebind
 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt
 igt@xe_prime_self_import@basic-with_one_bo
 igt@xe_exec_basic@many-basic
 igt@kms_mmap_write_crc@main
 igt@kms_flip@2x-busy-flip
 igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen
 igt@kms_addfb_basic@invalid-set-prop-any
 igt@xe_sysfs_scheduler@timeslice_duration_us-invalid
 igt@kms_frontbuffer_tracking@fbcpsr-tiling-4
 igt@kms_cursor_edge_walk@64x64-left-edge
 igt@xe_module_load@reload-no-display

On 13.11.2024 18:52, Pravalika Gurram wrote:
> check the ctx_timestamp register post gt reset for each engine.
> 
> V2: move spinner code to lib avoid code redundancy
>     use flags to maintain the readability
>     use READ_ONCE to prevent compiler from optimizing it out [Lucas]
> 
> V3: call allocator in run_spinner and pass to spinner ctx [Zbigniew]
> v4: Integrate spin_ctx to xe_cork [Lucas]
> 
> Signed-off-by: Pravalika Gurram <pravalika.gurram@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Tested-by: Peter Senna Tschudin <peter.senna@linux.intel.com>

> ---
>  tests/intel/xe_spin_batch.c | 121 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 121 insertions(+)
> 
> diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
> index 9314e229e..9a5cdb830 100644
> --- a/tests/intel/xe_spin_batch.c
> +++ b/tests/intel/xe_spin_batch.c
> @@ -309,6 +309,121 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags)
>  	put_ahnd(ahnd);
>  }
>  
> +static void exec_store(int fd, struct drm_xe_engine_class_instance *eci,
> +		       bool hang)
> +{
> +	uint64_t ahnd, bb_size, bb_addr;
> +	uint32_t vm, exec_queue, bb;
> +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> +	struct drm_xe_sync syncobj = {
> +		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.timeline_value = USER_FENCE_VALUE,
> +	};
> +
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&syncobj),
> +	};
> +	struct {
> +		uint32_t batch[16];
> +		uint64_t pad;
> +		uint32_t data;
> +		uint64_t vm_sync;
> +		uint64_t exec_sync;
> +	} *data;
> +	uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr;
> +	int64_t timeout = NSEC_PER_SEC;
> +	int i, ret;
> +
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> +	bb_size = xe_bb_size(fd, sizeof(*data));
> +	bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0);
> +	bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0,
> +						      ALLOC_STRATEGY_LOW_TO_HIGH);
> +	data = xe_bo_map(fd, bb, bb_size);
> +	syncobj.addr = to_user_pointer(&data->vm_sync);
> +	xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1);
> +	xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
> +
> +	batch_offset = (char *)&data->batch - (char *)data;
> +	batch_addr = bb_addr + batch_offset;
> +	sdi_offset = (char *)&data->data - (char *)data;
> +	sdi_addr = bb_addr + sdi_offset;
> +
> +	i = 0;
> +
> +	data->batch[i++] = MI_STORE_DWORD_IMM_GEN4;
> +	data->batch[i++] = sdi_addr;
> +	data->batch[i++] = sdi_addr >> 32;
> +	data->batch[i++] = 0;
> +	if (!hang)
> +		data->batch[i++] = MI_BATCH_BUFFER_END;
> +	igt_assert(i <= ARRAY_SIZE(data->batch));
> +
> +	syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data;
> +	exec.exec_queue_id = exec_queue;
> +	exec.address = batch_addr;
> +	xe_exec(fd, &exec);
> +	ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout);
> +	igt_assert(hang ? ret < 0 : ret == 0);
> +
> +	munmap(data, bb_size);
> +	gem_close(fd, bb);
> +
> +	xe_exec_queue_destroy(fd, exec_queue);
> +	xe_vm_destroy(fd, vm);
> +
> +	put_ahnd(ahnd);
> +}
> +
> +static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> +	struct xe_cork *ctx = NULL;
> +	uint32_t vm;
> +	uint32_t ts_1, ts_2;
> +	uint64_t ahnd;
> +
> +	vm = xe_vm_create(fd, 0, 0);
> +	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +	ctx = xe_spin_ctx_init_opts(fd, eci, vm, 1, 1, .ahnd = ahnd);
> +	xe_spin_sync_start(fd, ctx);
> +
> +	/* Collect and check timestamps before stopping the spinner */
> +	usleep(50000);
> +	ts_1 = READ_ONCE(ctx->spin->timestamp);
> +	usleep(50000);
> +	ts_2 = READ_ONCE(ctx->spin->timestamp);
> +	igt_assert_neq_u32(ts_1, ts_2);
> +
> +	xe_spin_sync_end(fd, ctx);
> +	xe_spin_ctx_destroy(fd, ctx);
> +
> +	xe_vm_destroy(fd, vm);
> +	put_ahnd(ahnd);
> +}
> +
> +#define TRUE 1
> +#define FALSE 0
> +/**
> + * SUBTEST: spin-timestamp-check
> + * Description: Intiate gt reset then check the timestamp register for each engine.
> + * Test category: functionality test
> + */
> +static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> +	/*sanity check for exec submission*/
> +	exec_store(fd, eci, FALSE);
> +
> +	exec_store(fd, eci, TRUE);
> +
> +	run_spinner(fd, eci);
> +}
> +
>  igt_main
>  {
>  	struct drm_xe_engine_class_instance *hwe;
> @@ -343,6 +458,12 @@ igt_main
>  			xe_for_each_engine_class(class)
>  				xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT);
>  
> +	igt_subtest_with_dynamic("spin-timestamp-check")
> +		xe_for_each_engine(fd, hwe) {
> +			igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class))
> +				xe_spin_timestamp_check(fd, hwe);
> +		}
> +
>  	igt_fixture
>  		drm_close_driver(fd);
>  }