* [igt-dev] [PATCH i-g-t v4 01/21] lib/intel_blt: Add blt_ctrl_surf_object() helper
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 6:53 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 02/21] tests/gem_ccs: Drop local function for setting ctrl surface object Zbigniew Kempczyński
` (24 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
In the series we start using this more time so it's worth to add
it as common code.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/intel_blt.c | 11 +++++++++++
lib/intel_blt.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index bc28f15e8d..a3d67f5136 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1390,6 +1390,17 @@ void blt_set_copy_object(struct blt_copy_object *obj,
memcpy(obj, orig, sizeof(*obj));
}
+void blt_set_ctrl_surf_object(struct blt_ctrl_surf_copy_object *obj,
+ uint32_t handle, uint32_t region, uint64_t size,
+ uint8_t mocs, enum blt_access_type access_type)
+{
+ obj->handle = handle;
+ obj->region = region;
+ obj->size = size;
+ obj->mocs = mocs;
+ obj->access_type = access_type;
+}
+
/**
* blt_surface_fill_rect:
* @fd: drm fd
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 9c4ddc7a89..2aa1259ae8 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -248,6 +248,9 @@ void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
enum blt_surface_type surface_type);
void blt_set_copy_object(struct blt_copy_object *obj,
const struct blt_copy_object *orig);
+void blt_set_ctrl_surf_object(struct blt_ctrl_surf_copy_object *obj,
+ uint32_t handle, uint32_t region, uint64_t size,
+ uint8_t mocs, enum blt_access_type access_type);
void blt_surface_info(const char *info,
const struct blt_copy_object *obj);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 01/21] lib/intel_blt: Add blt_ctrl_surf_object() helper
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 01/21] lib/intel_blt: Add blt_ctrl_surf_object() helper Zbigniew Kempczyński
@ 2023-07-13 6:53 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 6:53 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> In the series we start using this more time so it's worth to add
> it as common code.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> lib/intel_blt.c | 11 +++++++++++
> lib/intel_blt.h | 3 +++
> 2 files changed, 14 insertions(+)
>
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index bc28f15e8d..a3d67f5136 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1390,6 +1390,17 @@ void blt_set_copy_object(struct blt_copy_object *obj,
> memcpy(obj, orig, sizeof(*obj));
> }
>
> +void blt_set_ctrl_surf_object(struct blt_ctrl_surf_copy_object *obj,
> + uint32_t handle, uint32_t region, uint64_t size,
> + uint8_t mocs, enum blt_access_type access_type)
> +{
> + obj->handle = handle;
> + obj->region = region;
> + obj->size = size;
> + obj->mocs = mocs;
> + obj->access_type = access_type;
> +}
> +
> /**
> * blt_surface_fill_rect:
> * @fd: drm fd
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 9c4ddc7a89..2aa1259ae8 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -248,6 +248,9 @@ void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
> enum blt_surface_type surface_type);
> void blt_set_copy_object(struct blt_copy_object *obj,
> const struct blt_copy_object *orig);
> +void blt_set_ctrl_surf_object(struct blt_ctrl_surf_copy_object *obj,
> + uint32_t handle, uint32_t region, uint64_t size,
> + uint8_t mocs, enum blt_access_type access_type);
>
> void blt_surface_info(const char *info,
> const struct blt_copy_object *obj);
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 02/21] tests/gem_ccs: Drop local function for setting ctrl surface object
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 01/21] lib/intel_blt: Add blt_ctrl_surf_object() helper Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 6:59 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 03/21] lib/intel_blt: Add dump of two surfaces comparison in 8x8 blocks Zbigniew Kempczyński
` (23 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Until now gem_ccs was the only user of set_surf_object() and probably
from this reason it wasn't "globalized". Upcoming gem_ccs counterpart
for xe - xe_ccs - uses same object initialization and we got this
function (with small rename) in the blitter library so we can use it
and get rid of local version.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_ccs.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index f9ad9267df..9beddeaee4 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -77,17 +77,6 @@ struct test_config {
bool suspend_resume;
};
-static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
- uint32_t handle, uint32_t region, uint64_t size,
- uint8_t mocs, enum blt_access_type access_type)
-{
- obj->handle = handle;
- obj->region = region;
- obj->size = size;
- obj->mocs = mocs;
- obj->access_type = access_type;
-}
-
#define PRINT_SURFACE_INFO(name, obj) do { \
if (param.print_surface_info) \
blt_surface_info((name), (obj)); } while (0)
@@ -169,10 +158,10 @@ static void surf_copy(int i915,
surf.fd = i915;
surf.print_bb = param.print_bb;
- set_surf_object(&surf.src, mid->handle, mid->region, mid->size,
- uc_mocs, BLT_INDIRECT_ACCESS);
- set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
- uc_mocs, DIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
+ uc_mocs, BLT_INDIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
+ uc_mocs, DIRECT_ACCESS);
bb_size = 4096;
igt_assert_eq(__gem_create(i915, &bb_size, &bb1), 0);
blt_set_batch(&surf.bb, bb1, bb_size, REGION_SMEM);
@@ -191,8 +180,8 @@ static void surf_copy(int i915,
igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE);
- set_surf_object(&surf.dst, ccs2, REGION_SMEM, ccssize,
- 0, DIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.dst, ccs2, REGION_SMEM, ccssize,
+ 0, DIRECT_ACCESS);
blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
gem_sync(i915, surf.dst.handle);
@@ -213,10 +202,10 @@ static void surf_copy(int i915,
/* corrupt ccs */
for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
ccsmap[i] = i;
- set_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
- uc_mocs, DIRECT_ACCESS);
- set_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
- uc_mocs, INDIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
+ uc_mocs, DIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
+ uc_mocs, INDIRECT_ACCESS);
blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
memset(&blt, 0, sizeof(blt));
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 02/21] tests/gem_ccs: Drop local function for setting ctrl surface object
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 02/21] tests/gem_ccs: Drop local function for setting ctrl surface object Zbigniew Kempczyński
@ 2023-07-13 6:59 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 6:59 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Until now gem_ccs was the only user of set_surf_object() and probably
> from this reason it wasn't "globalized". Upcoming gem_ccs counterpart
> for xe - xe_ccs - uses same object initialization and we got this
> function (with small rename) in the blitter library so we can use it
> and get rid of local version.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> tests/i915/gem_ccs.c | 31 ++++++++++---------------------
> 1 file changed, 10 insertions(+), 21 deletions(-)
>
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index f9ad9267df..9beddeaee4 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -77,17 +77,6 @@ struct test_config {
> bool suspend_resume;
> };
>
> -static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
> - uint32_t handle, uint32_t region, uint64_t size,
> - uint8_t mocs, enum blt_access_type access_type)
> -{
> - obj->handle = handle;
> - obj->region = region;
> - obj->size = size;
> - obj->mocs = mocs;
> - obj->access_type = access_type;
> -}
> -
> #define PRINT_SURFACE_INFO(name, obj) do { \
> if (param.print_surface_info) \
> blt_surface_info((name), (obj)); } while (0)
> @@ -169,10 +158,10 @@ static void surf_copy(int i915,
>
> surf.fd = i915;
> surf.print_bb = param.print_bb;
> - set_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> - uc_mocs, BLT_INDIRECT_ACCESS);
> - set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
> - uc_mocs, DIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> + uc_mocs, BLT_INDIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
> + uc_mocs, DIRECT_ACCESS);
> bb_size = 4096;
> igt_assert_eq(__gem_create(i915, &bb_size, &bb1), 0);
> blt_set_batch(&surf.bb, bb1, bb_size, REGION_SMEM);
> @@ -191,8 +180,8 @@ static void surf_copy(int i915,
>
> igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE);
>
> - set_surf_object(&surf.dst, ccs2, REGION_SMEM, ccssize,
> - 0, DIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.dst, ccs2, REGION_SMEM, ccssize,
> + 0, DIRECT_ACCESS);
> blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
> gem_sync(i915, surf.dst.handle);
>
> @@ -213,10 +202,10 @@ static void surf_copy(int i915,
> /* corrupt ccs */
> for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
> ccsmap[i] = i;
> - set_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
> - uc_mocs, DIRECT_ACCESS);
> - set_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> - uc_mocs, INDIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
> + uc_mocs, DIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> + uc_mocs, INDIRECT_ACCESS);
> blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
>
> memset(&blt, 0, sizeof(blt));
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 03/21] lib/intel_blt: Add dump of two surfaces comparison in 8x8 blocks
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 01/21] lib/intel_blt: Add blt_ctrl_surf_object() helper Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 02/21] tests/gem_ccs: Drop local function for setting ctrl surface object Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:08 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 04/21] tests/gem_ccs: Use global image dump comparison function Zbigniew Kempczyński
` (22 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Add limited to 32bit color function which compares two surfaces
dumping differences in 8x8 as single ascii char. It's globalized
version of already existed dump_corruption_info() from gem_ccs
test but I'm planning to use it in xe_ccs so keeping common code
locally in the test doesn't make sense.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/intel_blt.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
lib/intel_blt.h | 2 ++
2 files changed, 66 insertions(+)
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index a3d67f5136..1af57c4912 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1516,3 +1516,67 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
if (!obj->ptr)
munmap(map, obj->size);
}
+
+static int compare_nxn(const struct blt_copy_object *surf1,
+ const struct blt_copy_object *surf2,
+ int xsize, int ysize, int bx, int by)
+{
+ int x, y, corrupted;
+ uint32_t pos, px1, px2;
+
+ corrupted = 0;
+ for (y = 0; y < ysize; y++) {
+ for (x = 0; x < xsize; x++) {
+ pos = bx * xsize + by * ysize * surf1->pitch / 4;
+ pos += x + y * surf1->pitch / 4;
+ px1 = surf1->ptr[pos];
+ px2 = surf2->ptr[pos];
+ if (px1 != px2)
+ corrupted++;
+ }
+ }
+
+ return corrupted;
+}
+
+/**
+ * blt_dump_corruption_info_32b:
+ * @surf1: first surface
+ * @surf2: second surface
+ *
+ * Function dumps ascii representation of the surfaces corruption. Comparison
+ * is performed on 8x8 32bpp color pixel blocks. Number of differences on
+ * such block varies from 0 (no corruption) to 64 (pixels on those surfaces
+ * differs). It is added then to '0' ascii character to point the corruption
+ * occured, for non affected block '.' is printed out.
+ *
+ * Idea of this function is to determine character of the differences between
+ * two surfaces without generating difference image.
+ *
+ * Currently function assumes both @surf1 and @surf2 are 32-bit color surfaces.
+ */
+void blt_dump_corruption_info_32b(const struct blt_copy_object *surf1,
+ const struct blt_copy_object *surf2)
+{
+ const int xsize = 8, ysize = 8;
+ int w, h, bx, by, corrupted;
+
+ igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2);
+ igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2);
+ w = surf1->x2;
+ h = surf1->y2;
+
+ igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n",
+ surf1->x2, surf1->y2, xsize, ysize);
+
+ for (by = 0; by < h / ysize; by++) {
+ for (bx = 0; bx < w / xsize; bx++) {
+ corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by);
+ if (corrupted == 0)
+ igt_info(".");
+ else
+ igt_info("%c", '0' + corrupted);
+ }
+ igt_info("\n");
+ }
+}
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 2aa1259ae8..c134466d4d 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -259,5 +259,7 @@ void blt_surface_fill_rect(int fd, const struct blt_copy_object *obj,
void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
const struct blt_copy_object *obj,
uint32_t width, uint32_t height);
+void blt_dump_corruption_info_32b(const struct blt_copy_object *surf1,
+ const struct blt_copy_object *surf2);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 03/21] lib/intel_blt: Add dump of two surfaces comparison in 8x8 blocks
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 03/21] lib/intel_blt: Add dump of two surfaces comparison in 8x8 blocks Zbigniew Kempczyński
@ 2023-07-13 7:08 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:08 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Add limited to 32bit color function which compares two surfaces
> dumping differences in 8x8 as single ascii char. It's globalized
> version of already existed dump_corruption_info() from gem_ccs
> test but I'm planning to use it in xe_ccs so keeping common code
> locally in the test doesn't make sense.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> lib/intel_blt.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
> lib/intel_blt.h | 2 ++
> 2 files changed, 66 insertions(+)
>
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index a3d67f5136..1af57c4912 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1516,3 +1516,67 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
> if (!obj->ptr)
> munmap(map, obj->size);
> }
> +
> +static int compare_nxn(const struct blt_copy_object *surf1,
> + const struct blt_copy_object *surf2,
> + int xsize, int ysize, int bx, int by)
Alignment seems to be off here
> +{
> + int x, y, corrupted;
> + uint32_t pos, px1, px2;
> +
> + corrupted = 0;
> + for (y = 0; y < ysize; y++) {
> + for (x = 0; x < xsize; x++) {
> + pos = bx * xsize + by * ysize * surf1->pitch / 4;
> + pos += x + y * surf1->pitch / 4;
> + px1 = surf1->ptr[pos];
> + px2 = surf2->ptr[pos];
> + if (px1 != px2)
> + corrupted++;
> + }
> + }
> +
> + return corrupted;
> +}
> +
> +/**
> + * blt_dump_corruption_info_32b:
> + * @surf1: first surface
> + * @surf2: second surface
> + *
> + * Function dumps ascii representation of the surfaces corruption. Comparison
> + * is performed on 8x8 32bpp color pixel blocks. Number of differences on
> + * such block varies from 0 (no corruption) to 64 (pixels on those surfaces ^- all pixels?
> + * differs). It is added then to '0' ascii character to point the corruption
> + * occured, for non affected block '.' is printed out.
^- s/occured/occurred/
With fixed alignment and docs:
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> + *
> + * Idea of this function is to determine character of the differences between
> + * two surfaces without generating difference image.
> + *
> + * Currently function assumes both @surf1 and @surf2 are 32-bit color surfaces.
> + */
> +void blt_dump_corruption_info_32b(const struct blt_copy_object *surf1,
> + const struct blt_copy_object *surf2)
> +{
> + const int xsize = 8, ysize = 8;
> + int w, h, bx, by, corrupted;
> +
> + igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2);
> + igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2);
> + w = surf1->x2;
> + h = surf1->y2;
> +
> + igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n",
> + surf1->x2, surf1->y2, xsize, ysize);
> +
> + for (by = 0; by < h / ysize; by++) {
> + for (bx = 0; bx < w / xsize; bx++) {
> + corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by);
> + if (corrupted == 0)
> + igt_info(".");
> + else
> + igt_info("%c", '0' + corrupted);
> + }
> + igt_info("\n");
> + }
> +}
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 2aa1259ae8..c134466d4d 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -259,5 +259,7 @@ void blt_surface_fill_rect(int fd, const struct blt_copy_object *obj,
> void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
> const struct blt_copy_object *obj,
> uint32_t width, uint32_t height);
> +void blt_dump_corruption_info_32b(const struct blt_copy_object *surf1,
> + const struct blt_copy_object *surf2);
>
> #endif
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 04/21] tests/gem_ccs: Use global image dump comparison function
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (2 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 03/21] lib/intel_blt: Add dump of two surfaces comparison in 8x8 blocks Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:12 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 05/21] tests/api_intel_allocator: Don't use allocator ahnd aliasing api Zbigniew Kempczyński
` (21 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
As this function was extracted and available globally keeping local
version doesn't makes sense.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_ccs.c | 50 +-------------------------------------------
1 file changed, 1 insertion(+), 49 deletions(-)
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index 9beddeaee4..8f5d5b4f96 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -85,54 +85,6 @@ struct test_config {
if (param.write_png) \
blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
-static int compare_nxn(const struct blt_copy_object *surf1,
- const struct blt_copy_object *surf2,
- int xsize, int ysize, int bx, int by)
-{
- int x, y, corrupted;
- uint32_t pos, px1, px2;
-
- corrupted = 0;
- for (y = 0; y < ysize; y++) {
- for (x = 0; x < xsize; x++) {
- pos = bx * xsize + by * ysize * surf1->pitch / 4;
- pos += x + y * surf1->pitch / 4;
- px1 = surf1->ptr[pos];
- px2 = surf2->ptr[pos];
- if (px1 != px2)
- corrupted++;
- }
- }
-
- return corrupted;
-}
-
-static void dump_corruption_info(const struct blt_copy_object *surf1,
- const struct blt_copy_object *surf2)
-{
- const int xsize = 8, ysize = 8;
- int w, h, bx, by, corrupted;
-
- igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2);
- igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2);
- w = surf1->x2;
- h = surf1->y2;
-
- igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n",
- surf1->x2, surf1->y2, xsize, ysize);
-
- for (by = 0; by < h / ysize; by++) {
- for (bx = 0; bx < w / xsize; bx++) {
- corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by);
- if (corrupted == 0)
- igt_info(".");
- else
- igt_info("%c", '0' + corrupted);
- }
- igt_info("\n");
- }
-}
-
static void surf_copy(int i915,
const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
@@ -232,7 +184,7 @@ static void surf_copy(int i915,
WRITE_PNG(i915, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
result = memcmp(src->ptr, dst->ptr, src->size);
if (result)
- dump_corruption_info(src, dst);
+ blt_dump_corruption_info_32b(src, dst);
munmap(ccsmap, ccssize);
gem_close(i915, ccs);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 04/21] tests/gem_ccs: Use global image dump comparison function
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 04/21] tests/gem_ccs: Use global image dump comparison function Zbigniew Kempczyński
@ 2023-07-13 7:12 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:12 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> As this function was extracted and available globally keeping local
> version doesn't makes sense.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
I think you could squash commits that add global defs and remove local
definitions Anyway:
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> tests/i915/gem_ccs.c | 50 +-------------------------------------------
> 1 file changed, 1 insertion(+), 49 deletions(-)
>
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index 9beddeaee4..8f5d5b4f96 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -85,54 +85,6 @@ struct test_config {
> if (param.write_png) \
> blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
>
> -static int compare_nxn(const struct blt_copy_object *surf1,
> - const struct blt_copy_object *surf2,
> - int xsize, int ysize, int bx, int by)
> -{
> - int x, y, corrupted;
> - uint32_t pos, px1, px2;
> -
> - corrupted = 0;
> - for (y = 0; y < ysize; y++) {
> - for (x = 0; x < xsize; x++) {
> - pos = bx * xsize + by * ysize * surf1->pitch / 4;
> - pos += x + y * surf1->pitch / 4;
> - px1 = surf1->ptr[pos];
> - px2 = surf2->ptr[pos];
> - if (px1 != px2)
> - corrupted++;
> - }
> - }
> -
> - return corrupted;
> -}
> -
> -static void dump_corruption_info(const struct blt_copy_object *surf1,
> - const struct blt_copy_object *surf2)
> -{
> - const int xsize = 8, ysize = 8;
> - int w, h, bx, by, corrupted;
> -
> - igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2);
> - igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2);
> - w = surf1->x2;
> - h = surf1->y2;
> -
> - igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n",
> - surf1->x2, surf1->y2, xsize, ysize);
> -
> - for (by = 0; by < h / ysize; by++) {
> - for (bx = 0; bx < w / xsize; bx++) {
> - corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by);
> - if (corrupted == 0)
> - igt_info(".");
> - else
> - igt_info("%c", '0' + corrupted);
> - }
> - igt_info("\n");
> - }
> -}
> -
> static void surf_copy(int i915,
> const intel_ctx_t *ctx,
> const struct intel_execution_engine2 *e,
> @@ -232,7 +184,7 @@ static void surf_copy(int i915,
> WRITE_PNG(i915, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
> result = memcmp(src->ptr, dst->ptr, src->size);
> if (result)
> - dump_corruption_info(src, dst);
> + blt_dump_corruption_info_32b(src, dst);
>
> munmap(ccsmap, ccssize);
> gem_close(i915, ccs);
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 05/21] tests/api_intel_allocator: Don't use allocator ahnd aliasing api
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (3 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 04/21] tests/gem_ccs: Use global image dump comparison function Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 06/21] lib/intel_allocator: Drop aliasing allocator handle api Zbigniew Kempczyński
` (20 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
There's no tests (apart this one) which are using aliasing ahnd
- intel_allocator_open_vm_as(). Additionally it is problematic
on adopting allocator to xe where I need to track allocations
to support easy vm binding. Let's adopt "open-vm" to not to use
this api.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
tests/i915/api_intel_allocator.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c
index b7e3efb87f..77c2d25e83 100644
--- a/tests/i915/api_intel_allocator.c
+++ b/tests/i915/api_intel_allocator.c
@@ -612,32 +612,27 @@ static void reopen_fork(int fd)
static void open_vm(int fd)
{
- uint64_t ahnd[4], offset[4], size = 0x1000;
+ uint64_t ahnd[3], offset[3], size = 0x1000;
int i, n = ARRAY_SIZE(ahnd);
ahnd[0] = intel_allocator_open_vm(fd, 1, INTEL_ALLOCATOR_SIMPLE);
ahnd[1] = intel_allocator_open_vm(fd, 1, INTEL_ALLOCATOR_SIMPLE);
- ahnd[2] = intel_allocator_open_vm_as(ahnd[1], 2);
- ahnd[3] = intel_allocator_open(fd, 3, INTEL_ALLOCATOR_SIMPLE);
+ ahnd[2] = intel_allocator_open(fd, 2, INTEL_ALLOCATOR_SIMPLE);
offset[0] = intel_allocator_alloc(ahnd[0], 1, size, 0);
offset[1] = intel_allocator_alloc(ahnd[1], 2, size, 0);
igt_assert(offset[0] != offset[1]);
- offset[2] = intel_allocator_alloc(ahnd[2], 3, size, 0);
- igt_assert(offset[0] != offset[2] && offset[1] != offset[2]);
-
- offset[3] = intel_allocator_alloc(ahnd[3], 1, size, 0);
- igt_assert(offset[0] == offset[3]);
+ offset[2] = intel_allocator_alloc(ahnd[2], 1, size, 0);
+ igt_assert(offset[0] == offset[2]);
/*
- * As ahnd[0-2] lead to same allocator check can we free all handles
+ * As ahnd[0-1] lead to same allocator check we can free all handles
* using selected ahnd.
*/
- intel_allocator_free(ahnd[0], 1);
- intel_allocator_free(ahnd[0], 2);
- intel_allocator_free(ahnd[0], 3);
- intel_allocator_free(ahnd[3], 1);
+ igt_assert_eq(intel_allocator_free(ahnd[0], 1), true);
+ igt_assert_eq(intel_allocator_free(ahnd[1], 2), true);
+ igt_assert_eq(intel_allocator_free(ahnd[2], 1), true);
for (i = 0; i < n - 1; i++)
igt_assert_eq(intel_allocator_close(ahnd[i]), (i == n - 2));
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 06/21] lib/intel_allocator: Drop aliasing allocator handle api
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (4 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 05/21] tests/api_intel_allocator: Don't use allocator ahnd aliasing api Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 07/21] lib/intel_allocator: Remove extensive debugging Zbigniew Kempczyński
` (19 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
There's no real user of this api, lets drop it.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
--
v3: Remove also ipc message passing for open-as (Karolina)
---
lib/intel_allocator.c | 73 --------------------------------
lib/intel_allocator.h | 1 -
lib/intel_allocator_msgchannel.h | 8 +---
3 files changed, 1 insertion(+), 81 deletions(-)
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index 8161221dbf..09f665fbb9 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -25,7 +25,6 @@
static const char *reqtype_str[] = {
[REQ_STOP] = "stop",
[REQ_OPEN] = "open",
- [REQ_OPEN_AS] = "open as",
[REQ_CLOSE] = "close",
[REQ_ADDRESS_RANGE] = "address range",
[REQ_ALLOC] = "alloc",
@@ -376,19 +375,6 @@ static struct allocator *allocator_open(int fd, uint32_t ctx, uint32_t vm,
return al;
}
-static struct allocator *allocator_open_as(struct allocator *base,
- uint32_t new_vm, uint64_t *ahndp)
-{
- struct allocator *al;
-
- igt_assert(ahndp);
- al = __allocator_create(base->fd, base->ctx, new_vm, base->ial);
- __allocator_get(al);
- *ahndp = __handle_create(al);
-
- return al;
-}
-
static bool allocator_close(uint64_t ahnd)
{
struct allocator *al;
@@ -512,47 +498,6 @@ static int handle_request(struct alloc_req *req, struct alloc_resp *resp)
refcnt - 1, refcnt, ret - 1, ret);
break;
- case REQ_OPEN_AS:
- /* lock first to avoid concurrent close */
- pthread_mutex_lock(&map_mutex);
-
- al = __allocator_find_by_handle(req->allocator_handle);
- resp->response_type = RESP_OPEN_AS;
-
- if (!al) {
- alloc_info("<open as> [tid: %ld] ahnd: %" PRIx64
- " -> no handle\n",
- (long) req->tid, req->allocator_handle);
- pthread_mutex_unlock(&map_mutex);
- break;
- }
-
- if (!al->vm) {
- alloc_info("<open as> [tid: %ld] ahnd: %" PRIx64
- " -> only open as for <fd, vm> is possible\n",
- (long) req->tid, req->allocator_handle);
- pthread_mutex_unlock(&map_mutex);
- break;
- }
-
-
- al = allocator_open_as(al, req->open_as.new_vm, &ahnd);
- refcnt = atomic_load(&al->refcount);
- ret = atomic_load(&al->ial->refcount);
- pthread_mutex_unlock(&map_mutex);
-
- resp->response_type = RESP_OPEN_AS;
- resp->open.allocator_handle = ahnd;
-
- alloc_info("<open as> [tid: %ld] fd: %d, ahnd: %" PRIx64
- ", ctx: %u, vm: %u"
- ", alloc_type: %u, al->refcnt: %ld->%ld"
- ", refcnt: %d->%d\n",
- (long) req->tid, al->fd, ahnd,
- al->ctx, al->vm, al->ial->type,
- refcnt - 1, refcnt, ret - 1, ret);
- break;
-
case REQ_CLOSE:
pthread_mutex_lock(&map_mutex);
al = __allocator_find_by_handle(req->allocator_handle);
@@ -1037,24 +982,6 @@ uint64_t intel_allocator_open_vm(int fd, uint32_t vm, uint8_t allocator_type)
ALLOC_STRATEGY_HIGH_TO_LOW, 0);
}
-uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm)
-{
- struct alloc_req req = { .request_type = REQ_OPEN_AS,
- .allocator_handle = allocator_handle,
- .open_as.new_vm = new_vm };
- struct alloc_resp resp;
-
- /* Get child_tid only once at open() */
- if (child_tid == -1)
- child_tid = gettid();
-
- igt_assert(handle_request(&req, &resp) == 0);
- igt_assert(resp.open_as.allocator_handle);
- igt_assert(resp.response_type == RESP_OPEN_AS);
-
- return resp.open.allocator_handle;
-}
-
/**
* intel_allocator_close:
* @allocator_handle: handle to the allocator that will be closed
diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h
index a6bf573e9d..3ec74f6191 100644
--- a/lib/intel_allocator.h
+++ b/lib/intel_allocator.h
@@ -182,7 +182,6 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm,
enum allocator_strategy strategy,
uint64_t default_alignment);
-uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm);
bool intel_allocator_close(uint64_t allocator_handle);
void intel_allocator_get_address_range(uint64_t allocator_handle,
uint64_t *startp, uint64_t *endp);
diff --git a/lib/intel_allocator_msgchannel.h b/lib/intel_allocator_msgchannel.h
index cefbf4ce33..ba38530fd1 100644
--- a/lib/intel_allocator_msgchannel.h
+++ b/lib/intel_allocator_msgchannel.h
@@ -13,7 +13,6 @@
enum reqtype {
REQ_STOP,
REQ_OPEN,
- REQ_OPEN_AS,
REQ_CLOSE,
REQ_ADDRESS_RANGE,
REQ_ALLOC,
@@ -27,7 +26,6 @@ enum reqtype {
enum resptype {
RESP_OPEN,
- RESP_OPEN_AS,
RESP_CLOSE,
RESP_ADDRESS_RANGE,
RESP_ALLOC,
@@ -58,10 +56,6 @@ struct alloc_req {
uint64_t default_alignment;
} open;
- struct {
- uint32_t new_vm;
- } open_as;
-
struct {
uint32_t handle;
uint64_t size;
@@ -100,7 +94,7 @@ struct alloc_resp {
union {
struct {
uint64_t allocator_handle;
- } open, open_as;
+ } open;
struct {
bool is_empty;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 07/21] lib/intel_allocator: Remove extensive debugging
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (5 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 06/21] lib/intel_allocator: Drop aliasing allocator handle api Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 08/21] lib/xe_ioctl: Export non-assert xe_exec function Zbigniew Kempczyński
` (18 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Debugging map keys comparison leads to produce extensive logging what
in turn obscures analysis. Remove it to get clearer logs.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/intel_allocator.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index 09f665fbb9..cf964ccc41 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -1330,9 +1330,6 @@ static int equal_handles(const void *key1, const void *key2)
{
const struct handle_entry *h1 = key1, *h2 = key2;
- alloc_debug("h1: %llx, h2: %llx\n",
- (long long) h1->handle, (long long) h2->handle);
-
return h1->handle == h2->handle;
}
@@ -1340,9 +1337,6 @@ static int equal_ctx(const void *key1, const void *key2)
{
const struct allocator *a1 = key1, *a2 = key2;
- alloc_debug("a1: <fd: %d, ctx: %u>, a2 <fd: %d, ctx: %u>\n",
- a1->fd, a1->ctx, a2->fd, a2->ctx);
-
return a1->fd == a2->fd && a1->ctx == a2->ctx;
}
@@ -1350,9 +1344,6 @@ static int equal_vm(const void *key1, const void *key2)
{
const struct allocator *a1 = key1, *a2 = key2;
- alloc_debug("a1: <fd: %d, vm: %u>, a2 <fd: %d, vm: %u>\n",
- a1->fd, a1->vm, a2->fd, a2->vm);
-
return a1->fd == a2->fd && a1->vm == a2->vm;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 08/21] lib/xe_ioctl: Export non-assert xe_exec function
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (6 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 07/21] lib/intel_allocator: Remove extensive debugging Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 09/21] lib/xe_query: Use vramN when returning string region name Zbigniew Kempczyński
` (17 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Export __xe_exec() helper to allow caller to handle the error
individually.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/xe/xe_ioctl.c | 2 +-
lib/xe/xe_ioctl.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 9ead7307c4..0b5c7a4fce 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -357,7 +357,7 @@ void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot)
return __xe_bo_map(fd, bo, size, prot);
}
-static int __xe_exec(int fd, struct drm_xe_exec *exec)
+int __xe_exec(int fd, struct drm_xe_exec *exec)
{
int err = 0;
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index e014ad66c9..320e0f9f68 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -75,6 +75,7 @@ void xe_engine_destroy(int fd, uint32_t engine);
uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
void *xe_bo_map(int fd, uint32_t bo, size_t size);
void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot);
+int __xe_exec(int fd, struct drm_xe_exec *exec);
void xe_exec(int fd, struct drm_xe_exec *exec);
void xe_exec_sync(int fd, uint32_t engine, uint64_t addr,
struct drm_xe_sync *sync, uint32_t num_syncs);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 09/21] lib/xe_query: Use vramN when returning string region name
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (7 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 08/21] lib/xe_ioctl: Export non-assert xe_exec function Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 10/21] lib/xe_query: Add xe_region_class() helper Zbigniew Kempczyński
` (16 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
For tests which are mixing regions (like xe_ccs) name is confusing.
As an example might be example "subtest-name-vram-1-vram-1". It's
more readable when it will be renamed to "subtest-name-vram1-vram1".
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/xe/xe_query.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 48fb5afba7..830b7e401d 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -445,7 +445,7 @@ struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region)
* xe_region_name:
* @region: region mask
*
- * Returns region string like "system" or "vram-n" where n=0...62.
+ * Returns region string like "system" or "vramN" where N=0...62.
*/
const char *xe_region_name(uint64_t region)
{
@@ -457,7 +457,7 @@ const char *xe_region_name(uint64_t region)
vrams = calloc(64, sizeof(char *));
for (int i = 0; i < 64; i++) {
if (i != 0)
- asprintf(&vrams[i], "vram-%d", i - 1);
+ asprintf(&vrams[i], "vram%d", i - 1);
else
asprintf(&vrams[i], "system");
igt_assert(vrams[i]);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 10/21] lib/xe_query: Add xe_region_class() helper
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (8 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 09/21] lib/xe_query: Use vramN when returning string region name Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 11/21] lib/drmtest: Add get_intel_driver() helper Zbigniew Kempczyński
` (15 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
In the common code we often need to be aware of region class.
Add helper which returns it from region id.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/xe/xe_query.c | 16 ++++++++++++++++
lib/xe/xe_query.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 830b7e401d..f535ad8534 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -467,6 +467,22 @@ const char *xe_region_name(uint64_t region)
return vrams[region_idx];
}
+/**
+ * xe_region_class:
+ * @fd: xe device fd
+ * @region: region mask
+ *
+ * Returns class of memory region structure for @region mask.
+ */
+uint16_t xe_region_class(int fd, uint64_t region)
+{
+ struct drm_xe_query_mem_region *memreg;
+
+ memreg = xe_mem_region(fd, region);
+
+ return memreg->mem_class;
+}
+
/**
* xe_min_page_size:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index ff328ab942..68ca5a680c 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -85,6 +85,7 @@ struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
const char *xe_region_name(uint64_t region);
+uint16_t xe_region_class(int fd, uint64_t region);
uint32_t xe_min_page_size(int fd, uint64_t region);
struct drm_xe_query_config *xe_config(int fd);
unsigned int xe_number_hw_engines(int fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 11/21] lib/drmtest: Add get_intel_driver() helper
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (9 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 10/21] lib/xe_query: Add xe_region_class() helper Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 12/21] lib/xe_util: Return dynamic subtest name for Xe Zbigniew Kempczyński
` (14 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
In libraries with i915 and Xe code divergence we might use
is_xe_device() or is_i915_device() to distinct code paths.
But to avoid additional open and string compare we can cache
this information in data structures.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/drmtest.c | 10 ++++++++++
lib/drmtest.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 5cdb0196d3..e1da66c877 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -151,6 +151,16 @@ bool is_intel_device(int fd)
return is_i915_device(fd) || is_xe_device(fd);
}
+enum intel_driver get_intel_driver(int fd)
+{
+ if (is_xe_device(fd))
+ return INTEL_DRIVER_XE;
+ else if (is_i915_device(fd))
+ return INTEL_DRIVER_I915;
+
+ igt_assert_f(0, "Device is not handled by Intel driver\n");
+}
+
static char _forced_driver[16] = "";
/**
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 9c3ea5d14c..97ab6e759e 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -124,6 +124,7 @@ bool is_nouveau_device(int fd);
bool is_vc4_device(int fd);
bool is_xe_device(int fd);
bool is_intel_device(int fd);
+enum intel_driver get_intel_driver(int fd);
/**
* do_or_die:
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 12/21] lib/xe_util: Return dynamic subtest name for Xe
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (10 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 11/21] lib/drmtest: Add get_intel_driver() helper Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper " Zbigniew Kempczyński
` (13 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
For tests which are working on more than one region using name suffix
like "vram01-system" etc. is common thing. Instead handcrafting this
naming add xe_memregion_dynamic_subtest_name() function which is
similar to memregion_dynamic_subtest_name() for i915.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/meson.build | 3 +-
lib/xe/xe_util.c | 104 +++++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_util.h | 30 ++++++++++++++
3 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 lib/xe/xe_util.c
create mode 100644 lib/xe/xe_util.h
diff --git a/lib/meson.build b/lib/meson.build
index 5523b4450e..ce11c0715f 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -105,7 +105,8 @@ lib_sources = [
'xe/xe_compute_square_kernels.c',
'xe/xe_ioctl.c',
'xe/xe_query.c',
- 'xe/xe_spin.c'
+ 'xe/xe_spin.c',
+ 'xe/xe_util.c',
]
lib_deps = [
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
new file mode 100644
index 0000000000..5f0f69a8c6
--- /dev/null
+++ b/lib/xe/xe_util.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "igt.h"
+#include "igt_syncobj.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
+
+static bool __region_belongs_to_regions_type(struct drm_xe_query_mem_region *region,
+ uint32_t *mem_regions_type,
+ int num_regions)
+{
+ for (int i = 0; i < num_regions; i++)
+ if (mem_regions_type[i] == region->mem_class)
+ return true;
+ return false;
+}
+
+struct igt_collection *
+__xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions)
+{
+ struct drm_xe_query_mem_region *memregion;
+ struct igt_collection *set = NULL;
+ uint64_t memreg = all_memory_regions(xe), region;
+ int count = 0, pos = 0;
+
+ xe_for_each_mem_region(xe, memreg, region) {
+ memregion = xe_mem_region(xe, region);
+ if (__region_belongs_to_regions_type(memregion,
+ mem_regions_type,
+ num_regions))
+ count++;
+ }
+
+ set = igt_collection_create(count);
+
+ xe_for_each_mem_region(xe, memreg, region) {
+ memregion = xe_mem_region(xe, region);
+ igt_assert(region < (1ull << 31));
+ if (__region_belongs_to_regions_type(memregion,
+ mem_regions_type,
+ num_regions)) {
+ igt_collection_set_value(set, pos++, (int)region);
+ }
+ }
+
+ igt_assert(count == pos);
+
+ return set;
+}
+
+/**
+ * xe_memregion_dynamic_subtest_name:
+ * @xe: drm fd of Xe device
+ * @igt_collection: memory region collection
+ *
+ * Function iterates over all memory regions inside the collection (keeped
+ * in the value field) and generates the name which can be used during dynamic
+ * subtest creation.
+ *
+ * Returns: newly allocated string, has to be freed by caller. Asserts if
+ * caller tries to create a name using empty collection.
+ */
+char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set)
+{
+ struct igt_collection_data *data;
+ char *name, *p;
+ uint32_t region, len;
+
+ igt_assert(set && set->size);
+ /* enough for "name%d-" * n */
+ len = set->size * 8;
+ p = name = malloc(len);
+ igt_assert(name);
+
+ for_each_collection_data(data, set) {
+ struct drm_xe_query_mem_region *memreg;
+ int r;
+
+ region = data->value;
+ memreg = xe_mem_region(xe, region);
+
+ if (XE_IS_CLASS_VRAM(memreg))
+ r = snprintf(p, len, "%s%d-",
+ xe_region_name(region),
+ memreg->instance);
+ else
+ r = snprintf(p, len, "%s-",
+ xe_region_name(region));
+
+ igt_assert(r > 0);
+ p += r;
+ len -= r;
+ }
+
+ /* remove last '-' */
+ *(p - 1) = 0;
+
+ return name;
+}
+
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
new file mode 100644
index 0000000000..9f56fa9898
--- /dev/null
+++ b/lib/xe/xe_util.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ *
+ */
+
+#ifndef XE_UTIL_H
+#define XE_UTIL_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <xe_drm.h>
+
+#define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
+ (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_SYSMEM)
+#define XE_IS_VRAM_MEMORY_REGION(fd, region) \
+ (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_VRAM)
+
+struct igt_collection *
+__xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions);
+
+#define xe_get_memory_region_set(regions, mem_region_types...) ({ \
+ unsigned int arr__[] = { mem_region_types }; \
+ __xe_get_memory_region_set(regions, arr__, ARRAY_SIZE(arr__)); \
+})
+
+char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set);
+
+#endif /* XE_UTIL_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper for Xe
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (11 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 12/21] lib/xe_util: Return dynamic subtest name for Xe Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:15 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 14/21] lib/intel_allocator: Add intel_allocator_bind() Zbigniew Kempczyński
` (12 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Before calling exec we need to prepare vm to contain valid entries.
Bind/unbind in xe expects single bind_op or vector of bind_ops what
makes preparation of it a little bit inconvinient. Add function
which iterates over list of xe_object (auxiliary structure which
describes bind information for object) and performs the bind/unbind
in one step. It also supports passing syncobj in/out to work in
pipelined executions.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
--
v3: - Drop priv field in the structure
---
lib/xe/xe_util.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_util.h | 17 +++++++
2 files changed, 142 insertions(+)
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 5f0f69a8c6..7d78065a13 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -102,3 +102,128 @@ char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set)
return name;
}
+#ifdef XEBINDDBG
+#define bind_info igt_info
+#define bind_debug igt_debug
+#else
+#define bind_info(...) {}
+#define bind_debug(...) {}
+#endif
+
+static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_list,
+ uint32_t *num_ops)
+{
+ struct drm_xe_vm_bind_op *bind_ops, *ops;
+ struct xe_object *obj;
+ uint32_t num_objects = 0, i = 0, op;
+
+ igt_list_for_each_entry(obj, obj_list, link)
+ num_objects++;
+
+ *num_ops = num_objects;
+ if (!num_objects) {
+ bind_info(" [nothing to bind]\n");
+ return NULL;
+ }
+
+ bind_ops = calloc(num_objects, sizeof(*bind_ops));
+ igt_assert(bind_ops);
+
+ igt_list_for_each_entry(obj, obj_list, link) {
+ ops = &bind_ops[i];
+
+ if (obj->bind_op == XE_OBJECT_BIND) {
+ op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC;
+ ops->obj = obj->handle;
+ } else {
+ op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC;
+ }
+
+ ops->op = op;
+ ops->obj_offset = 0;
+ ops->addr = obj->offset;
+ ops->range = obj->size;
+ ops->region = 0;
+
+ bind_info(" [%d]: [%6s] handle: %u, offset: %llx, size: %llx\n",
+ i, obj->bind_op == XE_OBJECT_BIND ? "BIND" : "UNBIND",
+ ops->obj, (long long)ops->addr, (long long)ops->range);
+ i++;
+ }
+
+ return bind_ops;
+}
+
+/**
+ * xe_bind_unbind_async:
+ * @xe: drm fd of Xe device
+ * @vm: vm to bind/unbind objects to/from
+ * @bind_engine: bind engine, 0 if default
+ * @obj_list: list of xe_object
+ * @sync_in: sync object (fence-in), 0 if there's no input dependency
+ * @sync_out: sync object (fence-out) to signal on bind/unbind completion,
+ * if 0 wait for bind/unbind completion.
+ *
+ * Function iterates over xe_object @obj_list, prepares binding operation
+ * and does bind/unbind in one step. Providing sync_in / sync_out allows
+ * working in pipelined mode. With sync_in and sync_out set to 0 function
+ * waits until binding operation is complete.
+ */
+void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
+ struct igt_list_head *obj_list,
+ uint32_t sync_in, uint32_t sync_out)
+{
+ struct drm_xe_vm_bind_op *bind_ops;
+ struct drm_xe_sync tabsyncs[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in },
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out },
+ };
+ struct drm_xe_sync *syncs;
+ uint32_t num_binds = 0;
+ int num_syncs;
+
+ bind_info("[Binding to vm: %u]\n", vm);
+ bind_ops = xe_alloc_bind_ops(obj_list, &num_binds);
+
+ if (!num_binds) {
+ if (sync_out)
+ syncobj_signal(xe, &sync_out, 1);
+ return;
+ }
+
+ if (sync_in) {
+ syncs = tabsyncs;
+ num_syncs = 2;
+ } else {
+ syncs = &tabsyncs[1];
+ num_syncs = 1;
+ }
+
+ /* User didn't pass sync out, create it and wait for completion */
+ if (!sync_out)
+ tabsyncs[1].handle = syncobj_create(xe, 0);
+
+ bind_info("[Binding syncobjs: (in: %u, out: %u)]\n",
+ tabsyncs[0].handle, tabsyncs[1].handle);
+
+ if (num_binds == 1) {
+ if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP)
+ xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0,
+ bind_ops[0].addr, bind_ops[0].range,
+ syncs, num_syncs);
+ else
+ xe_vm_unbind_async(xe, vm, bind_engine, 0,
+ bind_ops[0].addr, bind_ops[0].range,
+ syncs, num_syncs);
+ } else {
+ xe_vm_bind_array(xe, vm, bind_engine, bind_ops,
+ num_binds, syncs, num_syncs);
+ }
+
+ if (!sync_out) {
+ igt_assert_eq(syncobj_wait_err(xe, &tabsyncs[1].handle, 1, INT64_MAX, 0), 0);
+ syncobj_destroy(xe, tabsyncs[1].handle);
+ }
+
+ free(bind_ops);
+}
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index 9f56fa9898..61511dd97f 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -27,4 +27,21 @@ __xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions);
char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set);
+enum xe_bind_op {
+ XE_OBJECT_BIND,
+ XE_OBJECT_UNBIND,
+};
+
+struct xe_object {
+ uint32_t handle;
+ uint64_t offset;
+ uint64_t size;
+ enum xe_bind_op bind_op;
+ struct igt_list_head link;
+};
+
+void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
+ struct igt_list_head *obj_list,
+ uint32_t sync_in, uint32_t sync_out);
+
#endif /* XE_UTIL_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper for Xe
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper " Zbigniew Kempczyński
@ 2023-07-13 7:15 ` Karolina Stolarek
2023-07-13 7:53 ` Zbigniew Kempczyński
0 siblings, 1 reply; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:15 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Before calling exec we need to prepare vm to contain valid entries.
> Bind/unbind in xe expects single bind_op or vector of bind_ops what
> makes preparation of it a little bit inconvinient. Add function
> which iterates over list of xe_object (auxiliary structure which
> describes bind information for object) and performs the bind/unbind
> in one step. It also supports passing syncobj in/out to work in
> pipelined executions.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> --
> v3: - Drop priv field in the structure
> ---
> lib/xe/xe_util.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++
> lib/xe/xe_util.h | 17 +++++++
> 2 files changed, 142 insertions(+)
>
> diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> index 5f0f69a8c6..7d78065a13 100644
> --- a/lib/xe/xe_util.c
> +++ b/lib/xe/xe_util.c
> @@ -102,3 +102,128 @@ char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set)
> return name;
> }
>
> +#ifdef XEBINDDBG
> +#define bind_info igt_info
> +#define bind_debug igt_debug
> +#else
> +#define bind_info(...) {}
> +#define bind_debug(...) {}
> +#endif
> +
> +static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_list,
> + uint32_t *num_ops)
> +{
> + struct drm_xe_vm_bind_op *bind_ops, *ops;
> + struct xe_object *obj;
> + uint32_t num_objects = 0, i = 0, op;
> +
> + igt_list_for_each_entry(obj, obj_list, link)
> + num_objects++;
> +
> + *num_ops = num_objects;
> + if (!num_objects) {
> + bind_info(" [nothing to bind]\n");
> + return NULL;
> + }
> +
> + bind_ops = calloc(num_objects, sizeof(*bind_ops));
> + igt_assert(bind_ops);
> +
> + igt_list_for_each_entry(obj, obj_list, link) {
> + ops = &bind_ops[i];
> +
> + if (obj->bind_op == XE_OBJECT_BIND) {
> + op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC;
> + ops->obj = obj->handle;
> + } else {
> + op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC;
> + }
> +
> + ops->op = op;
> + ops->obj_offset = 0;
> + ops->addr = obj->offset;
> + ops->range = obj->size;
> + ops->region = 0;
> +
> + bind_info(" [%d]: [%6s] handle: %u, offset: %llx, size: %llx\n",
> + i, obj->bind_op == XE_OBJECT_BIND ? "BIND" : "UNBIND",
> + ops->obj, (long long)ops->addr, (long long)ops->range);
> + i++;
> + }
> +
> + return bind_ops;
> +}
> +
> +/**
> + * xe_bind_unbind_async:
> + * @xe: drm fd of Xe device
> + * @vm: vm to bind/unbind objects to/from
> + * @bind_engine: bind engine, 0 if default
> + * @obj_list: list of xe_object
> + * @sync_in: sync object (fence-in), 0 if there's no input dependency
> + * @sync_out: sync object (fence-out) to signal on bind/unbind completion,
> + * if 0 wait for bind/unbind completion.
> + *
> + * Function iterates over xe_object @obj_list, prepares binding operation
> + * and does bind/unbind in one step. Providing sync_in / sync_out allows
> + * working in pipelined mode. With sync_in and sync_out set to 0 function
> + * waits until binding operation is complete.
> + */
> +void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
> + struct igt_list_head *obj_list,
> + uint32_t sync_in, uint32_t sync_out)
> +{
> + struct drm_xe_vm_bind_op *bind_ops;
> + struct drm_xe_sync tabsyncs[2] = {
> + { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in },
> + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out },
> + };
> + struct drm_xe_sync *syncs;
> + uint32_t num_binds = 0;
> + int num_syncs;
> +
> + bind_info("[Binding to vm: %u]\n", vm);
> + bind_ops = xe_alloc_bind_ops(obj_list, &num_binds);
> +
> + if (!num_binds) {
> + if (sync_out)
> + syncobj_signal(xe, &sync_out, 1);
> + return;
> + }
> +
> + if (sync_in) {
> + syncs = tabsyncs;
> + num_syncs = 2;
> + } else {
> + syncs = &tabsyncs[1];
> + num_syncs = 1;
> + }
> +
> + /* User didn't pass sync out, create it and wait for completion */
> + if (!sync_out)
> + tabsyncs[1].handle = syncobj_create(xe, 0);
> +
> + bind_info("[Binding syncobjs: (in: %u, out: %u)]\n",
> + tabsyncs[0].handle, tabsyncs[1].handle);
> +
> + if (num_binds == 1) {
> + if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP)
> + xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0,
> + bind_ops[0].addr, bind_ops[0].range,
> + syncs, num_syncs);
I just noticed that the alignment is off by 1 space. Could you fix it
before merging? Sorry about overlooking that bit.
All the best,
Karolina
> + else
> + xe_vm_unbind_async(xe, vm, bind_engine, 0,
> + bind_ops[0].addr, bind_ops[0].range,
> + syncs, num_syncs);
> + } else {
> + xe_vm_bind_array(xe, vm, bind_engine, bind_ops,
> + num_binds, syncs, num_syncs);
> + }
> +
> + if (!sync_out) {
> + igt_assert_eq(syncobj_wait_err(xe, &tabsyncs[1].handle, 1, INT64_MAX, 0), 0);
> + syncobj_destroy(xe, tabsyncs[1].handle);
> + }
> +
> + free(bind_ops);
> +}
> diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> index 9f56fa9898..61511dd97f 100644
> --- a/lib/xe/xe_util.h
> +++ b/lib/xe/xe_util.h
> @@ -27,4 +27,21 @@ __xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions);
>
> char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set);
>
> +enum xe_bind_op {
> + XE_OBJECT_BIND,
> + XE_OBJECT_UNBIND,
> +};
> +
> +struct xe_object {
> + uint32_t handle;
> + uint64_t offset;
> + uint64_t size;
> + enum xe_bind_op bind_op;
> + struct igt_list_head link;
> +};
> +
> +void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
> + struct igt_list_head *obj_list,
> + uint32_t sync_in, uint32_t sync_out);
> +
> #endif /* XE_UTIL_H */
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper for Xe
2023-07-13 7:15 ` Karolina Stolarek
@ 2023-07-13 7:53 ` Zbigniew Kempczyński
0 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-13 7:53 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Thu, Jul 13, 2023 at 09:15:52AM +0200, Karolina Stolarek wrote:
> On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> > Before calling exec we need to prepare vm to contain valid entries.
> > Bind/unbind in xe expects single bind_op or vector of bind_ops what
> > makes preparation of it a little bit inconvinient. Add function
> > which iterates over list of xe_object (auxiliary structure which
> > describes bind information for object) and performs the bind/unbind
> > in one step. It also supports passing syncobj in/out to work in
> > pipelined executions.
> >
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> > --
> > v3: - Drop priv field in the structure
> > ---
> > lib/xe/xe_util.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++
> > lib/xe/xe_util.h | 17 +++++++
> > 2 files changed, 142 insertions(+)
> >
> > diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
> > index 5f0f69a8c6..7d78065a13 100644
> > --- a/lib/xe/xe_util.c
> > +++ b/lib/xe/xe_util.c
> > @@ -102,3 +102,128 @@ char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set)
> > return name;
> > }
> > +#ifdef XEBINDDBG
> > +#define bind_info igt_info
> > +#define bind_debug igt_debug
> > +#else
> > +#define bind_info(...) {}
> > +#define bind_debug(...) {}
> > +#endif
> > +
> > +static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_list,
> > + uint32_t *num_ops)
> > +{
> > + struct drm_xe_vm_bind_op *bind_ops, *ops;
> > + struct xe_object *obj;
> > + uint32_t num_objects = 0, i = 0, op;
> > +
> > + igt_list_for_each_entry(obj, obj_list, link)
> > + num_objects++;
> > +
> > + *num_ops = num_objects;
> > + if (!num_objects) {
> > + bind_info(" [nothing to bind]\n");
> > + return NULL;
> > + }
> > +
> > + bind_ops = calloc(num_objects, sizeof(*bind_ops));
> > + igt_assert(bind_ops);
> > +
> > + igt_list_for_each_entry(obj, obj_list, link) {
> > + ops = &bind_ops[i];
> > +
> > + if (obj->bind_op == XE_OBJECT_BIND) {
> > + op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC;
> > + ops->obj = obj->handle;
> > + } else {
> > + op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC;
> > + }
> > +
> > + ops->op = op;
> > + ops->obj_offset = 0;
> > + ops->addr = obj->offset;
> > + ops->range = obj->size;
> > + ops->region = 0;
> > +
> > + bind_info(" [%d]: [%6s] handle: %u, offset: %llx, size: %llx\n",
> > + i, obj->bind_op == XE_OBJECT_BIND ? "BIND" : "UNBIND",
> > + ops->obj, (long long)ops->addr, (long long)ops->range);
> > + i++;
> > + }
> > +
> > + return bind_ops;
> > +}
> > +
> > +/**
> > + * xe_bind_unbind_async:
> > + * @xe: drm fd of Xe device
> > + * @vm: vm to bind/unbind objects to/from
> > + * @bind_engine: bind engine, 0 if default
> > + * @obj_list: list of xe_object
> > + * @sync_in: sync object (fence-in), 0 if there's no input dependency
> > + * @sync_out: sync object (fence-out) to signal on bind/unbind completion,
> > + * if 0 wait for bind/unbind completion.
> > + *
> > + * Function iterates over xe_object @obj_list, prepares binding operation
> > + * and does bind/unbind in one step. Providing sync_in / sync_out allows
> > + * working in pipelined mode. With sync_in and sync_out set to 0 function
> > + * waits until binding operation is complete.
> > + */
> > +void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
> > + struct igt_list_head *obj_list,
> > + uint32_t sync_in, uint32_t sync_out)
> > +{
> > + struct drm_xe_vm_bind_op *bind_ops;
> > + struct drm_xe_sync tabsyncs[2] = {
> > + { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in },
> > + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out },
> > + };
> > + struct drm_xe_sync *syncs;
> > + uint32_t num_binds = 0;
> > + int num_syncs;
> > +
> > + bind_info("[Binding to vm: %u]\n", vm);
> > + bind_ops = xe_alloc_bind_ops(obj_list, &num_binds);
> > +
> > + if (!num_binds) {
> > + if (sync_out)
> > + syncobj_signal(xe, &sync_out, 1);
> > + return;
> > + }
> > +
> > + if (sync_in) {
> > + syncs = tabsyncs;
> > + num_syncs = 2;
> > + } else {
> > + syncs = &tabsyncs[1];
> > + num_syncs = 1;
> > + }
> > +
> > + /* User didn't pass sync out, create it and wait for completion */
> > + if (!sync_out)
> > + tabsyncs[1].handle = syncobj_create(xe, 0);
> > +
> > + bind_info("[Binding syncobjs: (in: %u, out: %u)]\n",
> > + tabsyncs[0].handle, tabsyncs[1].handle);
> > +
> > + if (num_binds == 1) {
> > + if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP)
> > + xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0,
> > + bind_ops[0].addr, bind_ops[0].range,
> > + syncs, num_syncs);
>
> I just noticed that the alignment is off by 1 space. Could you fix it before
> merging? Sorry about overlooking that bit.
Sure, I've also overlooked this as my editor has a bug and it moves this
function call arguments in second and third line one char to the left.
Thanks for spotting this before merging.
--
Zbigniew
>
> All the best,
> Karolina
>
> > + else
> > + xe_vm_unbind_async(xe, vm, bind_engine, 0,
> > + bind_ops[0].addr, bind_ops[0].range,
> > + syncs, num_syncs);
> > + } else {
> > + xe_vm_bind_array(xe, vm, bind_engine, bind_ops,
> > + num_binds, syncs, num_syncs);
> > + }
> > +
> > + if (!sync_out) {
> > + igt_assert_eq(syncobj_wait_err(xe, &tabsyncs[1].handle, 1, INT64_MAX, 0), 0);
> > + syncobj_destroy(xe, tabsyncs[1].handle);
> > + }
> > +
> > + free(bind_ops);
> > +}
> > diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
> > index 9f56fa9898..61511dd97f 100644
> > --- a/lib/xe/xe_util.h
> > +++ b/lib/xe/xe_util.h
> > @@ -27,4 +27,21 @@ __xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions);
> > char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set);
> > +enum xe_bind_op {
> > + XE_OBJECT_BIND,
> > + XE_OBJECT_UNBIND,
> > +};
> > +
> > +struct xe_object {
> > + uint32_t handle;
> > + uint64_t offset;
> > + uint64_t size;
> > + enum xe_bind_op bind_op;
> > + struct igt_list_head link;
> > +};
> > +
> > +void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine,
> > + struct igt_list_head *obj_list,
> > + uint32_t sync_in, uint32_t sync_out);
> > +
> > #endif /* XE_UTIL_H */
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 14/21] lib/intel_allocator: Add intel_allocator_bind()
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (12 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 13/21] lib/xe_util: Add vm bind/unbind helper " Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:17 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 15/21] lib/intel_ctx: Add xe context information Zbigniew Kempczyński
` (11 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Synchronize allocator state to vm.
This change allows xe user to execute vm-bind/unbind for allocator
alloc()/free() operations which occurred since last binding/unbinding.
Before doing exec user should call intel_allocator_bind() to ensure
all vma's are in place.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
v2: Rewrite tracking mechanism: previous code uses bind map embedded
in allocator structure. Unfortunately this wasn't good idea
- for xe binding everything was fine, but it regress multiprocess/
multithreaded allocations. Main reason of this was children
processes couldn't get its reference as this memory was allocated
on allocator thread (separate process). Currently each child
contains its own separate tracking maps for ahnd and for each
ahnd bind map.
v3: - Don't use priv field (we may clean bind_map apriori as failing
asserts and outdated bind_map is not a problem anymore).
- Use only vm on tracking ahnd (Karolina)
- Add braces to avoid checkpatch complaining (Karolina)
- Use igt_assert_f() instead conditional block (Karolina)
---
lib/igt_core.c | 5 +
lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++-
lib/intel_allocator.h | 3 +
3 files changed, 265 insertions(+), 2 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 2ae2cb6883..041e4b3288 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -74,6 +74,7 @@
#include "igt_sysrq.h"
#include "igt_rc.h"
#include "igt_list.h"
+#include "igt_map.h"
#include "igt_device_scan.h"
#include "igt_thread.h"
#include "runnercomms.h"
@@ -320,6 +321,8 @@ bool test_multi_fork_child;
/* For allocator purposes */
pid_t child_pid = -1;
__thread pid_t child_tid = -1;
+struct igt_map *ahnd_map;
+pthread_mutex_t ahnd_map_mutex;
enum {
/*
@@ -2523,6 +2526,8 @@ bool __igt_fork(void)
case 0:
test_child = true;
pthread_mutex_init(&print_mutex, NULL);
+ pthread_mutex_init(&ahnd_map_mutex, NULL);
+ ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64);
child_pid = getpid();
child_tid = -1;
exit_handler_count = 0;
diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
index cf964ccc41..f0a9b7fb53 100644
--- a/lib/intel_allocator.c
+++ b/lib/intel_allocator.c
@@ -17,8 +17,8 @@
#include "intel_allocator.h"
#include "intel_allocator_msgchannel.h"
#include "xe/xe_query.h"
+#include "xe/xe_util.h"
-//#define ALLOCDBG
#ifdef ALLOCDBG
#define alloc_info igt_info
#define alloc_debug igt_debug
@@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type)
#define alloc_debug(...) {}
#endif
+#ifdef ALLOCBINDDBG
+#define bind_info igt_info
+#define bind_debug igt_debug
+#else
+#define bind_info(...) {}
+#define bind_debug(...) {}
+#endif
+
/*
* We limit allocator space to avoid hang when batch would be
* pinned in the last page.
@@ -64,6 +72,30 @@ struct handle_entry {
struct allocator *al;
};
+/* For tracking alloc()/free() for Xe */
+struct ahnd_info {
+ int fd;
+ uint64_t ahnd;
+ uint32_t vm;
+ enum intel_driver driver;
+ struct igt_map *bind_map;
+ pthread_mutex_t bind_map_mutex;
+};
+
+enum allocator_bind_op {
+ BOUND,
+ TO_BIND,
+ TO_UNBIND,
+};
+
+struct allocator_object {
+ uint32_t handle;
+ uint64_t offset;
+ uint64_t size;
+
+ enum allocator_bind_op bind_op;
+};
+
struct intel_allocator *
intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end);
struct intel_allocator *
@@ -122,6 +154,13 @@ static pid_t allocator_pid = -1;
extern pid_t child_pid;
extern __thread pid_t child_tid;
+/*
+ * Track alloc()/free() requires storing in local process which has
+ * an access to real drm fd it can work on.
+ */
+extern struct igt_map *ahnd_map;
+extern pthread_mutex_t ahnd_map_mutex;
+
/*
* - for parent process we have child_pid == -1
* - for child which calls intel_allocator_init() allocator_pid == child_pid
@@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void)
}
}
+static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm)
+{
+ struct ahnd_info *ainfo;
+
+ pthread_mutex_lock(&ahnd_map_mutex);
+ ainfo = igt_map_search(ahnd_map, &ahnd);
+ if (!ainfo) {
+ ainfo = malloc(sizeof(*ainfo));
+ ainfo->fd = fd;
+ ainfo->ahnd = ahnd;
+ ainfo->vm = vm;
+ ainfo->driver = get_intel_driver(fd);
+ ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
+ pthread_mutex_init(&ainfo->bind_map_mutex, NULL);
+ bind_debug("[TRACK AHND] pid: %d, tid: %d, create <fd: %d, "
+ "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n",
+ getpid(), gettid(), ainfo->fd,
+ (long long)ainfo->ahnd, ainfo->vm,
+ ainfo->driver, ahnd_map, ainfo->bind_map);
+ igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo);
+ }
+
+ pthread_mutex_unlock(&ahnd_map_mutex);
+}
+
+static void untrack_ahnd(uint64_t ahnd)
+{
+ struct ahnd_info *ainfo;
+
+ pthread_mutex_lock(&ahnd_map_mutex);
+ ainfo = igt_map_search(ahnd_map, &ahnd);
+ if (ainfo) {
+ bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n",
+ getpid(), gettid(), (long long)ahnd);
+ igt_map_remove(ahnd_map, &ahnd, map_entry_free_func);
+ }
+ pthread_mutex_unlock(&ahnd_map_mutex);
+}
+
static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
uint32_t vm,
uint64_t start, uint64_t end,
@@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
igt_assert(resp.open.allocator_handle);
igt_assert(resp.response_type == RESP_OPEN);
+ /*
+ * Igts mostly uses ctx as id when opening the allocator (i915 legacy).
+ * If ctx is passed let's use it as an vm id, otherwise use vm.
+ */
+ track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm);
+
return resp.open.allocator_handle;
}
@@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle)
igt_assert(handle_request(&req, &resp) == 0);
igt_assert(resp.response_type == RESP_CLOSE);
+ untrack_ahnd(allocator_handle);
+
return resp.close.is_empty;
}
@@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle,
*endp = resp.address_range.end;
}
+static bool is_same(struct allocator_object *obj,
+ uint32_t handle, uint64_t offset, uint64_t size,
+ enum allocator_bind_op bind_op)
+{
+ return obj->handle == handle && obj->offset == offset && obj->size == size &&
+ (obj->bind_op == bind_op || obj->bind_op == BOUND);
+}
+
+static void track_object(uint64_t allocator_handle, uint32_t handle,
+ uint64_t offset, uint64_t size,
+ enum allocator_bind_op bind_op)
+{
+ struct ahnd_info *ainfo;
+ struct allocator_object *obj;
+
+ bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n",
+ bind_op == TO_BIND ? "BIND" : "UNBIND",
+ getpid(), gettid(),
+ (long long)allocator_handle,
+ handle, (long long)offset, (long long)size);
+
+ if (offset == ALLOC_INVALID_ADDRESS) {
+ bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n",
+ (long long)offset);
+ return;
+ }
+
+ pthread_mutex_lock(&ahnd_map_mutex);
+ ainfo = igt_map_search(ahnd_map, &allocator_handle);
+ pthread_mutex_unlock(&ahnd_map_mutex);
+ igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n",
+ (long long)allocator_handle);
+
+ if (ainfo->driver == INTEL_DRIVER_I915)
+ return; /* no-op for i915, at least for now */
+
+ pthread_mutex_lock(&ainfo->bind_map_mutex);
+ obj = igt_map_search(ainfo->bind_map, &handle);
+ if (obj) {
+ /*
+ * User may call alloc() couple of times, check object is the
+ * same. For free() there's simple case, just remove from
+ * bind_map.
+ */
+ if (bind_op == TO_BIND) {
+ igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true);
+ } else if (bind_op == TO_UNBIND) {
+ if (obj->bind_op == TO_BIND)
+ igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func);
+ else if (obj->bind_op == BOUND)
+ obj->bind_op = bind_op;
+ }
+ } else {
+ /* Ignore to unbind bo which wasn't previously inserted */
+ if (bind_op == TO_UNBIND)
+ goto out;
+
+ obj = calloc(1, sizeof(*obj));
+ obj->handle = handle;
+ obj->offset = offset;
+ obj->size = size;
+ obj->bind_op = bind_op;
+ igt_map_insert(ainfo->bind_map, &obj->handle, obj);
+ }
+out:
+ pthread_mutex_unlock(&ainfo->bind_map_mutex);
+}
+
/**
* __intel_allocator_alloc:
* @allocator_handle: handle to an allocator
@@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle,
igt_assert(handle_request(&req, &resp) == 0);
igt_assert(resp.response_type == RESP_ALLOC);
+ track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND);
+
return resp.alloc.offset;
}
@@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle)
igt_assert(handle_request(&req, &resp) == 0);
igt_assert(resp.response_type == RESP_FREE);
+ track_object(allocator_handle, handle, 0, 0, TO_UNBIND);
+
return resp.free.freed;
}
@@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle)
}
}
+static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out)
+{
+ struct allocator_object *obj;
+ struct igt_map_entry *pos;
+ struct igt_list_head obj_list;
+ struct xe_object *entry, *tmp;
+
+ IGT_INIT_LIST_HEAD(&obj_list);
+
+ pthread_mutex_lock(&ainfo->bind_map_mutex);
+ igt_map_foreach(ainfo->bind_map, pos) {
+ obj = pos->data;
+
+ if (obj->bind_op == BOUND)
+ continue;
+
+ bind_info("= [vm: %u] %s => %u %lx %lx\n",
+ ainfo->vm,
+ obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND",
+ obj->handle, obj->offset,
+ obj->size);
+
+ entry = malloc(sizeof(*entry));
+ entry->handle = obj->handle;
+ entry->offset = obj->offset;
+ entry->size = obj->size;
+ entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND :
+ XE_OBJECT_UNBIND;
+ igt_list_add(&entry->link, &obj_list);
+
+ /*
+ * We clean bind_map even before calling bind/unbind
+ * as all binding operations asserts in case of error.
+ */
+ if (obj->bind_op == TO_BIND)
+ obj->bind_op = BOUND;
+ else
+ igt_map_remove(ainfo->bind_map, &obj->handle,
+ map_entry_free_func);
+ }
+ pthread_mutex_unlock(&ainfo->bind_map_mutex);
+
+ xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out);
+
+ igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) {
+ igt_list_del(&entry->link);
+ free(entry);
+ }
+}
+
+/**
+ * intel_allocator_bind:
+ * @allocator_handle: handle to an allocator
+ * @sync_in: syncobj (fence-in)
+ * @sync_out: syncobj (fence-out)
+ *
+ * Function binds and unbinds all objects added to the allocator which weren't
+ * previously binded/unbinded.
+ *
+ **/
+void intel_allocator_bind(uint64_t allocator_handle,
+ uint32_t sync_in, uint32_t sync_out)
+{
+ struct ahnd_info *ainfo;
+
+ pthread_mutex_lock(&ahnd_map_mutex);
+ ainfo = igt_map_search(ahnd_map, &allocator_handle);
+ pthread_mutex_unlock(&ahnd_map_mutex);
+ igt_assert(ainfo);
+
+ /*
+ * We collect bind/unbind operations on alloc()/free() to do group
+ * operation getting @sync_in as syncobj handle (fence-in). If user
+ * passes 0 as @sync_out we bind/unbind synchronously.
+ */
+ __xe_op_bind(ainfo, sync_in, sync_out);
+}
+
static int equal_handles(const void *key1, const void *key2)
{
const struct handle_entry *h1 = key1, *h2 = key2;
@@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators)
igt_map_destroy(map, map_entry_free_func);
}
+static void __free_ahnd_map(void)
+{
+ struct igt_map_entry *pos;
+ struct ahnd_info *ainfo;
+
+ if (!ahnd_map)
+ return;
+
+ igt_map_foreach(ahnd_map, pos) {
+ ainfo = pos->data;
+ igt_map_destroy(ainfo->bind_map, map_entry_free_func);
+ }
+
+ igt_map_destroy(ahnd_map, map_entry_free_func);
+}
+
/**
* intel_allocator_init:
*
@@ -1400,12 +1652,15 @@ void intel_allocator_init(void)
__free_maps(handles, true);
__free_maps(ctx_map, false);
__free_maps(vm_map, false);
+ __free_ahnd_map();
atomic_init(&next_handle, 1);
handles = igt_map_create(hash_handles, equal_handles);
ctx_map = igt_map_create(hash_instance, equal_ctx);
vm_map = igt_map_create(hash_instance, equal_vm);
- igt_assert(handles && ctx_map && vm_map);
+ pthread_mutex_init(&ahnd_map_mutex, NULL);
+ ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64);
+ igt_assert(handles && ctx_map && vm_map && ahnd_map);
channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE);
}
diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h
index 3ec74f6191..f9ff7f1cc9 100644
--- a/lib/intel_allocator.h
+++ b/lib/intel_allocator.h
@@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle,
void intel_allocator_print(uint64_t allocator_handle);
+void intel_allocator_bind(uint64_t allocator_handle,
+ uint32_t sync_in, uint32_t sync_out);
+
#define ALLOC_INVALID_ADDRESS (-1ull)
#define INTEL_ALLOCATOR_NONE 0
#define INTEL_ALLOCATOR_RELOC 1
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 14/21] lib/intel_allocator: Add intel_allocator_bind()
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 14/21] lib/intel_allocator: Add intel_allocator_bind() Zbigniew Kempczyński
@ 2023-07-13 7:17 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:17 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Synchronize allocator state to vm.
>
> This change allows xe user to execute vm-bind/unbind for allocator
> alloc()/free() operations which occurred since last binding/unbinding.
> Before doing exec user should call intel_allocator_bind() to ensure
> all vma's are in place.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
You've clarified my doubts, so:
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> v2: Rewrite tracking mechanism: previous code uses bind map embedded
> in allocator structure. Unfortunately this wasn't good idea
> - for xe binding everything was fine, but it regress multiprocess/
> multithreaded allocations. Main reason of this was children
> processes couldn't get its reference as this memory was allocated
> on allocator thread (separate process). Currently each child
> contains its own separate tracking maps for ahnd and for each
> ahnd bind map.
> v3: - Don't use priv field (we may clean bind_map apriori as failing
> asserts and outdated bind_map is not a problem anymore).
> - Use only vm on tracking ahnd (Karolina)
> - Add braces to avoid checkpatch complaining (Karolina)
> - Use igt_assert_f() instead conditional block (Karolina)
> ---
> lib/igt_core.c | 5 +
> lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++-
> lib/intel_allocator.h | 3 +
> 3 files changed, 265 insertions(+), 2 deletions(-)
>
> diff --git a/lib/igt_core.c b/lib/igt_core.c
> index 2ae2cb6883..041e4b3288 100644
> --- a/lib/igt_core.c
> +++ b/lib/igt_core.c
> @@ -74,6 +74,7 @@
> #include "igt_sysrq.h"
> #include "igt_rc.h"
> #include "igt_list.h"
> +#include "igt_map.h"
> #include "igt_device_scan.h"
> #include "igt_thread.h"
> #include "runnercomms.h"
> @@ -320,6 +321,8 @@ bool test_multi_fork_child;
> /* For allocator purposes */
> pid_t child_pid = -1;
> __thread pid_t child_tid = -1;
> +struct igt_map *ahnd_map;
> +pthread_mutex_t ahnd_map_mutex;
>
> enum {
> /*
> @@ -2523,6 +2526,8 @@ bool __igt_fork(void)
> case 0:
> test_child = true;
> pthread_mutex_init(&print_mutex, NULL);
> + pthread_mutex_init(&ahnd_map_mutex, NULL);
> + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64);
> child_pid = getpid();
> child_tid = -1;
> exit_handler_count = 0;
> diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c
> index cf964ccc41..f0a9b7fb53 100644
> --- a/lib/intel_allocator.c
> +++ b/lib/intel_allocator.c
> @@ -17,8 +17,8 @@
> #include "intel_allocator.h"
> #include "intel_allocator_msgchannel.h"
> #include "xe/xe_query.h"
> +#include "xe/xe_util.h"
>
> -//#define ALLOCDBG
> #ifdef ALLOCDBG
> #define alloc_info igt_info
> #define alloc_debug igt_debug
> @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type)
> #define alloc_debug(...) {}
> #endif
>
> +#ifdef ALLOCBINDDBG
> +#define bind_info igt_info
> +#define bind_debug igt_debug
> +#else
> +#define bind_info(...) {}
> +#define bind_debug(...) {}
> +#endif
> +
> /*
> * We limit allocator space to avoid hang when batch would be
> * pinned in the last page.
> @@ -64,6 +72,30 @@ struct handle_entry {
> struct allocator *al;
> };
>
> +/* For tracking alloc()/free() for Xe */
> +struct ahnd_info {
> + int fd;
> + uint64_t ahnd;
> + uint32_t vm;
> + enum intel_driver driver;
> + struct igt_map *bind_map;
> + pthread_mutex_t bind_map_mutex;
> +};
> +
> +enum allocator_bind_op {
> + BOUND,
> + TO_BIND,
> + TO_UNBIND,
> +};
> +
> +struct allocator_object {
> + uint32_t handle;
> + uint64_t offset;
> + uint64_t size;
> +
> + enum allocator_bind_op bind_op;
> +};
> +
> struct intel_allocator *
> intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end);
> struct intel_allocator *
> @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1;
> extern pid_t child_pid;
> extern __thread pid_t child_tid;
>
> +/*
> + * Track alloc()/free() requires storing in local process which has
> + * an access to real drm fd it can work on.
> + */
> +extern struct igt_map *ahnd_map;
> +extern pthread_mutex_t ahnd_map_mutex;
> +
> /*
> * - for parent process we have child_pid == -1
> * - for child which calls intel_allocator_init() allocator_pid == child_pid
> @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void)
> }
> }
>
> +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm)
> +{
> + struct ahnd_info *ainfo;
> +
> + pthread_mutex_lock(&ahnd_map_mutex);
> + ainfo = igt_map_search(ahnd_map, &ahnd);
> + if (!ainfo) {
> + ainfo = malloc(sizeof(*ainfo));
> + ainfo->fd = fd;
> + ainfo->ahnd = ahnd;
> + ainfo->vm = vm;
> + ainfo->driver = get_intel_driver(fd);
> + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32);
> + pthread_mutex_init(&ainfo->bind_map_mutex, NULL);
> + bind_debug("[TRACK AHND] pid: %d, tid: %d, create <fd: %d, "
> + "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n",
> + getpid(), gettid(), ainfo->fd,
> + (long long)ainfo->ahnd, ainfo->vm,
> + ainfo->driver, ahnd_map, ainfo->bind_map);
> + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo);
> + }
> +
> + pthread_mutex_unlock(&ahnd_map_mutex);
> +}
> +
> +static void untrack_ahnd(uint64_t ahnd)
> +{
> + struct ahnd_info *ainfo;
> +
> + pthread_mutex_lock(&ahnd_map_mutex);
> + ainfo = igt_map_search(ahnd_map, &ahnd);
> + if (ainfo) {
> + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n",
> + getpid(), gettid(), (long long)ahnd);
> + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func);
> + }
> + pthread_mutex_unlock(&ahnd_map_mutex);
> +}
> +
> static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
> uint32_t vm,
> uint64_t start, uint64_t end,
> @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx,
> igt_assert(resp.open.allocator_handle);
> igt_assert(resp.response_type == RESP_OPEN);
>
> + /*
> + * Igts mostly uses ctx as id when opening the allocator (i915 legacy).
> + * If ctx is passed let's use it as an vm id, otherwise use vm.
> + */
> + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm);
> +
> return resp.open.allocator_handle;
> }
>
> @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle)
> igt_assert(handle_request(&req, &resp) == 0);
> igt_assert(resp.response_type == RESP_CLOSE);
>
> + untrack_ahnd(allocator_handle);
> +
> return resp.close.is_empty;
> }
>
> @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle,
> *endp = resp.address_range.end;
> }
>
> +static bool is_same(struct allocator_object *obj,
> + uint32_t handle, uint64_t offset, uint64_t size,
> + enum allocator_bind_op bind_op)
> +{
> + return obj->handle == handle && obj->offset == offset && obj->size == size &&
> + (obj->bind_op == bind_op || obj->bind_op == BOUND);
> +}
> +
> +static void track_object(uint64_t allocator_handle, uint32_t handle,
> + uint64_t offset, uint64_t size,
> + enum allocator_bind_op bind_op)
> +{
> + struct ahnd_info *ainfo;
> + struct allocator_object *obj;
> +
> + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n",
> + bind_op == TO_BIND ? "BIND" : "UNBIND",
> + getpid(), gettid(),
> + (long long)allocator_handle,
> + handle, (long long)offset, (long long)size);
> +
> + if (offset == ALLOC_INVALID_ADDRESS) {
> + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n",
> + (long long)offset);
> + return;
> + }
> +
> + pthread_mutex_lock(&ahnd_map_mutex);
> + ainfo = igt_map_search(ahnd_map, &allocator_handle);
> + pthread_mutex_unlock(&ahnd_map_mutex);
> + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n",
> + (long long)allocator_handle);
> +
> + if (ainfo->driver == INTEL_DRIVER_I915)
> + return; /* no-op for i915, at least for now */
> +
> + pthread_mutex_lock(&ainfo->bind_map_mutex);
> + obj = igt_map_search(ainfo->bind_map, &handle);
> + if (obj) {
> + /*
> + * User may call alloc() couple of times, check object is the
> + * same. For free() there's simple case, just remove from
> + * bind_map.
> + */
> + if (bind_op == TO_BIND) {
> + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true);
> + } else if (bind_op == TO_UNBIND) {
> + if (obj->bind_op == TO_BIND)
> + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func);
> + else if (obj->bind_op == BOUND)
> + obj->bind_op = bind_op;
> + }
> + } else {
> + /* Ignore to unbind bo which wasn't previously inserted */
> + if (bind_op == TO_UNBIND)
> + goto out;
> +
> + obj = calloc(1, sizeof(*obj));
> + obj->handle = handle;
> + obj->offset = offset;
> + obj->size = size;
> + obj->bind_op = bind_op;
> + igt_map_insert(ainfo->bind_map, &obj->handle, obj);
> + }
> +out:
> + pthread_mutex_unlock(&ainfo->bind_map_mutex);
> +}
> +
> /**
> * __intel_allocator_alloc:
> * @allocator_handle: handle to an allocator
> @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle,
> igt_assert(handle_request(&req, &resp) == 0);
> igt_assert(resp.response_type == RESP_ALLOC);
>
> + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND);
> +
> return resp.alloc.offset;
> }
>
> @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle)
> igt_assert(handle_request(&req, &resp) == 0);
> igt_assert(resp.response_type == RESP_FREE);
>
> + track_object(allocator_handle, handle, 0, 0, TO_UNBIND);
> +
> return resp.free.freed;
> }
>
> @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle)
> }
> }
>
> +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out)
> +{
> + struct allocator_object *obj;
> + struct igt_map_entry *pos;
> + struct igt_list_head obj_list;
> + struct xe_object *entry, *tmp;
> +
> + IGT_INIT_LIST_HEAD(&obj_list);
> +
> + pthread_mutex_lock(&ainfo->bind_map_mutex);
> + igt_map_foreach(ainfo->bind_map, pos) {
> + obj = pos->data;
> +
> + if (obj->bind_op == BOUND)
> + continue;
> +
> + bind_info("= [vm: %u] %s => %u %lx %lx\n",
> + ainfo->vm,
> + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND",
> + obj->handle, obj->offset,
> + obj->size);
> +
> + entry = malloc(sizeof(*entry));
> + entry->handle = obj->handle;
> + entry->offset = obj->offset;
> + entry->size = obj->size;
> + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND :
> + XE_OBJECT_UNBIND;
> + igt_list_add(&entry->link, &obj_list);
> +
> + /*
> + * We clean bind_map even before calling bind/unbind
> + * as all binding operations asserts in case of error.
> + */
> + if (obj->bind_op == TO_BIND)
> + obj->bind_op = BOUND;
> + else
> + igt_map_remove(ainfo->bind_map, &obj->handle,
> + map_entry_free_func);
> + }
> + pthread_mutex_unlock(&ainfo->bind_map_mutex);
> +
> + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out);
> +
> + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) {
> + igt_list_del(&entry->link);
> + free(entry);
> + }
> +}
> +
> +/**
> + * intel_allocator_bind:
> + * @allocator_handle: handle to an allocator
> + * @sync_in: syncobj (fence-in)
> + * @sync_out: syncobj (fence-out)
> + *
> + * Function binds and unbinds all objects added to the allocator which weren't
> + * previously binded/unbinded.
> + *
> + **/
> +void intel_allocator_bind(uint64_t allocator_handle,
> + uint32_t sync_in, uint32_t sync_out)
> +{
> + struct ahnd_info *ainfo;
> +
> + pthread_mutex_lock(&ahnd_map_mutex);
> + ainfo = igt_map_search(ahnd_map, &allocator_handle);
> + pthread_mutex_unlock(&ahnd_map_mutex);
> + igt_assert(ainfo);
> +
> + /*
> + * We collect bind/unbind operations on alloc()/free() to do group
> + * operation getting @sync_in as syncobj handle (fence-in). If user
> + * passes 0 as @sync_out we bind/unbind synchronously.
> + */
> + __xe_op_bind(ainfo, sync_in, sync_out);
> +}
> +
> static int equal_handles(const void *key1, const void *key2)
> {
> const struct handle_entry *h1 = key1, *h2 = key2;
> @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators)
> igt_map_destroy(map, map_entry_free_func);
> }
>
> +static void __free_ahnd_map(void)
> +{
> + struct igt_map_entry *pos;
> + struct ahnd_info *ainfo;
> +
> + if (!ahnd_map)
> + return;
> +
> + igt_map_foreach(ahnd_map, pos) {
> + ainfo = pos->data;
> + igt_map_destroy(ainfo->bind_map, map_entry_free_func);
> + }
> +
> + igt_map_destroy(ahnd_map, map_entry_free_func);
> +}
> +
> /**
> * intel_allocator_init:
> *
> @@ -1400,12 +1652,15 @@ void intel_allocator_init(void)
> __free_maps(handles, true);
> __free_maps(ctx_map, false);
> __free_maps(vm_map, false);
> + __free_ahnd_map();
>
> atomic_init(&next_handle, 1);
> handles = igt_map_create(hash_handles, equal_handles);
> ctx_map = igt_map_create(hash_instance, equal_ctx);
> vm_map = igt_map_create(hash_instance, equal_vm);
> - igt_assert(handles && ctx_map && vm_map);
> + pthread_mutex_init(&ahnd_map_mutex, NULL);
> + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64);
> + igt_assert(handles && ctx_map && vm_map && ahnd_map);
>
> channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE);
> }
> diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h
> index 3ec74f6191..f9ff7f1cc9 100644
> --- a/lib/intel_allocator.h
> +++ b/lib/intel_allocator.h
> @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle,
>
> void intel_allocator_print(uint64_t allocator_handle);
>
> +void intel_allocator_bind(uint64_t allocator_handle,
> + uint32_t sync_in, uint32_t sync_out);
> +
> #define ALLOC_INVALID_ADDRESS (-1ull)
> #define INTEL_ALLOCATOR_NONE 0
> #define INTEL_ALLOCATOR_RELOC 1
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 15/21] lib/intel_ctx: Add xe context information
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (13 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 14/21] lib/intel_allocator: Add intel_allocator_bind() Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:22 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 16/21] lib/intel_blt: Introduce blt_copy_init() helper to cache driver Zbigniew Kempczyński
` (10 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Most complicated part in adopting i915_blt to intel_blt - which should
handle both drivers - is how to achieve pipelined execution. In term
pipelined execution I mean all gpu workloads are executed without
stalls.
Comparing to i915 relocations and softpinning xe architecture migrates
binding (this means also unbind operation) responsibility from the
kernel to user via vm_bind ioctl(). To avoid stalls user has to
provide in/out fences (syncobjs) between consecutive bindings/execs.
Of course for many igt tests we don't need pipelined execution,
just synchronous bind, then exec. But exercising the driver should
also cover pipelining to verify it is possible to work without stalls.
I decided to extend intel_ctx_t with all necessary for xe objects
(vm, engine, syncobjs) to get flexibility in deciding how to bind,
execute and wait for (synchronize) those operations. Context object
along with i915 engine is already passed to blitter library so adding
xe required fields doesn't break i915 but will allow xe path to get
all necessary data to execute.
Using intel_ctx with xe requires some code patterns caused by usage
of an allocator. For xe the allocator started tracking alloc()/free()
operations to do bind/unbind in one call just before execution.
I've added two helpers in intel_ctx which - intel_ctx_xe_exec()
and intel_ctx_xe_sync(). Depending how intel_ctx was created
(with 0 or real syncobj handles as in/bind/out fences) bind and exec
in intel_ctx_xe_exec() are pipelined but synchronize last operation
(exec). For real syncobjs they are used to join bind + exec calls
but there's no wait for exec (sync-out) completion. This allows
building more cascaded bind + exec operations without stalls.
To wait for a sync-out fence caller may use intel_ctx_xe_sync()
which is synchronous wait on syncobj. It allows user to reset
fences to prepare for next operation.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
v3: drop local __xe_exec() (Karolina)
---
lib/intel_ctx.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++-
lib/intel_ctx.h | 14 +++++++
2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index ded9c0f1e4..0c1ce6d10b 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -5,9 +5,12 @@
#include <stddef.h>
+#include "i915/gem_engine_topology.h"
+#include "igt_syncobj.h"
+#include "intel_allocator.h"
#include "intel_ctx.h"
#include "ioctl_wrappers.h"
-#include "i915/gem_engine_topology.h"
+#include "xe/xe_ioctl.h"
/**
* SECTION:intel_ctx
@@ -390,3 +393,96 @@ unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine)
{
return intel_ctx_cfg_engine_class(&ctx->cfg, engine);
}
+
+/**
+ * intel_ctx_xe:
+ * @fd: open i915 drm file descriptor
+ * @vm: vm
+ * @engine: engine
+ *
+ * Returns an intel_ctx_t representing the xe context.
+ */
+intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine,
+ uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out)
+{
+ intel_ctx_t *ctx;
+
+ ctx = calloc(1, sizeof(*ctx));
+ igt_assert(ctx);
+
+ ctx->fd = fd;
+ ctx->vm = vm;
+ ctx->engine = engine;
+ ctx->sync_in = sync_in;
+ ctx->sync_bind = sync_bind;
+ ctx->sync_out = sync_out;
+
+ return ctx;
+}
+
+int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset)
+{
+ struct drm_xe_sync syncs[2] = {
+ { .flags = DRM_XE_SYNC_SYNCOBJ, },
+ { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ };
+ struct drm_xe_exec exec = {
+ .engine_id = ctx->engine,
+ .syncs = (uintptr_t)syncs,
+ .num_syncs = 2,
+ .address = bb_offset,
+ .num_batch_buffer = 1,
+ };
+ uint32_t sync_in = ctx->sync_in;
+ uint32_t sync_bind = ctx->sync_bind ?: syncobj_create(ctx->fd, 0);
+ uint32_t sync_out = ctx->sync_out ?: syncobj_create(ctx->fd, 0);
+ int ret;
+
+ /* Synchronize allocator state -> vm */
+ intel_allocator_bind(ahnd, sync_in, sync_bind);
+
+ /* Pipelined exec */
+ syncs[0].handle = sync_bind;
+ syncs[1].handle = sync_out;
+
+ ret = __xe_exec(ctx->fd, &exec);
+ if (ret)
+ goto err;
+
+ if (!ctx->sync_bind || !ctx->sync_out)
+ syncobj_wait_err(ctx->fd, &sync_out, 1, INT64_MAX, 0);
+
+err:
+ if (!ctx->sync_bind)
+ syncobj_destroy(ctx->fd, sync_bind);
+
+ if (!ctx->sync_out)
+ syncobj_destroy(ctx->fd, sync_out);
+
+ return ret;
+}
+
+void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset)
+{
+ igt_assert_eq(__intel_ctx_xe_exec(ctx, ahnd, bb_offset), 0);
+}
+
+#define RESET_SYNCOBJ(__fd, __sync) do { \
+ if (__sync) \
+ syncobj_reset((__fd), &(__sync), 1); \
+} while (0)
+
+int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs)
+{
+ int ret;
+
+ ret = syncobj_wait_err(ctx->fd, &ctx->sync_out, 1, INT64_MAX, 0);
+
+ if (reset_syncs) {
+ RESET_SYNCOBJ(ctx->fd, ctx->sync_in);
+ RESET_SYNCOBJ(ctx->fd, ctx->sync_bind);
+ RESET_SYNCOBJ(ctx->fd, ctx->sync_out);
+ }
+
+ return ret;
+}
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
index 3cfeaae81e..59d0360ada 100644
--- a/lib/intel_ctx.h
+++ b/lib/intel_ctx.h
@@ -67,6 +67,14 @@ int intel_ctx_cfg_engine_class(const intel_ctx_cfg_t *cfg, unsigned int engine);
typedef struct intel_ctx {
uint32_t id;
intel_ctx_cfg_t cfg;
+
+ /* Xe */
+ int fd;
+ uint32_t vm;
+ uint32_t engine;
+ uint32_t sync_in;
+ uint32_t sync_bind;
+ uint32_t sync_out;
} intel_ctx_t;
int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg,
@@ -81,4 +89,10 @@ void intel_ctx_destroy(int fd, const intel_ctx_t *ctx);
unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine);
+intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine,
+ uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out);
+int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset);
+void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset);
+int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs);
+
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 15/21] lib/intel_ctx: Add xe context information
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 15/21] lib/intel_ctx: Add xe context information Zbigniew Kempczyński
@ 2023-07-13 7:22 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:22 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Most complicated part in adopting i915_blt to intel_blt - which should
> handle both drivers - is how to achieve pipelined execution. In term
> pipelined execution I mean all gpu workloads are executed without
> stalls.
>
> Comparing to i915 relocations and softpinning xe architecture migrates
> binding (this means also unbind operation) responsibility from the
> kernel to user via vm_bind ioctl(). To avoid stalls user has to
> provide in/out fences (syncobjs) between consecutive bindings/execs.
> Of course for many igt tests we don't need pipelined execution,
> just synchronous bind, then exec. But exercising the driver should
> also cover pipelining to verify it is possible to work without stalls.
>
> I decided to extend intel_ctx_t with all necessary for xe objects
> (vm, engine, syncobjs) to get flexibility in deciding how to bind,
> execute and wait for (synchronize) those operations. Context object
> along with i915 engine is already passed to blitter library so adding
> xe required fields doesn't break i915 but will allow xe path to get
> all necessary data to execute.
>
> Using intel_ctx with xe requires some code patterns caused by usage
> of an allocator. For xe the allocator started tracking alloc()/free()
> operations to do bind/unbind in one call just before execution.
> I've added two helpers in intel_ctx which - intel_ctx_xe_exec()
> and intel_ctx_xe_sync(). Depending how intel_ctx was created
> (with 0 or real syncobj handles as in/bind/out fences) bind and exec
> in intel_ctx_xe_exec() are pipelined but synchronize last operation
> (exec). For real syncobjs they are used to join bind + exec calls
> but there's no wait for exec (sync-out) completion. This allows
> building more cascaded bind + exec operations without stalls.
>
> To wait for a sync-out fence caller may use intel_ctx_xe_sync()
> which is synchronous wait on syncobj. It allows user to reset
> fences to prepare for next operation.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
I think you've forgot to add my r-b, or has something changed in v4?
There's nothing in the log.
Thanks,
Karolina
> ---
> v3: drop local __xe_exec() (Karolina)
> ---
> lib/intel_ctx.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++-
> lib/intel_ctx.h | 14 +++++++
> 2 files changed, 111 insertions(+), 1 deletion(-)
>
> diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
> index ded9c0f1e4..0c1ce6d10b 100644
> --- a/lib/intel_ctx.c
> +++ b/lib/intel_ctx.c
> @@ -5,9 +5,12 @@
>
> #include <stddef.h>
>
> +#include "i915/gem_engine_topology.h"
> +#include "igt_syncobj.h"
> +#include "intel_allocator.h"
> #include "intel_ctx.h"
> #include "ioctl_wrappers.h"
> -#include "i915/gem_engine_topology.h"
> +#include "xe/xe_ioctl.h"
>
> /**
> * SECTION:intel_ctx
> @@ -390,3 +393,96 @@ unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine)
> {
> return intel_ctx_cfg_engine_class(&ctx->cfg, engine);
> }
> +
> +/**
> + * intel_ctx_xe:
> + * @fd: open i915 drm file descriptor
> + * @vm: vm
> + * @engine: engine
> + *
> + * Returns an intel_ctx_t representing the xe context.
> + */
> +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine,
> + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out)
> +{
> + intel_ctx_t *ctx;
> +
> + ctx = calloc(1, sizeof(*ctx));
> + igt_assert(ctx);
> +
> + ctx->fd = fd;
> + ctx->vm = vm;
> + ctx->engine = engine;
> + ctx->sync_in = sync_in;
> + ctx->sync_bind = sync_bind;
> + ctx->sync_out = sync_out;
> +
> + return ctx;
> +}
> +
> +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset)
> +{
> + struct drm_xe_sync syncs[2] = {
> + { .flags = DRM_XE_SYNC_SYNCOBJ, },
> + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
> + };
> + struct drm_xe_exec exec = {
> + .engine_id = ctx->engine,
> + .syncs = (uintptr_t)syncs,
> + .num_syncs = 2,
> + .address = bb_offset,
> + .num_batch_buffer = 1,
> + };
> + uint32_t sync_in = ctx->sync_in;
> + uint32_t sync_bind = ctx->sync_bind ?: syncobj_create(ctx->fd, 0);
> + uint32_t sync_out = ctx->sync_out ?: syncobj_create(ctx->fd, 0);
> + int ret;
> +
> + /* Synchronize allocator state -> vm */
> + intel_allocator_bind(ahnd, sync_in, sync_bind);
> +
> + /* Pipelined exec */
> + syncs[0].handle = sync_bind;
> + syncs[1].handle = sync_out;
> +
> + ret = __xe_exec(ctx->fd, &exec);
> + if (ret)
> + goto err;
> +
> + if (!ctx->sync_bind || !ctx->sync_out)
> + syncobj_wait_err(ctx->fd, &sync_out, 1, INT64_MAX, 0);
> +
> +err:
> + if (!ctx->sync_bind)
> + syncobj_destroy(ctx->fd, sync_bind);
> +
> + if (!ctx->sync_out)
> + syncobj_destroy(ctx->fd, sync_out);
> +
> + return ret;
> +}
> +
> +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset)
> +{
> + igt_assert_eq(__intel_ctx_xe_exec(ctx, ahnd, bb_offset), 0);
> +}
> +
> +#define RESET_SYNCOBJ(__fd, __sync) do { \
> + if (__sync) \
> + syncobj_reset((__fd), &(__sync), 1); \
> +} while (0)
> +
> +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs)
> +{
> + int ret;
> +
> + ret = syncobj_wait_err(ctx->fd, &ctx->sync_out, 1, INT64_MAX, 0);
> +
> + if (reset_syncs) {
> + RESET_SYNCOBJ(ctx->fd, ctx->sync_in);
> + RESET_SYNCOBJ(ctx->fd, ctx->sync_bind);
> + RESET_SYNCOBJ(ctx->fd, ctx->sync_out);
> + }
> +
> + return ret;
> +}
> diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
> index 3cfeaae81e..59d0360ada 100644
> --- a/lib/intel_ctx.h
> +++ b/lib/intel_ctx.h
> @@ -67,6 +67,14 @@ int intel_ctx_cfg_engine_class(const intel_ctx_cfg_t *cfg, unsigned int engine);
> typedef struct intel_ctx {
> uint32_t id;
> intel_ctx_cfg_t cfg;
> +
> + /* Xe */
> + int fd;
> + uint32_t vm;
> + uint32_t engine;
> + uint32_t sync_in;
> + uint32_t sync_bind;
> + uint32_t sync_out;
> } intel_ctx_t;
>
> int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg,
> @@ -81,4 +89,10 @@ void intel_ctx_destroy(int fd, const intel_ctx_t *ctx);
>
> unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine);
>
> +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine,
> + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out);
> +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset);
> +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset);
> +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs);
> +
> #endif
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 16/21] lib/intel_blt: Introduce blt_copy_init() helper to cache driver
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (14 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 15/21] lib/intel_ctx: Add xe context information Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 17/21] lib/intel_blt: Extend blitter library to support xe driver Zbigniew Kempczyński
` (9 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Instead of calling is_xe_device() and is_i915_device() multiple
times in code which distincs xe and i915 paths add driver field
to structures used in blitter library.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/igt_fb.c | 2 +-
lib/intel_blt.c | 40 +++++++++++++++++++++++++++++++---
lib/intel_blt.h | 8 ++++++-
tests/i915/gem_ccs.c | 34 ++++++++++++++++-------------
tests/i915/gem_exercise_blt.c | 22 ++++++++++---------
tests/i915/gem_lmem_swapping.c | 4 ++--
6 files changed, 78 insertions(+), 32 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index a8988274f2..1814e8db11 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2900,7 +2900,7 @@ static void blitcopy(const struct igt_fb *dst_fb,
src = blt_fb_init(src_fb, i, mem_region);
dst = blt_fb_init(dst_fb, i, mem_region);
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(src_fb->fd, &blt);
blt.color_depth = blt_get_bpp(src_fb);
blt_set_copy_object(&blt.src, src);
blt_set_copy_object(&blt.dst, dst);
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 1af57c4912..059cc53b9c 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -692,6 +692,22 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
data->dw21.src_array_index);
}
+/**
+ * blt_copy_init:
+ * @fd: drm fd
+ * @blt: structure for initialization
+ *
+ * Function is zeroing @blt and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_copy_init(int fd, struct blt_copy_data *blt)
+{
+ memset(blt, 0, sizeof(*blt));
+
+ blt->fd = fd;
+ blt->driver = get_intel_driver(fd);
+}
+
/**
* emit_blt_block_copy:
* @fd: drm fd
@@ -889,6 +905,22 @@ static void dump_bb_surf_ctrl_cmd(const struct gen12_ctrl_surf_copy_data *data)
cmd[4], data->dw04.dst_address_hi, data->dw04.dst_mocs);
}
+/**
+ * blt_ctrl_surf_copy_init:
+ * @fd: drm fd
+ * @surf: structure for initialization
+ *
+ * Function is zeroing @surf and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_ctrl_surf_copy_init(int fd, struct blt_ctrl_surf_copy_data *surf)
+{
+ memset(surf, 0, sizeof(*surf));
+
+ surf->fd = fd;
+ surf->driver = get_intel_driver(fd);
+}
+
/**
* emit_blt_ctrl_surf_copy:
* @fd: drm fd
@@ -1317,7 +1349,7 @@ void blt_set_batch(struct blt_copy_batch *batch,
}
struct blt_copy_object *
-blt_create_object(int fd, uint32_t region,
+blt_create_object(const struct blt_copy_data *blt, uint32_t region,
uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
enum blt_tiling_type tiling,
enum blt_compression compression,
@@ -1329,10 +1361,12 @@ blt_create_object(int fd, uint32_t region,
uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
uint32_t handle;
+ igt_assert_f(blt->driver, "Driver isn't set, have you called blt_copy_init()?\n");
+
obj = calloc(1, sizeof(*obj));
obj->size = size;
- igt_assert(__gem_create_in_memory_regions(fd, &handle,
+ igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
&size, region) == 0);
blt_set_object(obj, handle, size, region, mocs, tiling,
@@ -1340,7 +1374,7 @@ blt_create_object(int fd, uint32_t region,
blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
if (create_mapping)
- obj->ptr = gem_mmap__device_coherent(fd, handle, 0, size,
+ obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size,
PROT_READ | PROT_WRITE);
return obj;
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index c134466d4d..307405e6e8 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -102,6 +102,7 @@ struct blt_copy_batch {
/* Common for block-copy and fast-copy */
struct blt_copy_data {
int fd;
+ enum intel_driver driver;
struct blt_copy_object src;
struct blt_copy_object dst;
struct blt_copy_batch bb;
@@ -155,6 +156,7 @@ struct blt_ctrl_surf_copy_object {
struct blt_ctrl_surf_copy_data {
int fd;
+ enum intel_driver driver;
struct blt_ctrl_surf_copy_object src;
struct blt_ctrl_surf_copy_object dst;
struct blt_copy_batch bb;
@@ -185,6 +187,8 @@ bool blt_uses_extended_block_copy(int fd);
const char *blt_tiling_name(enum blt_tiling_type tiling);
+void blt_copy_init(int fd, struct blt_copy_data *blt);
+
uint64_t emit_blt_block_copy(int fd,
uint64_t ahnd,
const struct blt_copy_data *blt,
@@ -205,6 +209,8 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
uint64_t bb_pos,
bool emit_bbe);
+void blt_ctrl_surf_copy_init(int fd, struct blt_ctrl_surf_copy_data *surf);
+
int blt_ctrl_surf_copy(int fd,
const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
@@ -230,7 +236,7 @@ void blt_set_batch(struct blt_copy_batch *batch,
uint32_t handle, uint64_t size, uint32_t region);
struct blt_copy_object *
-blt_create_object(int fd, uint32_t region,
+blt_create_object(const struct blt_copy_data *blt, uint32_t region,
uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
enum blt_tiling_type tiling,
enum blt_compression compression,
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index 8f5d5b4f96..1a5f3674a0 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -108,7 +108,7 @@ static void surf_copy(int i915,
ccs = gem_create(i915, ccssize);
ccs2 = gem_create(i915, ccssize);
- surf.fd = i915;
+ blt_ctrl_surf_copy_init(i915, &surf);
surf.print_bb = param.print_bb;
blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
uc_mocs, BLT_INDIRECT_ACCESS);
@@ -160,7 +160,7 @@ static void surf_copy(int i915,
uc_mocs, INDIRECT_ACCESS);
blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(i915, &blt);
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
blt_set_copy_object(&blt.src, mid);
@@ -251,7 +251,7 @@ static int blt_block_copy3(int i915,
bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
/* First blit src -> mid */
- memset(&blt0, 0, sizeof(blt0));
+ blt_copy_init(i915, &blt0);
blt0.src = blt3->src;
blt0.dst = blt3->mid;
blt0.bb = blt3->bb;
@@ -262,7 +262,7 @@ static int blt_block_copy3(int i915,
bb_pos = emit_blt_block_copy(i915, ahnd, &blt0, &ext0, bb_pos, false);
/* Second blit mid -> dst */
- memset(&blt0, 0, sizeof(blt0));
+ blt_copy_init(i915, &blt0);
blt0.src = blt3->mid;
blt0.dst = blt3->dst;
blt0.bb = blt3->bb;
@@ -273,7 +273,7 @@ static int blt_block_copy3(int i915,
bb_pos = emit_blt_block_copy(i915, ahnd, &blt0, &ext0, bb_pos, false);
/* Third blit dst -> final */
- memset(&blt0, 0, sizeof(blt0));
+ blt_copy_init(i915, &blt0);
blt0.src = blt3->dst;
blt0.dst = blt3->final;
blt0.bb = blt3->bb;
@@ -331,11 +331,13 @@ static void block_copy(int i915,
if (!blt_uses_extended_block_copy(i915))
pext = NULL;
- src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ blt_copy_init(i915, &blt);
+
+ src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
- mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
+ mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
mid_tiling, mid_compression, comp_type, true);
- dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
igt_assert(src->size == dst->size);
PRINT_SURFACE_INFO("src", src);
@@ -345,7 +347,6 @@ static void block_copy(int i915,
blt_surface_fill_rect(i915, src, width, height);
WRITE_PNG(i915, run_id, "src", src, width, height);
- memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
blt_set_copy_object(&blt.src, src);
@@ -390,7 +391,7 @@ static void block_copy(int i915,
}
}
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(i915, &blt);
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
blt_set_copy_object(&blt.src, mid);
@@ -427,6 +428,7 @@ static void block_multicopy(int i915,
const struct test_config *config)
{
struct blt_copy3_data blt3 = {};
+ struct blt_copy_data blt = {};
struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3;
struct blt_copy_object *src, *mid, *dst, *final;
const uint32_t bpp = 32;
@@ -446,13 +448,16 @@ static void block_multicopy(int i915,
if (!blt_uses_extended_block_copy(i915))
pext3 = NULL;
- src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ /* For object creation */
+ blt_copy_init(i915, &blt);
+
+ src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
- mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
+ mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
mid_tiling, mid_compression, comp_type, true);
- dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
mid_tiling, COMPRESSION_DISABLED, comp_type, true);
- final = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
igt_assert(src->size == dst->size);
PRINT_SURFACE_INFO("src", src);
@@ -462,7 +467,6 @@ static void block_multicopy(int i915,
blt_surface_fill_rect(i915, src, width, height);
- memset(&blt3, 0, sizeof(blt3));
blt3.color_depth = CD_32bit;
blt3.print_bb = param.print_bb;
blt_set_copy_object(&blt3.src, src);
diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
index 0cd1820430..7355eabbe9 100644
--- a/tests/i915/gem_exercise_blt.c
+++ b/tests/i915/gem_exercise_blt.c
@@ -89,7 +89,7 @@ static int fast_copy_one_bb(int i915,
bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
/* First blit */
- memset(&blt_tmp, 0, sizeof(blt_tmp));
+ blt_copy_init(i915, &blt_tmp);
blt_tmp.src = blt->src;
blt_tmp.dst = blt->mid;
blt_tmp.bb = blt->bb;
@@ -98,7 +98,7 @@ static int fast_copy_one_bb(int i915,
bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, false);
/* Second blit */
- memset(&blt_tmp, 0, sizeof(blt_tmp));
+ blt_copy_init(i915, &blt_tmp);
blt_tmp.src = blt->mid;
blt_tmp.dst = blt->dst;
blt_tmp.bb = blt->bb;
@@ -140,6 +140,7 @@ static void fast_copy_emit(int i915, const intel_ctx_t *ctx,
uint32_t region1, uint32_t region2,
enum blt_tiling_type mid_tiling)
{
+ struct blt_copy_data bltinit = {};
struct blt_fast_copy_data blt = {};
struct blt_copy_object *src, *mid, *dst;
const uint32_t bpp = 32;
@@ -152,11 +153,12 @@ static void fast_copy_emit(int i915, const intel_ctx_t *ctx,
igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
- src = blt_create_object(i915, region1, width, height, bpp, 0,
+ blt_copy_init(i915, &bltinit);
+ src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
T_LINEAR, COMPRESSION_DISABLED, 0, true);
- mid = blt_create_object(i915, region2, width, height, bpp, 0,
+ mid = blt_create_object(&bltinit, region2, width, height, bpp, 0,
mid_tiling, COMPRESSION_DISABLED, 0, true);
- dst = blt_create_object(i915, region1, width, height, bpp, 0,
+ dst = blt_create_object(&bltinit, region1, width, height, bpp, 0,
T_LINEAR, COMPRESSION_DISABLED, 0, true);
igt_assert(src->size == dst->size);
@@ -212,17 +214,17 @@ static void fast_copy(int i915, const intel_ctx_t *ctx,
igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
- src = blt_create_object(i915, region1, width, height, bpp, 0,
+ blt_copy_init(i915, &blt);
+ src = blt_create_object(&blt, region1, width, height, bpp, 0,
T_LINEAR, COMPRESSION_DISABLED, 0, true);
- mid = blt_create_object(i915, region2, width, height, bpp, 0,
+ mid = blt_create_object(&blt, region2, width, height, bpp, 0,
mid_tiling, COMPRESSION_DISABLED, 0, true);
- dst = blt_create_object(i915, region1, width, height, bpp, 0,
+ dst = blt_create_object(&blt, region1, width, height, bpp, 0,
T_LINEAR, COMPRESSION_DISABLED, 0, true);
igt_assert(src->size == dst->size);
blt_surface_fill_rect(i915, src, width, height);
- memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
blt_set_copy_object(&blt.src, src);
@@ -235,7 +237,7 @@ static void fast_copy(int i915, const intel_ctx_t *ctx,
WRITE_PNG(i915, mid_tiling, "src", &blt.src, width, height);
WRITE_PNG(i915, mid_tiling, "mid", &blt.dst, width, height);
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(i915, &blt);
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
blt_set_copy_object(&blt.src, mid);
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 83dbebec83..2921de8f9f 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -308,7 +308,7 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
buf[j] = seed++;
munmap(buf, obj->size);
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(i915, &blt);
blt.color_depth = CD_32bit;
memcpy(&blt.src, tmp, sizeof(blt.src));
@@ -366,7 +366,7 @@ verify_object_ccs(int i915, const struct object *obj,
cmd->handle = gem_create_from_pool(i915, &size, region);
blt_set_batch(cmd, cmd->handle, size, region);
- memset(&blt, 0, sizeof(blt));
+ blt_copy_init(i915, &blt);
blt.color_depth = CD_32bit;
memcpy(&blt.src, obj->blt_obj, sizeof(blt.src));
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 17/21] lib/intel_blt: Extend blitter library to support xe driver
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (15 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 16/21] lib/intel_blt: Introduce blt_copy_init() helper to cache driver Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:24 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 18/21] tests/xe_ccs: Check if flatccs is working with block-copy for Xe Zbigniew Kempczyński
` (8 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Use already written for i915 blitter library in xe development.
Add appropriate code paths which are unique for those drivers.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
v3: Extract common helpers for getting mapping and alignment (Karolina)
v4: Fix unwanted doc change (Karolina)
---
lib/intel_blt.c | 233 ++++++++++++++++++++++++++++++------------------
lib/intel_blt.h | 2 +-
2 files changed, 149 insertions(+), 86 deletions(-)
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 059cc53b9c..4657bb1aec 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -9,9 +9,13 @@
#include <malloc.h>
#include <cairo.h>
#include "drm.h"
-#include "igt.h"
#include "i915/gem_create.h"
+#include "igt.h"
+#include "igt_syncobj.h"
#include "intel_blt.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
#define BITRANGE(start, end) (end - start + 1)
#define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
@@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt)
return SM_NONE;
}
-static int __memory_type(uint32_t region)
+static int __memory_type(int fd, enum intel_driver driver, uint32_t region)
{
- igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
- IS_SYSTEM_MEMORY_REGION(region),
- "Invalid region: %x\n", region);
+ if (driver == INTEL_DRIVER_I915) {
+ igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
+ IS_SYSTEM_MEMORY_REGION(region),
+ "Invalid region: %x\n", region);
+ } else {
+ igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) ||
+ XE_IS_SYSMEM_MEMORY_REGION(fd, region),
+ "Invalid region: %x\n", region);
+ }
- if (IS_DEVICE_MEMORY_REGION(region))
+ if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region))
return TM_LOCAL_MEM;
+ else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region))
+ return TM_LOCAL_MEM;
+
return TM_SYSTEM_MEM;
}
-static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
+static enum blt_aux_mode __aux_mode(int fd,
+ enum intel_driver driver,
+ const struct blt_copy_object *obj)
{
- if (obj->compression == COMPRESSION_ENABLED) {
+ if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) {
igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region),
"XY_BLOCK_COPY_BLT supports compression "
"on device memory only\n");
return AM_AUX_CCS_E;
+ } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) {
+ igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region),
+ "XY_BLOCK_COPY_BLT supports compression "
+ "on device memory only\n");
+ return AM_AUX_CCS_E;
}
return AM_AUX_NONE;
@@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data,
data->dw00.length = extended_command ? 20 : 10;
if (__special_mode(blt) == SM_FULL_RESOLVE)
- data->dw01.dst_aux_mode = __aux_mode(&blt->src);
+ data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src);
else
- data->dw01.dst_aux_mode = __aux_mode(&blt->dst);
+ data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst);
data->dw01.dst_pitch = blt->dst.pitch - 1;
data->dw01.dst_mocs = blt->dst.mocs;
@@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data,
data->dw06.dst_x_offset = blt->dst.x_offset;
data->dw06.dst_y_offset = blt->dst.y_offset;
- data->dw06.dst_target_memory = __memory_type(blt->dst.region);
+ data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region);
data->dw07.src_x1 = blt->src.x1;
data->dw07.src_y1 = blt->src.y1;
data->dw08.src_pitch = blt->src.pitch - 1;
- data->dw08.src_aux_mode = __aux_mode(&blt->src);
+ data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src);
data->dw08.src_mocs = blt->src.mocs;
data->dw08.src_compression = blt->src.compression;
data->dw08.src_tiling = __block_tiling(blt->src.tiling);
@@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data,
data->dw11.src_x_offset = blt->src.x_offset;
data->dw11.src_y_offset = blt->src.y_offset;
- data->dw11.src_target_memory = __memory_type(blt->src.region);
+ data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region);
}
static void fill_data_ext(struct gen12_block_copy_data_ext *dext,
@@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
data->dw21.src_array_index);
}
+static uint64_t get_default_alignment(int fd, enum intel_driver driver)
+{
+ if (driver == INTEL_DRIVER_XE)
+ return xe_get_default_alignment(fd);
+
+ return gem_detect_safe_alignment(fd);
+}
+
+static void *bo_map(int fd, uint32_t handle, uint64_t size,
+ enum intel_driver driver)
+{
+ if (driver == INTEL_DRIVER_XE)
+ return xe_bo_map(fd, handle, size);
+
+ return gem_mmap__device_coherent(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+}
+
/**
* blt_copy_init:
* @fd: drm fd
@@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd,
igt_assert_f(ahnd, "block-copy supports softpin only\n");
igt_assert_f(blt, "block-copy requires data to do blit\n");
- alignment = gem_detect_safe_alignment(fd);
+ alignment = get_default_alignment(fd, blt->driver);
src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment)
+ blt->src.plane_offset;
dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment)
@@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd,
fill_data(&data, blt, src_offset, dst_offset, ext);
- bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size,
- PROT_READ | PROT_WRITE);
+ bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver);
igt_assert(bb_pos + sizeof(data) < blt->bb.size);
memcpy(bb + bb_pos, &data, sizeof(data));
@@ -812,29 +849,35 @@ int blt_block_copy(int fd,
igt_assert_f(ahnd, "block-copy supports softpin only\n");
igt_assert_f(blt, "block-copy requires data to do blit\n");
+ igt_assert_neq(blt->driver, 0);
- alignment = gem_detect_safe_alignment(fd);
+ alignment = get_default_alignment(fd, blt->driver);
src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
emit_blt_block_copy(fd, ahnd, blt, ext, 0, true);
- obj[0].offset = CANONICAL(dst_offset);
- obj[1].offset = CANONICAL(src_offset);
- obj[2].offset = CANONICAL(bb_offset);
- obj[0].handle = blt->dst.handle;
- obj[1].handle = blt->src.handle;
- obj[2].handle = blt->bb.handle;
- obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
- EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- execbuf.buffer_count = 3;
- execbuf.buffers_ptr = to_user_pointer(obj);
- execbuf.rsvd1 = ctx ? ctx->id : 0;
- execbuf.flags = e ? e->flags : I915_EXEC_BLT;
- ret = __gem_execbuf(fd, &execbuf);
+ if (blt->driver == INTEL_DRIVER_XE) {
+ intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+ } else {
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = blt->dst.handle;
+ obj[1].handle = blt->src.handle;
+ obj[2].handle = blt->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+
+ ret = __gem_execbuf(fd, &execbuf);
+ }
return ret;
}
@@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
- alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16);
+ alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16);
data.dw00.client = 0x2;
data.dw00.opcode = 0x48;
@@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
data.dw04.dst_address_hi = dst_offset >> 32;
data.dw04.dst_mocs = surf->dst.mocs;
- bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size,
- PROT_READ | PROT_WRITE);
+ bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver);
igt_assert(bb_pos + sizeof(data) < surf->bb.size);
memcpy(bb + bb_pos, &data, sizeof(data));
@@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd,
igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
+ igt_assert_neq(surf->driver, 0);
- alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16);
+ alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16);
src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment);
dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment);
bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment);
emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true);
- obj[0].offset = CANONICAL(dst_offset);
- obj[1].offset = CANONICAL(src_offset);
- obj[2].offset = CANONICAL(bb_offset);
- obj[0].handle = surf->dst.handle;
- obj[1].handle = surf->src.handle;
- obj[2].handle = surf->bb.handle;
- obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
- EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- execbuf.buffer_count = 3;
- execbuf.buffers_ptr = to_user_pointer(obj);
- execbuf.flags = e ? e->flags : I915_EXEC_BLT;
- execbuf.rsvd1 = ctx ? ctx->id : 0;
- gem_execbuf(fd, &execbuf);
- put_offset(ahnd, surf->dst.handle);
- put_offset(ahnd, surf->src.handle);
- put_offset(ahnd, surf->bb.handle);
+ if (surf->driver == INTEL_DRIVER_XE) {
+ intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+ } else {
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = surf->dst.handle;
+ obj[1].handle = surf->src.handle;
+ obj[2].handle = surf->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ gem_execbuf(fd, &execbuf);
+ put_offset(ahnd, surf->dst.handle);
+ put_offset(ahnd, surf->src.handle);
+ put_offset(ahnd, surf->bb.handle);
+ }
return 0;
}
@@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd,
uint32_t bbe = MI_BATCH_BUFFER_END;
uint32_t *bb;
- alignment = gem_detect_safe_alignment(fd);
+ alignment = get_default_alignment(fd, blt->driver);
data.dw00.client = 0x2;
data.dw00.opcode = 0x42;
@@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd,
data.dw01.dst_pitch = blt->dst.pitch;
data.dw01.color_depth = __fast_color_depth(blt->color_depth);
- data.dw01.dst_memory = __memory_type(blt->dst.region);
- data.dw01.src_memory = __memory_type(blt->src.region);
+ data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region);
+ data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region);
data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0;
data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0;
@@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd,
data.dw08.src_address_lo = src_offset;
data.dw09.src_address_hi = src_offset >> 32;
- bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size,
- PROT_READ | PROT_WRITE);
+ bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver);
igt_assert(bb_pos + sizeof(data) < blt->bb.size);
memcpy(bb + bb_pos, &data, sizeof(data));
@@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd,
uint64_t dst_offset, src_offset, bb_offset, alignment;
int ret;
- alignment = gem_detect_safe_alignment(fd);
+ igt_assert_f(ahnd, "fast-copy supports softpin only\n");
+ igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n");
+ igt_assert_neq(blt->driver, 0);
+ alignment = get_default_alignment(fd, blt->driver);
src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
emit_blt_fast_copy(fd, ahnd, blt, 0, true);
- obj[0].offset = CANONICAL(dst_offset);
- obj[1].offset = CANONICAL(src_offset);
- obj[2].offset = CANONICAL(bb_offset);
- obj[0].handle = blt->dst.handle;
- obj[1].handle = blt->src.handle;
- obj[2].handle = blt->bb.handle;
- obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
- EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- execbuf.buffer_count = 3;
- execbuf.buffers_ptr = to_user_pointer(obj);
- execbuf.rsvd1 = ctx ? ctx->id : 0;
- execbuf.flags = e ? e->flags : I915_EXEC_BLT;
- ret = __gem_execbuf(fd, &execbuf);
- put_offset(ahnd, blt->dst.handle);
- put_offset(ahnd, blt->src.handle);
- put_offset(ahnd, blt->bb.handle);
+ if (blt->driver == INTEL_DRIVER_XE) {
+ intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
+ } else {
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = blt->dst.handle;
+ obj[1].handle = blt->src.handle;
+ obj[2].handle = blt->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ ret = __gem_execbuf(fd, &execbuf);
+ put_offset(ahnd, blt->dst.handle);
+ put_offset(ahnd, blt->src.handle);
+ put_offset(ahnd, blt->bb.handle);
+ }
return ret;
}
@@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
obj = calloc(1, sizeof(*obj));
obj->size = size;
- igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
- &size, region) == 0);
+
+ if (blt->driver == INTEL_DRIVER_XE) {
+ size = ALIGN(size, xe_get_default_alignment(blt->fd));
+ handle = xe_bo_create_flags(blt->fd, 0, size, region);
+ } else {
+ igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
+ &size, region) == 0);
+ }
blt_set_object(obj, handle, size, region, mocs, tiling,
compression, compression_type);
blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
if (create_mapping)
- obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size,
- PROT_READ | PROT_WRITE);
+ obj->ptr = bo_map(blt->fd, handle, size, blt->driver);
return obj;
}
@@ -1529,14 +1587,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
int format;
int stride = obj->tiling ? obj->pitch * 4 : obj->pitch;
char filename[FILENAME_MAX];
+ bool is_xe = is_xe_device(fd);
snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png",
run_id, fileid, blt_tiling_name(obj->tiling), width, height,
obj->compression ? "compressed" : "uncompressed");
- if (!map)
- map = gem_mmap__device_coherent(fd, obj->handle, 0,
- obj->size, PROT_READ);
+ if (!map) {
+ if (is_xe)
+ map = xe_bo_map(fd, obj->handle, obj->size);
+ else
+ map = gem_mmap__device_coherent(fd, obj->handle, 0,
+ obj->size, PROT_READ);
+ }
format = CAIRO_FORMAT_RGB24;
surface = cairo_image_surface_create_for_data(map,
format, width, height,
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 307405e6e8..b8b3d724d5 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -8,7 +8,7 @@
/**
* SECTION:intel_blt
- * @short_description: i915 blitter library
+ * @short_description: i915/xe blitter library
* @title: Blitter library
* @include: intel_blt.h
*
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 17/21] lib/intel_blt: Extend blitter library to support xe driver
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 17/21] lib/intel_blt: Extend blitter library to support xe driver Zbigniew Kempczyński
@ 2023-07-13 7:24 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:24 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Use already written for i915 blitter library in xe development.
> Add appropriate code paths which are unique for those drivers.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> v3: Extract common helpers for getting mapping and alignment (Karolina)
> v4: Fix unwanted doc change (Karolina)
> ---
> lib/intel_blt.c | 233 ++++++++++++++++++++++++++++++------------------
> lib/intel_blt.h | 2 +-
> 2 files changed, 149 insertions(+), 86 deletions(-)
>
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 059cc53b9c..4657bb1aec 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -9,9 +9,13 @@
> #include <malloc.h>
> #include <cairo.h>
> #include "drm.h"
> -#include "igt.h"
> #include "i915/gem_create.h"
> +#include "igt.h"
> +#include "igt_syncobj.h"
> #include "intel_blt.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_util.h"
>
> #define BITRANGE(start, end) (end - start + 1)
> #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd))
> @@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt)
> return SM_NONE;
> }
>
> -static int __memory_type(uint32_t region)
> +static int __memory_type(int fd, enum intel_driver driver, uint32_t region)
> {
> - igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
> - IS_SYSTEM_MEMORY_REGION(region),
> - "Invalid region: %x\n", region);
> + if (driver == INTEL_DRIVER_I915) {
> + igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
> + IS_SYSTEM_MEMORY_REGION(region),
> + "Invalid region: %x\n", region);
> + } else {
> + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) ||
> + XE_IS_SYSMEM_MEMORY_REGION(fd, region),
> + "Invalid region: %x\n", region);
> + }
>
> - if (IS_DEVICE_MEMORY_REGION(region))
> + if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region))
> return TM_LOCAL_MEM;
> + else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region))
> + return TM_LOCAL_MEM;
> +
> return TM_SYSTEM_MEM;
> }
>
> -static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
> +static enum blt_aux_mode __aux_mode(int fd,
> + enum intel_driver driver,
> + const struct blt_copy_object *obj)
> {
> - if (obj->compression == COMPRESSION_ENABLED) {
> + if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) {
> igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region),
> "XY_BLOCK_COPY_BLT supports compression "
> "on device memory only\n");
> return AM_AUX_CCS_E;
> + } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) {
> + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region),
> + "XY_BLOCK_COPY_BLT supports compression "
> + "on device memory only\n");
> + return AM_AUX_CCS_E;
> }
>
> return AM_AUX_NONE;
> @@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data,
> data->dw00.length = extended_command ? 20 : 10;
>
> if (__special_mode(blt) == SM_FULL_RESOLVE)
> - data->dw01.dst_aux_mode = __aux_mode(&blt->src);
> + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src);
> else
> - data->dw01.dst_aux_mode = __aux_mode(&blt->dst);
> + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst);
> data->dw01.dst_pitch = blt->dst.pitch - 1;
>
> data->dw01.dst_mocs = blt->dst.mocs;
> @@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data,
>
> data->dw06.dst_x_offset = blt->dst.x_offset;
> data->dw06.dst_y_offset = blt->dst.y_offset;
> - data->dw06.dst_target_memory = __memory_type(blt->dst.region);
> + data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region);
>
> data->dw07.src_x1 = blt->src.x1;
> data->dw07.src_y1 = blt->src.y1;
>
> data->dw08.src_pitch = blt->src.pitch - 1;
> - data->dw08.src_aux_mode = __aux_mode(&blt->src);
> + data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src);
> data->dw08.src_mocs = blt->src.mocs;
> data->dw08.src_compression = blt->src.compression;
> data->dw08.src_tiling = __block_tiling(blt->src.tiling);
> @@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data,
>
> data->dw11.src_x_offset = blt->src.x_offset;
> data->dw11.src_y_offset = blt->src.y_offset;
> - data->dw11.src_target_memory = __memory_type(blt->src.region);
> + data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region);
> }
>
> static void fill_data_ext(struct gen12_block_copy_data_ext *dext,
> @@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
> data->dw21.src_array_index);
> }
>
> +static uint64_t get_default_alignment(int fd, enum intel_driver driver)
> +{
> + if (driver == INTEL_DRIVER_XE)
> + return xe_get_default_alignment(fd);
> +
> + return gem_detect_safe_alignment(fd);
> +}
> +
> +static void *bo_map(int fd, uint32_t handle, uint64_t size,
> + enum intel_driver driver)
> +{
> + if (driver == INTEL_DRIVER_XE)
> + return xe_bo_map(fd, handle, size);
> +
> + return gem_mmap__device_coherent(fd, handle, 0, size,
> + PROT_READ | PROT_WRITE);
> +}
> +
> /**
> * blt_copy_init:
> * @fd: drm fd
> @@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd,
> igt_assert_f(ahnd, "block-copy supports softpin only\n");
> igt_assert_f(blt, "block-copy requires data to do blit\n");
>
> - alignment = gem_detect_safe_alignment(fd);
> + alignment = get_default_alignment(fd, blt->driver);
> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment)
> + blt->src.plane_offset;
> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment)
> @@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd,
>
> fill_data(&data, blt, src_offset, dst_offset, ext);
>
> - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size,
> - PROT_READ | PROT_WRITE);
> + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver);
>
> igt_assert(bb_pos + sizeof(data) < blt->bb.size);
> memcpy(bb + bb_pos, &data, sizeof(data));
> @@ -812,29 +849,35 @@ int blt_block_copy(int fd,
>
> igt_assert_f(ahnd, "block-copy supports softpin only\n");
> igt_assert_f(blt, "block-copy requires data to do blit\n");
> + igt_assert_neq(blt->driver, 0);
>
> - alignment = gem_detect_safe_alignment(fd);
> + alignment = get_default_alignment(fd, blt->driver);
> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
>
> emit_blt_block_copy(fd, ahnd, blt, ext, 0, true);
>
> - obj[0].offset = CANONICAL(dst_offset);
> - obj[1].offset = CANONICAL(src_offset);
> - obj[2].offset = CANONICAL(bb_offset);
> - obj[0].handle = blt->dst.handle;
> - obj[1].handle = blt->src.handle;
> - obj[2].handle = blt->bb.handle;
> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - execbuf.buffer_count = 3;
> - execbuf.buffers_ptr = to_user_pointer(obj);
> - execbuf.rsvd1 = ctx ? ctx->id : 0;
> - execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> - ret = __gem_execbuf(fd, &execbuf);
> + if (blt->driver == INTEL_DRIVER_XE) {
> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> + } else {
> + obj[0].offset = CANONICAL(dst_offset);
> + obj[1].offset = CANONICAL(src_offset);
> + obj[2].offset = CANONICAL(bb_offset);
> + obj[0].handle = blt->dst.handle;
> + obj[1].handle = blt->src.handle;
> + obj[2].handle = blt->bb.handle;
> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + execbuf.buffer_count = 3;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.rsvd1 = ctx ? ctx->id : 0;
> + execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +
> + ret = __gem_execbuf(fd, &execbuf);
> + }
>
> return ret;
> }
> @@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
> igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
> igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
>
> - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16);
> + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16);
>
> data.dw00.client = 0x2;
> data.dw00.opcode = 0x48;
> @@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd,
> data.dw04.dst_address_hi = dst_offset >> 32;
> data.dw04.dst_mocs = surf->dst.mocs;
>
> - bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size,
> - PROT_READ | PROT_WRITE);
> + bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver);
>
> igt_assert(bb_pos + sizeof(data) < surf->bb.size);
> memcpy(bb + bb_pos, &data, sizeof(data));
> @@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd,
>
> igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
> igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
> + igt_assert_neq(surf->driver, 0);
>
> - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16);
> + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16);
> src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment);
> dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment);
> bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment);
>
> emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true);
>
> - obj[0].offset = CANONICAL(dst_offset);
> - obj[1].offset = CANONICAL(src_offset);
> - obj[2].offset = CANONICAL(bb_offset);
> - obj[0].handle = surf->dst.handle;
> - obj[1].handle = surf->src.handle;
> - obj[2].handle = surf->bb.handle;
> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - execbuf.buffer_count = 3;
> - execbuf.buffers_ptr = to_user_pointer(obj);
> - execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> - execbuf.rsvd1 = ctx ? ctx->id : 0;
> - gem_execbuf(fd, &execbuf);
> - put_offset(ahnd, surf->dst.handle);
> - put_offset(ahnd, surf->src.handle);
> - put_offset(ahnd, surf->bb.handle);
> + if (surf->driver == INTEL_DRIVER_XE) {
> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> + } else {
> + obj[0].offset = CANONICAL(dst_offset);
> + obj[1].offset = CANONICAL(src_offset);
> + obj[2].offset = CANONICAL(bb_offset);
> + obj[0].handle = surf->dst.handle;
> + obj[1].handle = surf->src.handle;
> + obj[2].handle = surf->bb.handle;
> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + execbuf.buffer_count = 3;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> + execbuf.rsvd1 = ctx ? ctx->id : 0;
> + gem_execbuf(fd, &execbuf);
> + put_offset(ahnd, surf->dst.handle);
> + put_offset(ahnd, surf->src.handle);
> + put_offset(ahnd, surf->bb.handle);
> + }
>
> return 0;
> }
> @@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd,
> uint32_t bbe = MI_BATCH_BUFFER_END;
> uint32_t *bb;
>
> - alignment = gem_detect_safe_alignment(fd);
> + alignment = get_default_alignment(fd, blt->driver);
>
> data.dw00.client = 0x2;
> data.dw00.opcode = 0x42;
> @@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd,
>
> data.dw01.dst_pitch = blt->dst.pitch;
> data.dw01.color_depth = __fast_color_depth(blt->color_depth);
> - data.dw01.dst_memory = __memory_type(blt->dst.region);
> - data.dw01.src_memory = __memory_type(blt->src.region);
> + data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region);
> + data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region);
> data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0;
> data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0;
>
> @@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd,
> data.dw08.src_address_lo = src_offset;
> data.dw09.src_address_hi = src_offset >> 32;
>
> - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size,
> - PROT_READ | PROT_WRITE);
> + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver);
>
> igt_assert(bb_pos + sizeof(data) < blt->bb.size);
> memcpy(bb + bb_pos, &data, sizeof(data));
> @@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd,
> uint64_t dst_offset, src_offset, bb_offset, alignment;
> int ret;
>
> - alignment = gem_detect_safe_alignment(fd);
> + igt_assert_f(ahnd, "fast-copy supports softpin only\n");
> + igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n");
> + igt_assert_neq(blt->driver, 0);
>
> + alignment = get_default_alignment(fd, blt->driver);
> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
>
> emit_blt_fast_copy(fd, ahnd, blt, 0, true);
>
> - obj[0].offset = CANONICAL(dst_offset);
> - obj[1].offset = CANONICAL(src_offset);
> - obj[2].offset = CANONICAL(bb_offset);
> - obj[0].handle = blt->dst.handle;
> - obj[1].handle = blt->src.handle;
> - obj[2].handle = blt->bb.handle;
> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - execbuf.buffer_count = 3;
> - execbuf.buffers_ptr = to_user_pointer(obj);
> - execbuf.rsvd1 = ctx ? ctx->id : 0;
> - execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> - ret = __gem_execbuf(fd, &execbuf);
> - put_offset(ahnd, blt->dst.handle);
> - put_offset(ahnd, blt->src.handle);
> - put_offset(ahnd, blt->bb.handle);
> + if (blt->driver == INTEL_DRIVER_XE) {
> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
> + } else {
> + obj[0].offset = CANONICAL(dst_offset);
> + obj[1].offset = CANONICAL(src_offset);
> + obj[2].offset = CANONICAL(bb_offset);
> + obj[0].handle = blt->dst.handle;
> + obj[1].handle = blt->src.handle;
> + obj[2].handle = blt->bb.handle;
> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + execbuf.buffer_count = 3;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.rsvd1 = ctx ? ctx->id : 0;
> + execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> + ret = __gem_execbuf(fd, &execbuf);
> + put_offset(ahnd, blt->dst.handle);
> + put_offset(ahnd, blt->src.handle);
> + put_offset(ahnd, blt->bb.handle);
> + }
>
> return ret;
> }
> @@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
> obj = calloc(1, sizeof(*obj));
>
> obj->size = size;
> - igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
> - &size, region) == 0);
> +
> + if (blt->driver == INTEL_DRIVER_XE) {
> + size = ALIGN(size, xe_get_default_alignment(blt->fd));
> + handle = xe_bo_create_flags(blt->fd, 0, size, region);
> + } else {
> + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
> + &size, region) == 0);
> + }
>
> blt_set_object(obj, handle, size, region, mocs, tiling,
> compression, compression_type);
> blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
>
> if (create_mapping)
> - obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size,
> - PROT_READ | PROT_WRITE);
> + obj->ptr = bo_map(blt->fd, handle, size, blt->driver);
>
> return obj;
> }
> @@ -1529,14 +1587,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid,
> int format;
> int stride = obj->tiling ? obj->pitch * 4 : obj->pitch;
> char filename[FILENAME_MAX];
> + bool is_xe = is_xe_device(fd);
>
> snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png",
> run_id, fileid, blt_tiling_name(obj->tiling), width, height,
> obj->compression ? "compressed" : "uncompressed");
>
> - if (!map)
> - map = gem_mmap__device_coherent(fd, obj->handle, 0,
> - obj->size, PROT_READ);
> + if (!map) {
> + if (is_xe)
> + map = xe_bo_map(fd, obj->handle, obj->size);
> + else
> + map = gem_mmap__device_coherent(fd, obj->handle, 0,
> + obj->size, PROT_READ);
> + }
> format = CAIRO_FORMAT_RGB24;
> surface = cairo_image_surface_create_for_data(map,
> format, width, height,
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 307405e6e8..b8b3d724d5 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -8,7 +8,7 @@
>
> /**
> * SECTION:intel_blt
> - * @short_description: i915 blitter library
> + * @short_description: i915/xe blitter library
> * @title: Blitter library
> * @include: intel_blt.h
> *
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 18/21] tests/xe_ccs: Check if flatccs is working with block-copy for Xe
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (16 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 17/21] lib/intel_blt: Extend blitter library to support xe driver Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:40 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy " Zbigniew Kempczyński
` (7 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
This is ported to xe copy of i915 gem_ccs test. Ported means all driver
dependent calls - like working on regions, binding and execution were
replaced by xe counterparts. I wondered to add conditionals for xe
in gem_ccs but this would decrease test readability so I dropped
this idea.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
v3: Drop unused macro, use system_memory() instead REGION_SMEM
in xe test (Karolina)
v4: Use globalized functions (Karolina)
---
tests/meson.build | 1 +
tests/xe/xe_ccs.c | 698 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 699 insertions(+)
create mode 100644 tests/xe/xe_ccs.c
diff --git a/tests/meson.build b/tests/meson.build
index d56e4c89da..da8653fabc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -263,6 +263,7 @@ i915_progs = [
]
xe_progs = [
+ 'xe_ccs',
'xe_create',
'xe_compute',
'xe_dma_buf_sync',
diff --git a/tests/xe/xe_ccs.c b/tests/xe/xe_ccs.c
new file mode 100644
index 0000000000..2d5ae33fa0
--- /dev/null
+++ b/tests/xe/xe_ccs.c
@@ -0,0 +1,698 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <errno.h>
+#include <glib.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "igt_syncobj.h"
+#include "intel_blt.h"
+#include "intel_mocs.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
+/**
+ * TEST: xe ccs
+ * Description: Exercise gen12 blitter with and without flatccs compression on Xe
+ * Run type: FULL
+ *
+ * SUBTEST: block-copy-compressed
+ * Description: Check block-copy flatccs compressed blit
+ *
+ * SUBTEST: block-copy-uncompressed
+ * Description: Check block-copy uncompressed blit
+ *
+ * SUBTEST: block-multicopy-compressed
+ * Description: Check block-multicopy flatccs compressed blit
+ *
+ * SUBTEST: block-multicopy-inplace
+ * Description: Check block-multicopy flatccs inplace decompression blit
+ *
+ * SUBTEST: ctrl-surf-copy
+ * Description: Check flatccs data can be copied from/to surface
+ *
+ * SUBTEST: ctrl-surf-copy-new-ctx
+ * Description: Check flatccs data are physically tagged and visible in vm
+ *
+ * SUBTEST: suspend-resume
+ * Description: Check flatccs data persists after suspend / resume (S0)
+ */
+
+IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression on Xe");
+
+static struct param {
+ int compression_format;
+ int tiling;
+ bool write_png;
+ bool print_bb;
+ bool print_surface_info;
+ int width;
+ int height;
+} param = {
+ .compression_format = 0,
+ .tiling = -1,
+ .write_png = false,
+ .print_bb = false,
+ .print_surface_info = false,
+ .width = 512,
+ .height = 512,
+};
+
+struct test_config {
+ bool compression;
+ bool inplace;
+ bool surfcopy;
+ bool new_ctx;
+ bool suspend_resume;
+};
+
+#define PRINT_SURFACE_INFO(name, obj) do { \
+ if (param.print_surface_info) \
+ blt_surface_info((name), (obj)); } while (0)
+
+#define WRITE_PNG(fd, id, name, obj, w, h) do { \
+ if (param.write_png) \
+ blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
+
+static void surf_copy(int xe,
+ intel_ctx_t *ctx,
+ uint64_t ahnd,
+ const struct blt_copy_object *src,
+ const struct blt_copy_object *mid,
+ const struct blt_copy_object *dst,
+ int run_id, bool suspend_resume)
+{
+ struct blt_copy_data blt = {};
+ struct blt_block_copy_data_ext ext = {};
+ struct blt_ctrl_surf_copy_data surf = {};
+ uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
+ uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
+ uint32_t *ccscopy;
+ uint8_t uc_mocs = intel_get_uc_mocs(xe);
+ uint32_t sysmem = system_memory(xe);
+ int result;
+
+ igt_assert(mid->compression);
+ ccscopy = (uint32_t *) malloc(ccssize);
+ ccs = xe_bo_create_flags(xe, 0, ccssize, sysmem);
+ ccs2 = xe_bo_create_flags(xe, 0, ccssize, sysmem);
+
+ blt_ctrl_surf_copy_init(xe, &surf);
+ surf.print_bb = param.print_bb;
+ blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
+ uc_mocs, BLT_INDIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS);
+ bb_size = xe_get_default_alignment(xe);
+ bb1 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
+ blt_set_batch(&surf.bb, bb1, bb_size, sysmem);
+ blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
+ intel_ctx_xe_sync(ctx, true);
+
+ ccsmap = xe_bo_map(xe, ccs, surf.dst.size);
+ memcpy(ccscopy, ccsmap, ccssize);
+
+ if (suspend_resume) {
+ char *orig, *orig2, *newsum, *newsum2;
+
+ orig = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
+ (void *)ccsmap, surf.dst.size);
+ orig2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
+ (void *)mid->ptr, mid->size);
+
+ igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE);
+
+ blt_set_ctrl_surf_object(&surf.dst, ccs2, system_memory(xe), ccssize,
+ 0, DIRECT_ACCESS);
+ blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
+ intel_ctx_xe_sync(ctx, true);
+
+ ccsmap2 = xe_bo_map(xe, ccs2, surf.dst.size);
+ newsum = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
+ (void *)ccsmap2, surf.dst.size);
+ newsum2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
+ (void *)mid->ptr, mid->size);
+
+ munmap(ccsmap2, ccssize);
+ igt_assert(!strcmp(orig, newsum));
+ igt_assert(!strcmp(orig2, newsum2));
+ g_free(orig);
+ g_free(orig2);
+ g_free(newsum);
+ g_free(newsum2);
+ }
+
+ /* corrupt ccs */
+ for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
+ ccsmap[i] = i;
+ blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
+ uc_mocs, DIRECT_ACCESS);
+ blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
+ uc_mocs, INDIRECT_ACCESS);
+ blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
+ intel_ctx_xe_sync(ctx, true);
+
+ blt_copy_init(xe, &blt);
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
+ bb2 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
+ blt_set_batch(&blt.bb, bb2, bb_size, sysmem);
+ blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
+ intel_ctx_xe_sync(ctx, true);
+ WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
+ result = memcmp(src->ptr, dst->ptr, src->size);
+ igt_assert(result != 0);
+
+ /* retrieve back ccs */
+ memcpy(ccsmap, ccscopy, ccssize);
+ blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
+
+ blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
+ intel_ctx_xe_sync(ctx, true);
+ WRITE_PNG(xe, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
+ result = memcmp(src->ptr, dst->ptr, src->size);
+ if (result)
+ blt_dump_corruption_info_32b(src, dst);
+
+ munmap(ccsmap, ccssize);
+ gem_close(xe, ccs);
+ gem_close(xe, ccs2);
+ gem_close(xe, bb1);
+ gem_close(xe, bb2);
+
+ igt_assert_f(result == 0,
+ "Source and destination surfaces are different after "
+ "restoring source ccs data\n");
+}
+
+struct blt_copy3_data {
+ int xe;
+ struct blt_copy_object src;
+ struct blt_copy_object mid;
+ struct blt_copy_object dst;
+ struct blt_copy_object final;
+ struct blt_copy_batch bb;
+ enum blt_color_depth color_depth;
+
+ /* debug stuff */
+ bool print_bb;
+};
+
+struct blt_block_copy3_data_ext {
+ struct blt_block_copy_object_ext src;
+ struct blt_block_copy_object_ext mid;
+ struct blt_block_copy_object_ext dst;
+ struct blt_block_copy_object_ext final;
+};
+
+static int blt_block_copy3(int xe,
+ const intel_ctx_t *ctx,
+ uint64_t ahnd,
+ const struct blt_copy3_data *blt3,
+ const struct blt_block_copy3_data_ext *ext3)
+{
+ struct blt_copy_data blt0;
+ struct blt_block_copy_data_ext ext0;
+ uint64_t bb_offset, alignment;
+ uint64_t bb_pos = 0;
+ int ret;
+
+ igt_assert_f(ahnd, "block-copy3 supports softpin only\n");
+ igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
+
+ alignment = xe_get_default_alignment(xe);
+ get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
+ get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
+ get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
+ get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
+ bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
+
+ /* First blit src -> mid */
+ blt_copy_init(xe, &blt0);
+ blt0.src = blt3->src;
+ blt0.dst = blt3->mid;
+ blt0.bb = blt3->bb;
+ blt0.color_depth = blt3->color_depth;
+ blt0.print_bb = blt3->print_bb;
+ ext0.src = ext3->src;
+ ext0.dst = ext3->mid;
+ bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false);
+
+ /* Second blit mid -> dst */
+ blt_copy_init(xe, &blt0);
+ blt0.src = blt3->mid;
+ blt0.dst = blt3->dst;
+ blt0.bb = blt3->bb;
+ blt0.color_depth = blt3->color_depth;
+ blt0.print_bb = blt3->print_bb;
+ ext0.src = ext3->mid;
+ ext0.dst = ext3->dst;
+ bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false);
+
+ /* Third blit dst -> final */
+ blt_copy_init(xe, &blt0);
+ blt0.src = blt3->dst;
+ blt0.dst = blt3->final;
+ blt0.bb = blt3->bb;
+ blt0.color_depth = blt3->color_depth;
+ blt0.print_bb = blt3->print_bb;
+ ext0.src = ext3->dst;
+ ext0.dst = ext3->final;
+ bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, true);
+
+ intel_ctx_xe_exec(ctx, ahnd, bb_offset);
+
+ return ret;
+}
+
+static void block_copy(int xe,
+ intel_ctx_t *ctx,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling,
+ const struct test_config *config)
+{
+ struct blt_copy_data blt = {};
+ struct blt_block_copy_data_ext ext = {}, *pext = &ext;
+ struct blt_copy_object *src, *mid, *dst;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = xe_get_default_alignment(xe);
+ uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
+ uint32_t run_id = mid_tiling;
+ uint32_t mid_region = region2, bb;
+ uint32_t width = param.width, height = param.height;
+ enum blt_compression mid_compression = config->compression;
+ int mid_compression_format = param.compression_format;
+ enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
+ uint8_t uc_mocs = intel_get_uc_mocs(xe);
+ int result;
+
+ bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+
+ if (!blt_uses_extended_block_copy(xe))
+ pext = NULL;
+
+ blt_copy_init(xe, &blt);
+
+ src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
+ mid_tiling, mid_compression, comp_type, true);
+ dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ igt_assert(src->size == dst->size);
+ PRINT_SURFACE_INFO("src", src);
+ PRINT_SURFACE_INFO("mid", mid);
+ PRINT_SURFACE_INFO("dst", dst);
+
+ blt_surface_fill_rect(xe, src, width, height);
+ WRITE_PNG(xe, run_id, "src", src, width, height);
+
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.dst, mid);
+ blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+ blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext);
+ intel_ctx_xe_sync(ctx, true);
+
+ /* We expect mid != src if there's compression */
+ if (mid->compression)
+ igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0);
+
+ WRITE_PNG(xe, run_id, "mid", &blt.dst, width, height);
+
+ if (config->surfcopy && pext) {
+ struct drm_xe_engine_class_instance inst = {
+ .engine_class = DRM_XE_ENGINE_CLASS_COPY,
+ };
+ intel_ctx_t *surf_ctx = ctx;
+ uint64_t surf_ahnd = ahnd;
+ uint32_t vm, engine;
+
+ if (config->new_ctx) {
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ engine = xe_engine_create(xe, vm, &inst, 0);
+ surf_ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0);
+ surf_ahnd = intel_allocator_open(xe, surf_ctx->vm,
+ INTEL_ALLOCATOR_RELOC);
+ }
+ surf_copy(xe, surf_ctx, surf_ahnd, src, mid, dst, run_id,
+ config->suspend_resume);
+
+ if (surf_ctx != ctx) {
+ xe_engine_destroy(xe, engine);
+ xe_vm_destroy(xe, vm);
+ free(surf_ctx);
+ put_ahnd(surf_ahnd);
+ }
+ }
+
+ blt_copy_init(xe, &blt);
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
+ if (config->inplace) {
+ blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type);
+ blt.dst.ptr = mid->ptr;
+ }
+
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+ blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext);
+ intel_ctx_xe_sync(ctx, true);
+
+ WRITE_PNG(xe, run_id, "dst", &blt.dst, width, height);
+
+ result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+ /* Politely clean vm */
+ put_offset(ahnd, src->handle);
+ put_offset(ahnd, mid->handle);
+ put_offset(ahnd, dst->handle);
+ put_offset(ahnd, bb);
+ intel_allocator_bind(ahnd, 0, 0);
+ blt_destroy_object(xe, src);
+ blt_destroy_object(xe, mid);
+ blt_destroy_object(xe, dst);
+ gem_close(xe, bb);
+ put_ahnd(ahnd);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+static void block_multicopy(int xe,
+ intel_ctx_t *ctx,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling,
+ const struct test_config *config)
+{
+ struct blt_copy3_data blt3 = {};
+ struct blt_copy_data blt = {};
+ struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3;
+ struct blt_copy_object *src, *mid, *dst, *final;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = xe_get_default_alignment(xe);
+ uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
+ uint32_t run_id = mid_tiling;
+ uint32_t mid_region = region2, bb;
+ uint32_t width = param.width, height = param.height;
+ enum blt_compression mid_compression = config->compression;
+ int mid_compression_format = param.compression_format;
+ enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
+ uint8_t uc_mocs = intel_get_uc_mocs(xe);
+ int result;
+
+ bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+
+ if (!blt_uses_extended_block_copy(xe))
+ pext3 = NULL;
+
+ blt_copy_init(xe, &blt);
+
+ src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
+ mid_tiling, mid_compression, comp_type, true);
+ dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
+ mid_tiling, COMPRESSION_DISABLED, comp_type, true);
+ final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ igt_assert(src->size == dst->size);
+ PRINT_SURFACE_INFO("src", src);
+ PRINT_SURFACE_INFO("mid", mid);
+ PRINT_SURFACE_INFO("dst", dst);
+ PRINT_SURFACE_INFO("final", final);
+
+ blt_surface_fill_rect(xe, src, width, height);
+
+ blt3.color_depth = CD_32bit;
+ blt3.print_bb = param.print_bb;
+ blt_set_copy_object(&blt3.src, src);
+ blt_set_copy_object(&blt3.mid, mid);
+ blt_set_copy_object(&blt3.dst, dst);
+ blt_set_copy_object(&blt3.final, final);
+
+ if (config->inplace) {
+ blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region,
+ mid->mocs, mid_tiling, COMPRESSION_DISABLED,
+ comp_type);
+ blt3.dst.ptr = mid->ptr;
+ }
+
+ blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_batch(&blt3.bb, bb, bb_size, region1);
+
+ blt_block_copy3(xe, ctx, ahnd, &blt3, pext3);
+ intel_ctx_xe_sync(ctx, true);
+
+ WRITE_PNG(xe, run_id, "src", &blt3.src, width, height);
+ if (!config->inplace)
+ WRITE_PNG(xe, run_id, "mid", &blt3.mid, width, height);
+ WRITE_PNG(xe, run_id, "dst", &blt3.dst, width, height);
+ WRITE_PNG(xe, run_id, "final", &blt3.final, width, height);
+
+ result = memcmp(src->ptr, blt3.final.ptr, src->size);
+
+ put_offset(ahnd, src->handle);
+ put_offset(ahnd, mid->handle);
+ put_offset(ahnd, dst->handle);
+ put_offset(ahnd, final->handle);
+ put_offset(ahnd, bb);
+ intel_allocator_bind(ahnd, 0, 0);
+ blt_destroy_object(xe, src);
+ blt_destroy_object(xe, mid);
+ blt_destroy_object(xe, dst);
+ blt_destroy_object(xe, final);
+ gem_close(xe, bb);
+ put_ahnd(ahnd);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+enum copy_func {
+ BLOCK_COPY,
+ BLOCK_MULTICOPY,
+};
+
+static const struct {
+ const char *suffix;
+ void (*copyfn)(int fd,
+ intel_ctx_t *ctx,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type btype,
+ const struct test_config *config);
+} copyfns[] = {
+ [BLOCK_COPY] = { "", block_copy },
+ [BLOCK_MULTICOPY] = { "-multicopy", block_multicopy },
+};
+
+static void block_copy_test(int xe,
+ const struct test_config *config,
+ struct igt_collection *set,
+ enum copy_func copy_function)
+{
+ struct drm_xe_engine_class_instance inst = {
+ .engine_class = DRM_XE_ENGINE_CLASS_COPY,
+ };
+ intel_ctx_t *ctx;
+ struct igt_collection *regions;
+ uint32_t vm, engine;
+ int tiling;
+
+ if (config->compression && !blt_block_copy_supports_compression(xe))
+ return;
+
+ if (config->inplace && !config->compression)
+ return;
+
+ for_each_tiling(tiling) {
+ if (!blt_block_copy_supports_tiling(xe, tiling) ||
+ (param.tiling >= 0 && param.tiling != tiling))
+ continue;
+
+ for_each_variation_r(regions, 2, set) {
+ uint32_t region1, region2;
+ char *regtxt;
+
+ region1 = igt_collection_get_value(regions, 0);
+ region2 = igt_collection_get_value(regions, 1);
+
+ /* Compressed surface must be in device memory */
+ if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
+ continue;
+
+ regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
+
+ igt_dynamic_f("%s-%s-compfmt%d-%s%s",
+ blt_tiling_name(tiling),
+ config->compression ?
+ "compressed" : "uncompressed",
+ param.compression_format, regtxt,
+ copyfns[copy_function].suffix) {
+ uint32_t sync_bind, sync_out;
+
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ engine = xe_engine_create(xe, vm, &inst, 0);
+ sync_bind = syncobj_create(xe, 0);
+ sync_out = syncobj_create(xe, 0);
+ ctx = intel_ctx_xe(xe, vm, engine,
+ 0, sync_bind, sync_out);
+
+ copyfns[copy_function].copyfn(xe, ctx,
+ region1, region2,
+ tiling, config);
+
+ xe_engine_destroy(xe, engine);
+ xe_vm_destroy(xe, vm);
+ syncobj_destroy(xe, sync_bind);
+ syncobj_destroy(xe, sync_out);
+ free(ctx);
+ }
+
+ free(regtxt);
+ }
+ }
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'b':
+ param.print_bb = true;
+ igt_debug("Print bb: %d\n", param.print_bb);
+ break;
+ case 'f':
+ param.compression_format = atoi(optarg);
+ igt_debug("Compression format: %d\n", param.compression_format);
+ igt_assert((param.compression_format & ~0x1f) == 0);
+ break;
+ case 'p':
+ param.write_png = true;
+ igt_debug("Write png: %d\n", param.write_png);
+ break;
+ case 's':
+ param.print_surface_info = true;
+ igt_debug("Print surface info: %d\n", param.print_surface_info);
+ break;
+ case 't':
+ param.tiling = atoi(optarg);
+ igt_debug("Tiling: %d\n", param.tiling);
+ break;
+ case 'W':
+ param.width = atoi(optarg);
+ igt_debug("Width: %d\n", param.width);
+ break;
+ case 'H':
+ param.height = atoi(optarg);
+ igt_debug("Height: %d\n", param.height);
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -b\tPrint bb\n"
+ " -f\tCompression format (0-31)\n"
+ " -p\tWrite PNG\n"
+ " -s\tPrint surface info\n"
+ " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
+ " -W\tWidth (default 512)\n"
+ " -H\tHeight (default 512)"
+ ;
+
+igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
+{
+ struct igt_collection *set;
+ int xe;
+
+ igt_fixture {
+ xe = drm_open_driver(DRIVER_XE);
+ igt_require(blt_has_block_copy(xe));
+
+ xe_device_get(xe);
+
+ set = xe_get_memory_region_set(xe,
+ XE_MEM_REGION_CLASS_SYSMEM,
+ XE_MEM_REGION_CLASS_VRAM);
+ }
+
+ igt_describe("Check block-copy uncompressed blit");
+ igt_subtest_with_dynamic("block-copy-uncompressed") {
+ struct test_config config = {};
+
+ block_copy_test(xe, &config, set, BLOCK_COPY);
+ }
+
+ igt_describe("Check block-copy flatccs compressed blit");
+ igt_subtest_with_dynamic("block-copy-compressed") {
+ struct test_config config = { .compression = true };
+
+ block_copy_test(xe, &config, set, BLOCK_COPY);
+ }
+
+ igt_describe("Check block-multicopy flatccs compressed blit");
+ igt_subtest_with_dynamic("block-multicopy-compressed") {
+ struct test_config config = { .compression = true };
+
+ block_copy_test(xe, &config, set, BLOCK_MULTICOPY);
+ }
+
+ igt_describe("Check block-multicopy flatccs inplace decompression blit");
+ igt_subtest_with_dynamic("block-multicopy-inplace") {
+ struct test_config config = { .compression = true,
+ .inplace = true };
+
+ block_copy_test(xe, &config, set, BLOCK_MULTICOPY);
+ }
+
+ igt_describe("Check flatccs data can be copied from/to surface");
+ igt_subtest_with_dynamic("ctrl-surf-copy") {
+ struct test_config config = { .compression = true,
+ .surfcopy = true };
+
+ block_copy_test(xe, &config, set, BLOCK_COPY);
+ }
+
+ igt_describe("Check flatccs data are physically tagged and visible"
+ " in different contexts");
+ igt_subtest_with_dynamic("ctrl-surf-copy-new-ctx") {
+ struct test_config config = { .compression = true,
+ .surfcopy = true,
+ .new_ctx = true };
+
+ block_copy_test(xe, &config, set, BLOCK_COPY);
+ }
+
+ igt_describe("Check flatccs data persists after suspend / resume (S0)");
+ igt_subtest_with_dynamic("suspend-resume") {
+ struct test_config config = { .compression = true,
+ .surfcopy = true,
+ .suspend_resume = true };
+
+ block_copy_test(xe, &config, set, BLOCK_COPY);
+ }
+
+ igt_fixture {
+ xe_device_put(xe);
+ close(xe);
+ }
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 18/21] tests/xe_ccs: Check if flatccs is working with block-copy for Xe
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 18/21] tests/xe_ccs: Check if flatccs is working with block-copy for Xe Zbigniew Kempczyński
@ 2023-07-13 7:40 ` Karolina Stolarek
0 siblings, 0 replies; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:40 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> This is ported to xe copy of i915 gem_ccs test. Ported means all driver
> dependent calls - like working on regions, binding and execution were
> replaced by xe counterparts. I wondered to add conditionals for xe
> in gem_ccs but this would decrease test readability so I dropped
> this idea.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> v3: Drop unused macro, use system_memory() instead REGION_SMEM
> in xe test (Karolina)
> v4: Use globalized functions (Karolina)
> ---
> tests/meson.build | 1 +
> tests/xe/xe_ccs.c | 698 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 699 insertions(+)
> create mode 100644 tests/xe/xe_ccs.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index d56e4c89da..da8653fabc 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -263,6 +263,7 @@ i915_progs = [
> ]
>
> xe_progs = [
> + 'xe_ccs',
> 'xe_create',
> 'xe_compute',
> 'xe_dma_buf_sync',
> diff --git a/tests/xe/xe_ccs.c b/tests/xe/xe_ccs.c
> new file mode 100644
> index 0000000000..2d5ae33fa0
> --- /dev/null
> +++ b/tests/xe/xe_ccs.c
> @@ -0,0 +1,698 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <glib.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "igt_syncobj.h"
> +#include "intel_blt.h"
> +#include "intel_mocs.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_util.h"
> +/**
> + * TEST: xe ccs
> + * Description: Exercise gen12 blitter with and without flatccs compression on Xe
> + * Run type: FULL
> + *
> + * SUBTEST: block-copy-compressed
> + * Description: Check block-copy flatccs compressed blit
> + *
> + * SUBTEST: block-copy-uncompressed
> + * Description: Check block-copy uncompressed blit
> + *
> + * SUBTEST: block-multicopy-compressed
> + * Description: Check block-multicopy flatccs compressed blit
> + *
> + * SUBTEST: block-multicopy-inplace
> + * Description: Check block-multicopy flatccs inplace decompression blit
> + *
> + * SUBTEST: ctrl-surf-copy
> + * Description: Check flatccs data can be copied from/to surface
> + *
> + * SUBTEST: ctrl-surf-copy-new-ctx
> + * Description: Check flatccs data are physically tagged and visible in vm
> + *
> + * SUBTEST: suspend-resume
> + * Description: Check flatccs data persists after suspend / resume (S0)
> + */
> +
> +IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression on Xe");
> +
> +static struct param {
> + int compression_format;
> + int tiling;
> + bool write_png;
> + bool print_bb;
> + bool print_surface_info;
> + int width;
> + int height;
> +} param = {
> + .compression_format = 0,
> + .tiling = -1,
> + .write_png = false,
> + .print_bb = false,
> + .print_surface_info = false,
> + .width = 512,
> + .height = 512,
> +};
> +
> +struct test_config {
> + bool compression;
> + bool inplace;
> + bool surfcopy;
> + bool new_ctx;
> + bool suspend_resume;
> +};
> +
> +#define PRINT_SURFACE_INFO(name, obj) do { \
> + if (param.print_surface_info) \
> + blt_surface_info((name), (obj)); } while (0)
> +
> +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
> + if (param.write_png) \
> + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
> +
> +static void surf_copy(int xe,
> + intel_ctx_t *ctx,
> + uint64_t ahnd,
> + const struct blt_copy_object *src,
> + const struct blt_copy_object *mid,
> + const struct blt_copy_object *dst,
> + int run_id, bool suspend_resume)
> +{
> + struct blt_copy_data blt = {};
> + struct blt_block_copy_data_ext ext = {};
> + struct blt_ctrl_surf_copy_data surf = {};
> + uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2;
> + uint64_t bb_size, ccssize = mid->size / CCS_RATIO;
> + uint32_t *ccscopy;
> + uint8_t uc_mocs = intel_get_uc_mocs(xe);
> + uint32_t sysmem = system_memory(xe);
> + int result;
> +
> + igt_assert(mid->compression);
> + ccscopy = (uint32_t *) malloc(ccssize);
> + ccs = xe_bo_create_flags(xe, 0, ccssize, sysmem);
> + ccs2 = xe_bo_create_flags(xe, 0, ccssize, sysmem);
> +
> + blt_ctrl_surf_copy_init(xe, &surf);
> + surf.print_bb = param.print_bb;
> + blt_set_ctrl_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> + uc_mocs, BLT_INDIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS);
> + bb_size = xe_get_default_alignment(xe);
> + bb1 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
> + blt_set_batch(&surf.bb, bb1, bb_size, sysmem);
> + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
> + intel_ctx_xe_sync(ctx, true);
> +
> + ccsmap = xe_bo_map(xe, ccs, surf.dst.size);
> + memcpy(ccscopy, ccsmap, ccssize);
> +
> + if (suspend_resume) {
> + char *orig, *orig2, *newsum, *newsum2;
> +
> + orig = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
> + (void *)ccsmap, surf.dst.size);
> + orig2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
> + (void *)mid->ptr, mid->size);
> +
> + igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE);
> +
> + blt_set_ctrl_surf_object(&surf.dst, ccs2, system_memory(xe), ccssize,
> + 0, DIRECT_ACCESS);
> + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
> + intel_ctx_xe_sync(ctx, true);
> +
> + ccsmap2 = xe_bo_map(xe, ccs2, surf.dst.size);
> + newsum = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
> + (void *)ccsmap2, surf.dst.size);
> + newsum2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
> + (void *)mid->ptr, mid->size);
> +
> + munmap(ccsmap2, ccssize);
> + igt_assert(!strcmp(orig, newsum));
> + igt_assert(!strcmp(orig2, newsum2));
> + g_free(orig);
> + g_free(orig2);
> + g_free(newsum);
> + g_free(newsum2);
> + }
> +
> + /* corrupt ccs */
> + for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
> + ccsmap[i] = i;
> + blt_set_ctrl_surf_object(&surf.src, ccs, sysmem, ccssize,
> + uc_mocs, DIRECT_ACCESS);
> + blt_set_ctrl_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> + uc_mocs, INDIRECT_ACCESS);
> + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
> + intel_ctx_xe_sync(ctx, true);
> +
> + blt_copy_init(xe, &blt);
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
> + bb2 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
> + blt_set_batch(&blt.bb, bb2, bb_size, sysmem);
> + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
> + intel_ctx_xe_sync(ctx, true);
> + WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
> + result = memcmp(src->ptr, dst->ptr, src->size);
> + igt_assert(result != 0);
> +
> + /* retrieve back ccs */
> + memcpy(ccsmap, ccscopy, ccssize);
> + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
> +
> + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
> + intel_ctx_xe_sync(ctx, true);
> + WRITE_PNG(xe, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
> + result = memcmp(src->ptr, dst->ptr, src->size);
> + if (result)
> + blt_dump_corruption_info_32b(src, dst);
> +
> + munmap(ccsmap, ccssize);
> + gem_close(xe, ccs);
> + gem_close(xe, ccs2);
> + gem_close(xe, bb1);
> + gem_close(xe, bb2);
> +
> + igt_assert_f(result == 0,
> + "Source and destination surfaces are different after "
> + "restoring source ccs data\n");
> +}
> +
> +struct blt_copy3_data {
> + int xe;
> + struct blt_copy_object src;
> + struct blt_copy_object mid;
> + struct blt_copy_object dst;
> + struct blt_copy_object final;
> + struct blt_copy_batch bb;
> + enum blt_color_depth color_depth;
> +
> + /* debug stuff */
> + bool print_bb;
> +};
> +
> +struct blt_block_copy3_data_ext {
> + struct blt_block_copy_object_ext src;
> + struct blt_block_copy_object_ext mid;
> + struct blt_block_copy_object_ext dst;
> + struct blt_block_copy_object_ext final;
> +};
> +
> +static int blt_block_copy3(int xe,
> + const intel_ctx_t *ctx,
> + uint64_t ahnd,
> + const struct blt_copy3_data *blt3,
> + const struct blt_block_copy3_data_ext *ext3)
> +{
> + struct blt_copy_data blt0;
> + struct blt_block_copy_data_ext ext0;
> + uint64_t bb_offset, alignment;
> + uint64_t bb_pos = 0;
> + int ret;
> +
> + igt_assert_f(ahnd, "block-copy3 supports softpin only\n");
> + igt_assert_f(blt3, "block-copy3 requires data to do blit\n");
> +
> + alignment = xe_get_default_alignment(xe);
> + get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment);
> + get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment);
> + get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment);
> + get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment);
> + bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment);
> +
> + /* First blit src -> mid */
> + blt_copy_init(xe, &blt0);
> + blt0.src = blt3->src;
> + blt0.dst = blt3->mid;
> + blt0.bb = blt3->bb;
> + blt0.color_depth = blt3->color_depth;
> + blt0.print_bb = blt3->print_bb;
> + ext0.src = ext3->src;
> + ext0.dst = ext3->mid;
> + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false);
> +
> + /* Second blit mid -> dst */
> + blt_copy_init(xe, &blt0);
> + blt0.src = blt3->mid;
> + blt0.dst = blt3->dst;
> + blt0.bb = blt3->bb;
> + blt0.color_depth = blt3->color_depth;
> + blt0.print_bb = blt3->print_bb;
> + ext0.src = ext3->mid;
> + ext0.dst = ext3->dst;
> + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false);
> +
> + /* Third blit dst -> final */
> + blt_copy_init(xe, &blt0);
> + blt0.src = blt3->dst;
> + blt0.dst = blt3->final;
> + blt0.bb = blt3->bb;
> + blt0.color_depth = blt3->color_depth;
> + blt0.print_bb = blt3->print_bb;
> + ext0.src = ext3->dst;
> + ext0.dst = ext3->final;
> + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, true);
> +
> + intel_ctx_xe_exec(ctx, ahnd, bb_offset);
> +
> + return ret;
> +}
> +
> +static void block_copy(int xe,
> + intel_ctx_t *ctx,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling,
> + const struct test_config *config)
> +{
> + struct blt_copy_data blt = {};
> + struct blt_block_copy_data_ext ext = {}, *pext = &ext;
> + struct blt_copy_object *src, *mid, *dst;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = xe_get_default_alignment(xe);
> + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
> + uint32_t run_id = mid_tiling;
> + uint32_t mid_region = region2, bb;
> + uint32_t width = param.width, height = param.height;
> + enum blt_compression mid_compression = config->compression;
> + int mid_compression_format = param.compression_format;
> + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> + uint8_t uc_mocs = intel_get_uc_mocs(xe);
> + int result;
> +
> + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> +
> + if (!blt_uses_extended_block_copy(xe))
> + pext = NULL;
> +
> + blt_copy_init(xe, &blt);
> +
> + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
> + mid_tiling, mid_compression, comp_type, true);
> + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + igt_assert(src->size == dst->size);
> + PRINT_SURFACE_INFO("src", src);
> + PRINT_SURFACE_INFO("mid", mid);
> + PRINT_SURFACE_INFO("dst", dst);
> +
> + blt_surface_fill_rect(xe, src, width, height);
> + WRITE_PNG(xe, run_id, "src", src, width, height);
> +
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.dst, mid);
> + blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext);
> + intel_ctx_xe_sync(ctx, true);
> +
> + /* We expect mid != src if there's compression */
> + if (mid->compression)
> + igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0);
> +
> + WRITE_PNG(xe, run_id, "mid", &blt.dst, width, height);
> +
> + if (config->surfcopy && pext) {
> + struct drm_xe_engine_class_instance inst = {
> + .engine_class = DRM_XE_ENGINE_CLASS_COPY,
> + };
> + intel_ctx_t *surf_ctx = ctx;
> + uint64_t surf_ahnd = ahnd;
> + uint32_t vm, engine;
> +
> + if (config->new_ctx) {
> + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> + engine = xe_engine_create(xe, vm, &inst, 0);
> + surf_ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0);
> + surf_ahnd = intel_allocator_open(xe, surf_ctx->vm,
> + INTEL_ALLOCATOR_RELOC);
> + }
> + surf_copy(xe, surf_ctx, surf_ahnd, src, mid, dst, run_id,
> + config->suspend_resume);
> +
> + if (surf_ctx != ctx) {
> + xe_engine_destroy(xe, engine);
> + xe_vm_destroy(xe, vm);
> + free(surf_ctx);
> + put_ahnd(surf_ahnd);
> + }
> + }
> +
> + blt_copy_init(xe, &blt);
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
> + if (config->inplace) {
> + blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type);
> + blt.dst.ptr = mid->ptr;
> + }
> +
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext);
> + intel_ctx_xe_sync(ctx, true);
> +
> + WRITE_PNG(xe, run_id, "dst", &blt.dst, width, height);
> +
> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> + /* Politely clean vm */
> + put_offset(ahnd, src->handle);
> + put_offset(ahnd, mid->handle);
> + put_offset(ahnd, dst->handle);
> + put_offset(ahnd, bb);
> + intel_allocator_bind(ahnd, 0, 0);
> + blt_destroy_object(xe, src);
> + blt_destroy_object(xe, mid);
> + blt_destroy_object(xe, dst);
> + gem_close(xe, bb);
> + put_ahnd(ahnd);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +static void block_multicopy(int xe,
> + intel_ctx_t *ctx,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling,
> + const struct test_config *config)
> +{
> + struct blt_copy3_data blt3 = {};
> + struct blt_copy_data blt = {};
> + struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3;
> + struct blt_copy_object *src, *mid, *dst, *final;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = xe_get_default_alignment(xe);
> + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC);
> + uint32_t run_id = mid_tiling;
> + uint32_t mid_region = region2, bb;
> + uint32_t width = param.width, height = param.height;
> + enum blt_compression mid_compression = config->compression;
> + int mid_compression_format = param.compression_format;
> + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> + uint8_t uc_mocs = intel_get_uc_mocs(xe);
> + int result;
> +
> + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> +
> + if (!blt_uses_extended_block_copy(xe))
> + pext3 = NULL;
> +
> + blt_copy_init(xe, &blt);
> +
> + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs,
> + mid_tiling, mid_compression, comp_type, true);
> + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
> + mid_tiling, COMPRESSION_DISABLED, comp_type, true);
> + final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + igt_assert(src->size == dst->size);
> + PRINT_SURFACE_INFO("src", src);
> + PRINT_SURFACE_INFO("mid", mid);
> + PRINT_SURFACE_INFO("dst", dst);
> + PRINT_SURFACE_INFO("final", final);
> +
> + blt_surface_fill_rect(xe, src, width, height);
> +
> + blt3.color_depth = CD_32bit;
> + blt3.print_bb = param.print_bb;
> + blt_set_copy_object(&blt3.src, src);
> + blt_set_copy_object(&blt3.mid, mid);
> + blt_set_copy_object(&blt3.dst, dst);
> + blt_set_copy_object(&blt3.final, final);
> +
> + if (config->inplace) {
> + blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region,
> + mid->mocs, mid_tiling, COMPRESSION_DISABLED,
> + comp_type);
> + blt3.dst.ptr = mid->ptr;
> + }
> +
> + blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_batch(&blt3.bb, bb, bb_size, region1);
> +
> + blt_block_copy3(xe, ctx, ahnd, &blt3, pext3);
> + intel_ctx_xe_sync(ctx, true);
> +
> + WRITE_PNG(xe, run_id, "src", &blt3.src, width, height);
> + if (!config->inplace)
> + WRITE_PNG(xe, run_id, "mid", &blt3.mid, width, height);
> + WRITE_PNG(xe, run_id, "dst", &blt3.dst, width, height);
> + WRITE_PNG(xe, run_id, "final", &blt3.final, width, height);
> +
> + result = memcmp(src->ptr, blt3.final.ptr, src->size);
> +
> + put_offset(ahnd, src->handle);
> + put_offset(ahnd, mid->handle);
> + put_offset(ahnd, dst->handle);
> + put_offset(ahnd, final->handle);
> + put_offset(ahnd, bb);
> + intel_allocator_bind(ahnd, 0, 0);
> + blt_destroy_object(xe, src);
> + blt_destroy_object(xe, mid);
> + blt_destroy_object(xe, dst);
> + blt_destroy_object(xe, final);
> + gem_close(xe, bb);
> + put_ahnd(ahnd);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +enum copy_func {
> + BLOCK_COPY,
> + BLOCK_MULTICOPY,
> +};
> +
> +static const struct {
> + const char *suffix;
> + void (*copyfn)(int fd,
> + intel_ctx_t *ctx,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type btype,
> + const struct test_config *config);
> +} copyfns[] = {
> + [BLOCK_COPY] = { "", block_copy },
> + [BLOCK_MULTICOPY] = { "-multicopy", block_multicopy },
> +};
> +
> +static void block_copy_test(int xe,
> + const struct test_config *config,
> + struct igt_collection *set,
> + enum copy_func copy_function)
> +{
> + struct drm_xe_engine_class_instance inst = {
> + .engine_class = DRM_XE_ENGINE_CLASS_COPY,
> + };
> + intel_ctx_t *ctx;
> + struct igt_collection *regions;
> + uint32_t vm, engine;
> + int tiling;
> +
> + if (config->compression && !blt_block_copy_supports_compression(xe))
> + return;
> +
> + if (config->inplace && !config->compression)
> + return;
> +
> + for_each_tiling(tiling) {
> + if (!blt_block_copy_supports_tiling(xe, tiling) ||
> + (param.tiling >= 0 && param.tiling != tiling))
> + continue;
> +
> + for_each_variation_r(regions, 2, set) {
> + uint32_t region1, region2;
> + char *regtxt;
> +
> + region1 = igt_collection_get_value(regions, 0);
> + region2 = igt_collection_get_value(regions, 1);
> +
> + /* Compressed surface must be in device memory */
> + if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2))
> + continue;
> +
> + regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
> +
> + igt_dynamic_f("%s-%s-compfmt%d-%s%s",
> + blt_tiling_name(tiling),
> + config->compression ?
> + "compressed" : "uncompressed",
> + param.compression_format, regtxt,
> + copyfns[copy_function].suffix) {
> + uint32_t sync_bind, sync_out;
> +
> + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> + engine = xe_engine_create(xe, vm, &inst, 0);
> + sync_bind = syncobj_create(xe, 0);
> + sync_out = syncobj_create(xe, 0);
> + ctx = intel_ctx_xe(xe, vm, engine,
> + 0, sync_bind, sync_out);
> +
> + copyfns[copy_function].copyfn(xe, ctx,
> + region1, region2,
> + tiling, config);
> +
> + xe_engine_destroy(xe, engine);
> + xe_vm_destroy(xe, vm);
> + syncobj_destroy(xe, sync_bind);
> + syncobj_destroy(xe, sync_out);
> + free(ctx);
> + }
> +
> + free(regtxt);
> + }
> + }
> +}
> +
> +static int opt_handler(int opt, int opt_index, void *data)
> +{
> + switch (opt) {
> + case 'b':
> + param.print_bb = true;
> + igt_debug("Print bb: %d\n", param.print_bb);
> + break;
> + case 'f':
> + param.compression_format = atoi(optarg);
> + igt_debug("Compression format: %d\n", param.compression_format);
> + igt_assert((param.compression_format & ~0x1f) == 0);
> + break;
> + case 'p':
> + param.write_png = true;
> + igt_debug("Write png: %d\n", param.write_png);
> + break;
> + case 's':
> + param.print_surface_info = true;
> + igt_debug("Print surface info: %d\n", param.print_surface_info);
> + break;
> + case 't':
> + param.tiling = atoi(optarg);
> + igt_debug("Tiling: %d\n", param.tiling);
> + break;
> + case 'W':
> + param.width = atoi(optarg);
> + igt_debug("Width: %d\n", param.width);
> + break;
> + case 'H':
> + param.height = atoi(optarg);
> + igt_debug("Height: %d\n", param.height);
> + break;
> + default:
> + return IGT_OPT_HANDLER_ERROR;
> + }
> +
> + return IGT_OPT_HANDLER_SUCCESS;
> +}
> +
> +const char *help_str =
> + " -b\tPrint bb\n"
> + " -f\tCompression format (0-31)\n"
> + " -p\tWrite PNG\n"
> + " -s\tPrint surface info\n"
> + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
> + " -W\tWidth (default 512)\n"
> + " -H\tHeight (default 512)"
> + ;
> +
> +igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> +{
> + struct igt_collection *set;
> + int xe;
> +
> + igt_fixture {
> + xe = drm_open_driver(DRIVER_XE);
> + igt_require(blt_has_block_copy(xe));
> +
> + xe_device_get(xe);
> +
> + set = xe_get_memory_region_set(xe,
> + XE_MEM_REGION_CLASS_SYSMEM,
> + XE_MEM_REGION_CLASS_VRAM);
> + }
> +
> + igt_describe("Check block-copy uncompressed blit");
> + igt_subtest_with_dynamic("block-copy-uncompressed") {
> + struct test_config config = {};
> +
> + block_copy_test(xe, &config, set, BLOCK_COPY);
> + }
> +
> + igt_describe("Check block-copy flatccs compressed blit");
> + igt_subtest_with_dynamic("block-copy-compressed") {
> + struct test_config config = { .compression = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_COPY);
> + }
> +
> + igt_describe("Check block-multicopy flatccs compressed blit");
> + igt_subtest_with_dynamic("block-multicopy-compressed") {
> + struct test_config config = { .compression = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_MULTICOPY);
> + }
> +
> + igt_describe("Check block-multicopy flatccs inplace decompression blit");
> + igt_subtest_with_dynamic("block-multicopy-inplace") {
> + struct test_config config = { .compression = true,
> + .inplace = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_MULTICOPY);
> + }
> +
> + igt_describe("Check flatccs data can be copied from/to surface");
> + igt_subtest_with_dynamic("ctrl-surf-copy") {
> + struct test_config config = { .compression = true,
> + .surfcopy = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_COPY);
> + }
> +
> + igt_describe("Check flatccs data are physically tagged and visible"
> + " in different contexts");
> + igt_subtest_with_dynamic("ctrl-surf-copy-new-ctx") {
> + struct test_config config = { .compression = true,
> + .surfcopy = true,
> + .new_ctx = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_COPY);
> + }
> +
> + igt_describe("Check flatccs data persists after suspend / resume (S0)");
> + igt_subtest_with_dynamic("suspend-resume") {
> + struct test_config config = { .compression = true,
> + .surfcopy = true,
> + .suspend_resume = true };
> +
> + block_copy_test(xe, &config, set, BLOCK_COPY);
> + }
> +
> + igt_fixture {
> + xe_device_put(xe);
> + close(xe);
> + }
> +}
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy for Xe
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (17 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 18/21] tests/xe_ccs: Check if flatccs is working with block-copy for Xe Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-13 7:43 ` Karolina Stolarek
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 20/21] tests/api-intel-allocator: Adopt to exercise allocator to Xe Zbigniew Kempczyński
` (6 subsequent siblings)
25 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Port this test to work on xe. Instead of adding conditional code for
xe code which would decrease readability this is new test for xe.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
v3: - Explicitely release offsets and unbind (Karolina)
- Use has-fast-copy instead of copied has-block-copy check (Karolina)
---
tests/meson.build | 1 +
tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++
2 files changed, 378 insertions(+)
create mode 100644 tests/xe/xe_exercise_blt.c
diff --git a/tests/meson.build b/tests/meson.build
index da8653fabc..3eddb2fb4e 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -276,6 +276,7 @@ xe_progs = [
'xe_exec_reset',
'xe_exec_store',
'xe_exec_threads',
+ 'xe_exercise_blt',
'xe_gpgpu_fill',
'xe_guc_pc',
'xe_huc_copy',
diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c
new file mode 100644
index 0000000000..693e80d0b7
--- /dev/null
+++ b/tests/xe/xe_exercise_blt.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "igt.h"
+#include "drm.h"
+#include "lib/intel_chipset.h"
+#include "intel_blt.h"
+#include "intel_mocs.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+#include "xe/xe_util.h"
+
+/**
+ * TEST: xe exercise blt
+ * Description: Exercise blitter commands on Xe
+ * Feature: blitter
+ * Run type: FULL
+ * Test category: GEM_Legacy
+ *
+ * SUBTEST: fast-copy
+ * Description:
+ * Check fast-copy blit
+ * blitter
+ *
+ * SUBTEST: fast-copy-emit
+ * Description:
+ * Check multiple fast-copy in one batch
+ * blitter
+ */
+
+IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe");
+
+static struct param {
+ int tiling;
+ bool write_png;
+ bool print_bb;
+ bool print_surface_info;
+ int width;
+ int height;
+} param = {
+ .tiling = -1,
+ .write_png = false,
+ .print_bb = false,
+ .print_surface_info = false,
+ .width = 512,
+ .height = 512,
+};
+
+#define PRINT_SURFACE_INFO(name, obj) do { \
+ if (param.print_surface_info) \
+ blt_surface_info((name), (obj)); } while (0)
+
+#define WRITE_PNG(fd, id, name, obj, w, h) do { \
+ if (param.write_png) \
+ blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
+
+struct blt_fast_copy_data {
+ int xe;
+ struct blt_copy_object src;
+ struct blt_copy_object mid;
+ struct blt_copy_object dst;
+
+ struct blt_copy_batch bb;
+ enum blt_color_depth color_depth;
+
+ /* debug stuff */
+ bool print_bb;
+};
+
+static int fast_copy_one_bb(int xe,
+ const intel_ctx_t *ctx,
+ uint64_t ahnd,
+ const struct blt_fast_copy_data *blt)
+{
+ struct blt_copy_data blt_tmp;
+ uint64_t bb_offset, alignment;
+ uint64_t bb_pos = 0;
+ int ret = 0;
+
+ alignment = xe_get_default_alignment(xe);
+
+ get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+ get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
+ get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+ bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+ /* First blit */
+ blt_copy_init(xe, &blt_tmp);
+ blt_tmp.src = blt->src;
+ blt_tmp.dst = blt->mid;
+ blt_tmp.bb = blt->bb;
+ blt_tmp.color_depth = blt->color_depth;
+ blt_tmp.print_bb = blt->print_bb;
+ bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false);
+
+ /* Second blit */
+ blt_copy_init(xe, &blt_tmp);
+ blt_tmp.src = blt->mid;
+ blt_tmp.dst = blt->dst;
+ blt_tmp.bb = blt->bb;
+ blt_tmp.color_depth = blt->color_depth;
+ blt_tmp.print_bb = blt->print_bb;
+ bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true);
+
+ intel_ctx_xe_exec(ctx, ahnd, bb_offset);
+
+ return ret;
+}
+
+static void fast_copy_emit(int xe, const intel_ctx_t *ctx,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling)
+{
+ struct blt_copy_data bltinit = {};
+ struct blt_fast_copy_data blt = {};
+ struct blt_copy_object *src, *mid, *dst;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = xe_get_default_alignment(xe);
+ uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ uint32_t bb, width = param.width, height = param.height;
+ int result;
+
+ bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+
+ blt_copy_init(xe, &bltinit);
+ src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ mid = blt_create_object(&bltinit, region2, width, height, bpp, 0,
+ mid_tiling, COMPRESSION_DISABLED, 0, true);
+ dst = blt_create_object(&bltinit, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ igt_assert(src->size == dst->size);
+
+ PRINT_SURFACE_INFO("src", src);
+ PRINT_SURFACE_INFO("mid", mid);
+ PRINT_SURFACE_INFO("dst", dst);
+
+ blt_surface_fill_rect(xe, src, width, height);
+ WRITE_PNG(xe, mid_tiling, "src", src, width, height);
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.mid, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ fast_copy_one_bb(xe, ctx, ahnd, &blt);
+
+ WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height);
+ WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
+
+ result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+ blt_destroy_object(xe, src);
+ blt_destroy_object(xe, mid);
+ blt_destroy_object(xe, dst);
+ gem_close(xe, bb);
+ put_ahnd(ahnd);
+
+ munmap(&bb, bb_size);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+static void fast_copy(int xe, const intel_ctx_t *ctx,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling)
+{
+ struct blt_copy_data blt = {};
+ struct blt_copy_object *src, *mid, *dst;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = xe_get_default_alignment(xe);
+ uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ uint32_t bb;
+ uint32_t width = param.width, height = param.height;
+ int result;
+
+ bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+
+ blt_copy_init(xe, &blt);
+ src = blt_create_object(&blt, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ mid = blt_create_object(&blt, region2, width, height, bpp, 0,
+ mid_tiling, COMPRESSION_DISABLED, 0, true);
+ dst = blt_create_object(&blt, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ igt_assert(src->size == dst->size);
+
+ blt_surface_fill_rect(xe, src, width, height);
+
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.dst, mid);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
+
+ WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height);
+ WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height);
+
+ blt_copy_init(xe, &blt);
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
+
+ WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
+
+ result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+ put_offset(ahnd, src->handle);
+ put_offset(ahnd, mid->handle);
+ put_offset(ahnd, dst->handle);
+ put_offset(ahnd, bb);
+ intel_allocator_bind(ahnd, 0, 0);
+ blt_destroy_object(xe, src);
+ blt_destroy_object(xe, mid);
+ blt_destroy_object(xe, dst);
+ gem_close(xe, bb);
+ put_ahnd(ahnd);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+enum fast_copy_func {
+ FAST_COPY,
+ FAST_COPY_EMIT
+};
+
+static char
+ *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
+ enum fast_copy_func func)
+{
+ char *name;
+ uint32_t len;
+
+ len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt,
+ func == FAST_COPY_EMIT ? "-emit" : "");
+
+ igt_assert_f(len >= 0, "asprintf failed!\n");
+
+ return name;
+}
+
+static void fast_copy_test(int xe,
+ struct igt_collection *set,
+ enum fast_copy_func func)
+{
+ struct drm_xe_engine_class_instance inst = {
+ .engine_class = DRM_XE_ENGINE_CLASS_COPY,
+ };
+ struct igt_collection *regions;
+ void (*copy_func)(int xe, const intel_ctx_t *ctx,
+ uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
+ intel_ctx_t *ctx;
+ int tiling;
+
+ for_each_tiling(tiling) {
+ if (!blt_fast_copy_supports_tiling(xe, tiling))
+ continue;
+
+ for_each_variation_r(regions, 2, set) {
+ uint32_t region1, region2;
+ uint32_t vm, engine;
+ char *regtxt, *test_name;
+
+ region1 = igt_collection_get_value(regions, 0);
+ region2 = igt_collection_get_value(regions, 1);
+
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
+ engine = xe_engine_create(xe, vm, &inst, 0);
+ ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0);
+
+ copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
+ regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
+ test_name = full_subtest_str(regtxt, tiling, func);
+
+ igt_dynamic_f("%s", test_name) {
+ copy_func(xe, ctx,
+ region1, region2,
+ tiling);
+ }
+
+ free(regtxt);
+ free(test_name);
+ xe_engine_destroy(xe, engine);
+ xe_vm_destroy(xe, vm);
+ free(ctx);
+ }
+ }
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'b':
+ param.print_bb = true;
+ igt_debug("Print bb: %d\n", param.print_bb);
+ break;
+ case 'p':
+ param.write_png = true;
+ igt_debug("Write png: %d\n", param.write_png);
+ break;
+ case 's':
+ param.print_surface_info = true;
+ igt_debug("Print surface info: %d\n", param.print_surface_info);
+ break;
+ case 't':
+ param.tiling = atoi(optarg);
+ igt_debug("Tiling: %d\n", param.tiling);
+ break;
+ case 'W':
+ param.width = atoi(optarg);
+ igt_debug("Width: %d\n", param.width);
+ break;
+ case 'H':
+ param.height = atoi(optarg);
+ igt_debug("Height: %d\n", param.height);
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -b\tPrint bb\n"
+ " -p\tWrite PNG\n"
+ " -s\tPrint surface info\n"
+ " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
+ " -W\tWidth (default 512)\n"
+ " -H\tHeight (default 512)"
+ ;
+
+igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
+{
+ struct igt_collection *set;
+ int xe;
+
+ igt_fixture {
+ xe = drm_open_driver(DRIVER_XE);
+ igt_require(blt_has_fast_copy(xe));
+
+ xe_device_get(xe);
+
+ set = xe_get_memory_region_set(xe,
+ XE_MEM_REGION_CLASS_SYSMEM,
+ XE_MEM_REGION_CLASS_VRAM);
+ }
+
+ igt_describe("Check fast-copy blit");
+ igt_subtest_with_dynamic("fast-copy") {
+ fast_copy_test(xe, set, FAST_COPY);
+ }
+
+ igt_describe("Check multiple fast-copy in one batch");
+ igt_subtest_with_dynamic("fast-copy-emit") {
+ fast_copy_test(xe, set, FAST_COPY_EMIT);
+ }
+
+ igt_fixture {
+ drm_close_driver(xe);
+ }
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy for Xe
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy " Zbigniew Kempczyński
@ 2023-07-13 7:43 ` Karolina Stolarek
2023-07-13 10:39 ` Zbigniew Kempczyński
0 siblings, 1 reply; 41+ messages in thread
From: Karolina Stolarek @ 2023-07-13 7:43 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> Port this test to work on xe. Instead of adding conditional code for
> xe code which would decrease readability this is new test for xe.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> v3: - Explicitely release offsets and unbind (Karolina)
> - Use has-fast-copy instead of copied has-block-copy check (Karolina)
> ---
> tests/meson.build | 1 +
> tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 378 insertions(+)
> create mode 100644 tests/xe/xe_exercise_blt.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index da8653fabc..3eddb2fb4e 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -276,6 +276,7 @@ xe_progs = [
> 'xe_exec_reset',
> 'xe_exec_store',
> 'xe_exec_threads',
> + 'xe_exercise_blt',
> 'xe_gpgpu_fill',
> 'xe_guc_pc',
> 'xe_huc_copy',
> diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c
> new file mode 100644
> index 0000000000..693e80d0b7
> --- /dev/null
> +++ b/tests/xe/xe_exercise_blt.c
> @@ -0,0 +1,377 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include "igt.h"
> +#include "drm.h"
> +#include "lib/intel_chipset.h"
> +#include "intel_blt.h"
> +#include "intel_mocs.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +#include "xe/xe_util.h"
> +
> +/**
> + * TEST: xe exercise blt
> + * Description: Exercise blitter commands on Xe
> + * Feature: blitter
> + * Run type: FULL
> + * Test category: GEM_Legacy
I forgot to ask about this category -- why is it "GEM Legacy" when it's
Xe? Copy-paste error? I think this should be removed, or changed to
something Xe-specific.
With that fixed:
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
> + *
> + * SUBTEST: fast-copy
> + * Description:
> + * Check fast-copy blit
> + * blitter
> + *
> + * SUBTEST: fast-copy-emit
> + * Description:
> + * Check multiple fast-copy in one batch
> + * blitter
> + */
> +
> +IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe");
> +
> +static struct param {
> + int tiling;
> + bool write_png;
> + bool print_bb;
> + bool print_surface_info;
> + int width;
> + int height;
> +} param = {
> + .tiling = -1,
> + .write_png = false,
> + .print_bb = false,
> + .print_surface_info = false,
> + .width = 512,
> + .height = 512,
> +};
> +
> +#define PRINT_SURFACE_INFO(name, obj) do { \
> + if (param.print_surface_info) \
> + blt_surface_info((name), (obj)); } while (0)
> +
> +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
> + if (param.write_png) \
> + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
> +
> +struct blt_fast_copy_data {
> + int xe;
> + struct blt_copy_object src;
> + struct blt_copy_object mid;
> + struct blt_copy_object dst;
> +
> + struct blt_copy_batch bb;
> + enum blt_color_depth color_depth;
> +
> + /* debug stuff */
> + bool print_bb;
> +};
> +
> +static int fast_copy_one_bb(int xe,
> + const intel_ctx_t *ctx,
> + uint64_t ahnd,
> + const struct blt_fast_copy_data *blt)
> +{
> + struct blt_copy_data blt_tmp;
> + uint64_t bb_offset, alignment;
> + uint64_t bb_pos = 0;
> + int ret = 0;
> +
> + alignment = xe_get_default_alignment(xe);
> +
> + get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> + get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
> + get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
> +
> + /* First blit */
> + blt_copy_init(xe, &blt_tmp);
> + blt_tmp.src = blt->src;
> + blt_tmp.dst = blt->mid;
> + blt_tmp.bb = blt->bb;
> + blt_tmp.color_depth = blt->color_depth;
> + blt_tmp.print_bb = blt->print_bb;
> + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false);
> +
> + /* Second blit */
> + blt_copy_init(xe, &blt_tmp);
> + blt_tmp.src = blt->mid;
> + blt_tmp.dst = blt->dst;
> + blt_tmp.bb = blt->bb;
> + blt_tmp.color_depth = blt->color_depth;
> + blt_tmp.print_bb = blt->print_bb;
> + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true);
> +
> + intel_ctx_xe_exec(ctx, ahnd, bb_offset);
> +
> + return ret;
> +}
> +
> +static void fast_copy_emit(int xe, const intel_ctx_t *ctx,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling)
> +{
> + struct blt_copy_data bltinit = {};
> + struct blt_fast_copy_data blt = {};
> + struct blt_copy_object *src, *mid, *dst;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = xe_get_default_alignment(xe);
> + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> + uint32_t bb, width = param.width, height = param.height;
> + int result;
> +
> + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> +
> + blt_copy_init(xe, &bltinit);
> + src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0,
> + mid_tiling, COMPRESSION_DISABLED, 0, true);
> + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + igt_assert(src->size == dst->size);
> +
> + PRINT_SURFACE_INFO("src", src);
> + PRINT_SURFACE_INFO("mid", mid);
> + PRINT_SURFACE_INFO("dst", dst);
> +
> + blt_surface_fill_rect(xe, src, width, height);
> + WRITE_PNG(xe, mid_tiling, "src", src, width, height);
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.mid, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + fast_copy_one_bb(xe, ctx, ahnd, &blt);
> +
> + WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height);
> + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
> +
> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> + blt_destroy_object(xe, src);
> + blt_destroy_object(xe, mid);
> + blt_destroy_object(xe, dst);
> + gem_close(xe, bb);
> + put_ahnd(ahnd);
> +
> + munmap(&bb, bb_size);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +static void fast_copy(int xe, const intel_ctx_t *ctx,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling)
> +{
> + struct blt_copy_data blt = {};
> + struct blt_copy_object *src, *mid, *dst;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = xe_get_default_alignment(xe);
> + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> + uint32_t bb;
> + uint32_t width = param.width, height = param.height;
> + int result;
> +
> + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> +
> + blt_copy_init(xe, &blt);
> + src = blt_create_object(&blt, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + mid = blt_create_object(&blt, region2, width, height, bpp, 0,
> + mid_tiling, COMPRESSION_DISABLED, 0, true);
> + dst = blt_create_object(&blt, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + igt_assert(src->size == dst->size);
> +
> + blt_surface_fill_rect(xe, src, width, height);
> +
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.dst, mid);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
> +
> + WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height);
> + WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height);
> +
> + blt_copy_init(xe, &blt);
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
> +
> + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
> +
> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> + put_offset(ahnd, src->handle);
> + put_offset(ahnd, mid->handle);
> + put_offset(ahnd, dst->handle);
> + put_offset(ahnd, bb);
> + intel_allocator_bind(ahnd, 0, 0);
> + blt_destroy_object(xe, src);
> + blt_destroy_object(xe, mid);
> + blt_destroy_object(xe, dst);
> + gem_close(xe, bb);
> + put_ahnd(ahnd);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +enum fast_copy_func {
> + FAST_COPY,
> + FAST_COPY_EMIT
> +};
> +
> +static char
> + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
> + enum fast_copy_func func)
> +{
> + char *name;
> + uint32_t len;
> +
> + len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt,
> + func == FAST_COPY_EMIT ? "-emit" : "");
> +
> + igt_assert_f(len >= 0, "asprintf failed!\n");
> +
> + return name;
> +}
> +
> +static void fast_copy_test(int xe,
> + struct igt_collection *set,
> + enum fast_copy_func func)
> +{
> + struct drm_xe_engine_class_instance inst = {
> + .engine_class = DRM_XE_ENGINE_CLASS_COPY,
> + };
> + struct igt_collection *regions;
> + void (*copy_func)(int xe, const intel_ctx_t *ctx,
> + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
> + intel_ctx_t *ctx;
> + int tiling;
> +
> + for_each_tiling(tiling) {
> + if (!blt_fast_copy_supports_tiling(xe, tiling))
> + continue;
> +
> + for_each_variation_r(regions, 2, set) {
> + uint32_t region1, region2;
> + uint32_t vm, engine;
> + char *regtxt, *test_name;
> +
> + region1 = igt_collection_get_value(regions, 0);
> + region2 = igt_collection_get_value(regions, 1);
> +
> + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> + engine = xe_engine_create(xe, vm, &inst, 0);
> + ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0);
> +
> + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
> + regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
> + test_name = full_subtest_str(regtxt, tiling, func);
> +
> + igt_dynamic_f("%s", test_name) {
> + copy_func(xe, ctx,
> + region1, region2,
> + tiling);
> + }
> +
> + free(regtxt);
> + free(test_name);
> + xe_engine_destroy(xe, engine);
> + xe_vm_destroy(xe, vm);
> + free(ctx);
> + }
> + }
> +}
> +
> +static int opt_handler(int opt, int opt_index, void *data)
> +{
> + switch (opt) {
> + case 'b':
> + param.print_bb = true;
> + igt_debug("Print bb: %d\n", param.print_bb);
> + break;
> + case 'p':
> + param.write_png = true;
> + igt_debug("Write png: %d\n", param.write_png);
> + break;
> + case 's':
> + param.print_surface_info = true;
> + igt_debug("Print surface info: %d\n", param.print_surface_info);
> + break;
> + case 't':
> + param.tiling = atoi(optarg);
> + igt_debug("Tiling: %d\n", param.tiling);
> + break;
> + case 'W':
> + param.width = atoi(optarg);
> + igt_debug("Width: %d\n", param.width);
> + break;
> + case 'H':
> + param.height = atoi(optarg);
> + igt_debug("Height: %d\n", param.height);
> + break;
> + default:
> + return IGT_OPT_HANDLER_ERROR;
> + }
> +
> + return IGT_OPT_HANDLER_SUCCESS;
> +}
> +
> +const char *help_str =
> + " -b\tPrint bb\n"
> + " -p\tWrite PNG\n"
> + " -s\tPrint surface info\n"
> + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
> + " -W\tWidth (default 512)\n"
> + " -H\tHeight (default 512)"
> + ;
> +
> +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
> +{
> + struct igt_collection *set;
> + int xe;
> +
> + igt_fixture {
> + xe = drm_open_driver(DRIVER_XE);
> + igt_require(blt_has_fast_copy(xe));
> +
> + xe_device_get(xe);
> +
> + set = xe_get_memory_region_set(xe,
> + XE_MEM_REGION_CLASS_SYSMEM,
> + XE_MEM_REGION_CLASS_VRAM);
> + }
> +
> + igt_describe("Check fast-copy blit");
> + igt_subtest_with_dynamic("fast-copy") {
> + fast_copy_test(xe, set, FAST_COPY);
> + }
> +
> + igt_describe("Check multiple fast-copy in one batch");
> + igt_subtest_with_dynamic("fast-copy-emit") {
> + fast_copy_test(xe, set, FAST_COPY_EMIT);
> + }
> +
> + igt_fixture {
> + drm_close_driver(xe);
> + }
> +}
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy for Xe
2023-07-13 7:43 ` Karolina Stolarek
@ 2023-07-13 10:39 ` Zbigniew Kempczyński
0 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-13 10:39 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Thu, Jul 13, 2023 at 09:43:54AM +0200, Karolina Stolarek wrote:
> On 12.07.2023 19:12, Zbigniew Kempczyński wrote:
> > Port this test to work on xe. Instead of adding conditional code for
> > xe code which would decrease readability this is new test for xe.
> >
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> > v3: - Explicitely release offsets and unbind (Karolina)
> > - Use has-fast-copy instead of copied has-block-copy check (Karolina)
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++
> > 2 files changed, 378 insertions(+)
> > create mode 100644 tests/xe/xe_exercise_blt.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build
> > index da8653fabc..3eddb2fb4e 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -276,6 +276,7 @@ xe_progs = [
> > 'xe_exec_reset',
> > 'xe_exec_store',
> > 'xe_exec_threads',
> > + 'xe_exercise_blt',
> > 'xe_gpgpu_fill',
> > 'xe_guc_pc',
> > 'xe_huc_copy',
> > diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c
> > new file mode 100644
> > index 0000000000..693e80d0b7
> > --- /dev/null
> > +++ b/tests/xe/xe_exercise_blt.c
> > @@ -0,0 +1,377 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +#include "igt.h"
> > +#include "drm.h"
> > +#include "lib/intel_chipset.h"
> > +#include "intel_blt.h"
> > +#include "intel_mocs.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +#include "xe/xe_util.h"
> > +
> > +/**
> > + * TEST: xe exercise blt
> > + * Description: Exercise blitter commands on Xe
> > + * Feature: blitter
> > + * Run type: FULL
> > + * Test category: GEM_Legacy
>
> I forgot to ask about this category -- why is it "GEM Legacy" when it's Xe?
> Copy-paste error? I think this should be removed, or changed to something
> Xe-specific.
Yes, copy-paste issue. I've fixed this before merge.
Thanks for the review.
--
Zbigniew
>
> With that fixed:
> Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
>
> > + *
> > + * SUBTEST: fast-copy
> > + * Description:
> > + * Check fast-copy blit
> > + * blitter
> > + *
> > + * SUBTEST: fast-copy-emit
> > + * Description:
> > + * Check multiple fast-copy in one batch
> > + * blitter
> > + */
> > +
> > +IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe");
> > +
> > +static struct param {
> > + int tiling;
> > + bool write_png;
> > + bool print_bb;
> > + bool print_surface_info;
> > + int width;
> > + int height;
> > +} param = {
> > + .tiling = -1,
> > + .write_png = false,
> > + .print_bb = false,
> > + .print_surface_info = false,
> > + .width = 512,
> > + .height = 512,
> > +};
> > +
> > +#define PRINT_SURFACE_INFO(name, obj) do { \
> > + if (param.print_surface_info) \
> > + blt_surface_info((name), (obj)); } while (0)
> > +
> > +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
> > + if (param.write_png) \
> > + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
> > +
> > +struct blt_fast_copy_data {
> > + int xe;
> > + struct blt_copy_object src;
> > + struct blt_copy_object mid;
> > + struct blt_copy_object dst;
> > +
> > + struct blt_copy_batch bb;
> > + enum blt_color_depth color_depth;
> > +
> > + /* debug stuff */
> > + bool print_bb;
> > +};
> > +
> > +static int fast_copy_one_bb(int xe,
> > + const intel_ctx_t *ctx,
> > + uint64_t ahnd,
> > + const struct blt_fast_copy_data *blt)
> > +{
> > + struct blt_copy_data blt_tmp;
> > + uint64_t bb_offset, alignment;
> > + uint64_t bb_pos = 0;
> > + int ret = 0;
> > +
> > + alignment = xe_get_default_alignment(xe);
> > +
> > + get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> > + get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
> > + get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> > + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
> > +
> > + /* First blit */
> > + blt_copy_init(xe, &blt_tmp);
> > + blt_tmp.src = blt->src;
> > + blt_tmp.dst = blt->mid;
> > + blt_tmp.bb = blt->bb;
> > + blt_tmp.color_depth = blt->color_depth;
> > + blt_tmp.print_bb = blt->print_bb;
> > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false);
> > +
> > + /* Second blit */
> > + blt_copy_init(xe, &blt_tmp);
> > + blt_tmp.src = blt->mid;
> > + blt_tmp.dst = blt->dst;
> > + blt_tmp.bb = blt->bb;
> > + blt_tmp.color_depth = blt->color_depth;
> > + blt_tmp.print_bb = blt->print_bb;
> > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true);
> > +
> > + intel_ctx_xe_exec(ctx, ahnd, bb_offset);
> > +
> > + return ret;
> > +}
> > +
> > +static void fast_copy_emit(int xe, const intel_ctx_t *ctx,
> > + uint32_t region1, uint32_t region2,
> > + enum blt_tiling_type mid_tiling)
> > +{
> > + struct blt_copy_data bltinit = {};
> > + struct blt_fast_copy_data blt = {};
> > + struct blt_copy_object *src, *mid, *dst;
> > + const uint32_t bpp = 32;
> > + uint64_t bb_size = xe_get_default_alignment(xe);
> > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
> > + INTEL_ALLOCATOR_SIMPLE,
> > + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> > + uint32_t bb, width = param.width, height = param.height;
> > + int result;
> > +
> > + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> > +
> > + blt_copy_init(xe, &bltinit);
> > + src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
> > + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> > + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0,
> > + mid_tiling, COMPRESSION_DISABLED, 0, true);
> > + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0,
> > + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> > + igt_assert(src->size == dst->size);
> > +
> > + PRINT_SURFACE_INFO("src", src);
> > + PRINT_SURFACE_INFO("mid", mid);
> > + PRINT_SURFACE_INFO("dst", dst);
> > +
> > + blt_surface_fill_rect(xe, src, width, height);
> > + WRITE_PNG(xe, mid_tiling, "src", src, width, height);
> > +
> > + memset(&blt, 0, sizeof(blt));
> > + blt.color_depth = CD_32bit;
> > + blt.print_bb = param.print_bb;
> > + blt_set_copy_object(&blt.src, src);
> > + blt_set_copy_object(&blt.mid, mid);
> > + blt_set_copy_object(&blt.dst, dst);
> > + blt_set_batch(&blt.bb, bb, bb_size, region1);
> > +
> > + fast_copy_one_bb(xe, ctx, ahnd, &blt);
> > +
> > + WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height);
> > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
> > +
> > + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> > +
> > + blt_destroy_object(xe, src);
> > + blt_destroy_object(xe, mid);
> > + blt_destroy_object(xe, dst);
> > + gem_close(xe, bb);
> > + put_ahnd(ahnd);
> > +
> > + munmap(&bb, bb_size);
> > +
> > + igt_assert_f(!result, "source and destination surfaces differs!\n");
> > +}
> > +
> > +static void fast_copy(int xe, const intel_ctx_t *ctx,
> > + uint32_t region1, uint32_t region2,
> > + enum blt_tiling_type mid_tiling)
> > +{
> > + struct blt_copy_data blt = {};
> > + struct blt_copy_object *src, *mid, *dst;
> > + const uint32_t bpp = 32;
> > + uint64_t bb_size = xe_get_default_alignment(xe);
> > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0,
> > + INTEL_ALLOCATOR_SIMPLE,
> > + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> > + uint32_t bb;
> > + uint32_t width = param.width, height = param.height;
> > + int result;
> > +
> > + bb = xe_bo_create_flags(xe, 0, bb_size, region1);
> > +
> > + blt_copy_init(xe, &blt);
> > + src = blt_create_object(&blt, region1, width, height, bpp, 0,
> > + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> > + mid = blt_create_object(&blt, region2, width, height, bpp, 0,
> > + mid_tiling, COMPRESSION_DISABLED, 0, true);
> > + dst = blt_create_object(&blt, region1, width, height, bpp, 0,
> > + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> > + igt_assert(src->size == dst->size);
> > +
> > + blt_surface_fill_rect(xe, src, width, height);
> > +
> > + blt.color_depth = CD_32bit;
> > + blt.print_bb = param.print_bb;
> > + blt_set_copy_object(&blt.src, src);
> > + blt_set_copy_object(&blt.dst, mid);
> > + blt_set_batch(&blt.bb, bb, bb_size, region1);
> > +
> > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
> > +
> > + WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height);
> > + WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height);
> > +
> > + blt_copy_init(xe, &blt);
> > + blt.color_depth = CD_32bit;
> > + blt.print_bb = param.print_bb;
> > + blt_set_copy_object(&blt.src, mid);
> > + blt_set_copy_object(&blt.dst, dst);
> > + blt_set_batch(&blt.bb, bb, bb_size, region1);
> > +
> > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt);
> > +
> > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height);
> > +
> > + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> > +
> > + put_offset(ahnd, src->handle);
> > + put_offset(ahnd, mid->handle);
> > + put_offset(ahnd, dst->handle);
> > + put_offset(ahnd, bb);
> > + intel_allocator_bind(ahnd, 0, 0);
> > + blt_destroy_object(xe, src);
> > + blt_destroy_object(xe, mid);
> > + blt_destroy_object(xe, dst);
> > + gem_close(xe, bb);
> > + put_ahnd(ahnd);
> > +
> > + igt_assert_f(!result, "source and destination surfaces differs!\n");
> > +}
> > +
> > +enum fast_copy_func {
> > + FAST_COPY,
> > + FAST_COPY_EMIT
> > +};
> > +
> > +static char
> > + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
> > + enum fast_copy_func func)
> > +{
> > + char *name;
> > + uint32_t len;
> > +
> > + len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt,
> > + func == FAST_COPY_EMIT ? "-emit" : "");
> > +
> > + igt_assert_f(len >= 0, "asprintf failed!\n");
> > +
> > + return name;
> > +}
> > +
> > +static void fast_copy_test(int xe,
> > + struct igt_collection *set,
> > + enum fast_copy_func func)
> > +{
> > + struct drm_xe_engine_class_instance inst = {
> > + .engine_class = DRM_XE_ENGINE_CLASS_COPY,
> > + };
> > + struct igt_collection *regions;
> > + void (*copy_func)(int xe, const intel_ctx_t *ctx,
> > + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
> > + intel_ctx_t *ctx;
> > + int tiling;
> > +
> > + for_each_tiling(tiling) {
> > + if (!blt_fast_copy_supports_tiling(xe, tiling))
> > + continue;
> > +
> > + for_each_variation_r(regions, 2, set) {
> > + uint32_t region1, region2;
> > + uint32_t vm, engine;
> > + char *regtxt, *test_name;
> > +
> > + region1 = igt_collection_get_value(regions, 0);
> > + region2 = igt_collection_get_value(regions, 1);
> > +
> > + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0);
> > + engine = xe_engine_create(xe, vm, &inst, 0);
> > + ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0);
> > +
> > + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
> > + regtxt = xe_memregion_dynamic_subtest_name(xe, regions);
> > + test_name = full_subtest_str(regtxt, tiling, func);
> > +
> > + igt_dynamic_f("%s", test_name) {
> > + copy_func(xe, ctx,
> > + region1, region2,
> > + tiling);
> > + }
> > +
> > + free(regtxt);
> > + free(test_name);
> > + xe_engine_destroy(xe, engine);
> > + xe_vm_destroy(xe, vm);
> > + free(ctx);
> > + }
> > + }
> > +}
> > +
> > +static int opt_handler(int opt, int opt_index, void *data)
> > +{
> > + switch (opt) {
> > + case 'b':
> > + param.print_bb = true;
> > + igt_debug("Print bb: %d\n", param.print_bb);
> > + break;
> > + case 'p':
> > + param.write_png = true;
> > + igt_debug("Write png: %d\n", param.write_png);
> > + break;
> > + case 's':
> > + param.print_surface_info = true;
> > + igt_debug("Print surface info: %d\n", param.print_surface_info);
> > + break;
> > + case 't':
> > + param.tiling = atoi(optarg);
> > + igt_debug("Tiling: %d\n", param.tiling);
> > + break;
> > + case 'W':
> > + param.width = atoi(optarg);
> > + igt_debug("Width: %d\n", param.width);
> > + break;
> > + case 'H':
> > + param.height = atoi(optarg);
> > + igt_debug("Height: %d\n", param.height);
> > + break;
> > + default:
> > + return IGT_OPT_HANDLER_ERROR;
> > + }
> > +
> > + return IGT_OPT_HANDLER_SUCCESS;
> > +}
> > +
> > +const char *help_str =
> > + " -b\tPrint bb\n"
> > + " -p\tWrite PNG\n"
> > + " -s\tPrint surface info\n"
> > + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
> > + " -W\tWidth (default 512)\n"
> > + " -H\tHeight (default 512)"
> > + ;
> > +
> > +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
> > +{
> > + struct igt_collection *set;
> > + int xe;
> > +
> > + igt_fixture {
> > + xe = drm_open_driver(DRIVER_XE);
> > + igt_require(blt_has_fast_copy(xe));
> > +
> > + xe_device_get(xe);
> > +
> > + set = xe_get_memory_region_set(xe,
> > + XE_MEM_REGION_CLASS_SYSMEM,
> > + XE_MEM_REGION_CLASS_VRAM);
> > + }
> > +
> > + igt_describe("Check fast-copy blit");
> > + igt_subtest_with_dynamic("fast-copy") {
> > + fast_copy_test(xe, set, FAST_COPY);
> > + }
> > +
> > + igt_describe("Check multiple fast-copy in one batch");
> > + igt_subtest_with_dynamic("fast-copy-emit") {
> > + fast_copy_test(xe, set, FAST_COPY_EMIT);
> > + }
> > +
> > + igt_fixture {
> > + drm_close_driver(xe);
> > + }
> > +}
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] [PATCH i-g-t v4 20/21] tests/api-intel-allocator: Adopt to exercise allocator to Xe
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (18 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 19/21] tests/xe_exercise_blt: Check blitter library fast-copy " Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 21/21] tests/gem_ccs: Avoid writing png twice Zbigniew Kempczyński
` (5 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
Xe vm binding requires some cooperation from allocator side (tracking
alloc()/free()) operations. This diverges the path internally inside
the allocator so it is necessary to check if allocator supports
properly both drivers.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
tests/i915/api_intel_allocator.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c
index 77c2d25e83..f3fcf8a341 100644
--- a/tests/i915/api_intel_allocator.c
+++ b/tests/i915/api_intel_allocator.c
@@ -9,6 +9,9 @@
#include "igt.h"
#include "igt_aux.h"
#include "intel_allocator.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
/**
* TEST: api intel allocator
* Category: Infrastructure
@@ -454,6 +457,7 @@ static void __simple_allocs(int fd)
uint32_t handles[SIMPLE_GROUP_ALLOCS];
uint64_t ahnd;
uint32_t ctx;
+ bool is_xe = is_xe_device(fd);
int i;
ctx = rand() % 2;
@@ -463,7 +467,12 @@ static void __simple_allocs(int fd)
uint32_t size;
size = (rand() % 4 + 1) * 0x1000;
- handles[i] = gem_create(fd, size);
+ if (is_xe)
+ handles[i] = xe_bo_create_flags(fd, 0, size,
+ system_memory(fd));
+ else
+ handles[i] = gem_create(fd, size);
+
intel_allocator_alloc(ahnd, handles[i], size, 0x1000);
}
@@ -573,8 +582,6 @@ static void reopen(int fd)
{
int fd2;
- igt_require_gem(fd);
-
fd2 = drm_reopen_driver(fd);
__reopen_allocs(fd, fd2, true);
@@ -587,8 +594,6 @@ static void reopen_fork(int fd)
{
int fd2;
- igt_require_gem(fd);
-
intel_allocator_multiprocess_start();
fd2 = drm_reopen_driver(fd);
@@ -838,7 +843,7 @@ igt_main
struct allocators *a;
igt_fixture {
- fd = drm_open_driver(DRIVER_INTEL);
+ fd = drm_open_driver(DRIVER_INTEL | DRIVER_XE);
atomic_init(&next_handle, 1);
srandom(0xdeadbeef);
}
@@ -911,12 +916,16 @@ igt_main
igt_subtest_f("open-vm")
open_vm(fd);
- igt_subtest_f("execbuf-with-allocator")
+ igt_subtest_f("execbuf-with-allocator") {
+ igt_require(is_i915_device(fd));
execbuf_with_allocator(fd);
+ }
igt_describe("Verifies creating and executing bb from gem pool");
- igt_subtest_f("gem-pool")
+ igt_subtest_f("gem-pool") {
+ igt_require(is_i915_device(fd));
gem_pool(fd);
+ }
igt_fixture
drm_close_driver(fd);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] [PATCH i-g-t v4 21/21] tests/gem_ccs: Avoid writing png twice
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (19 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 20/21] tests/api-intel-allocator: Adopt to exercise allocator to Xe Zbigniew Kempczyński
@ 2023-07-12 17:12 ` Zbigniew Kempczyński
2023-07-12 19:19 ` [igt-dev] ✓ Fi.CI.BAT: success for Extend intel_blt to work on Xe (rev4) Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-12 17:12 UTC (permalink / raw)
To: igt-dev
As Karolina noticed we write source png twice what's just takes
time as source surface is not touched. Drop one png write.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Karolina Stolarek <karolina.stolarek@intel.com>
Reviewed-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
tests/i915/gem_ccs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index 1a5f3674a0..f5d4ab3598 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -362,7 +362,6 @@ static void block_copy(int i915,
if (mid->compression)
igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0);
- WRITE_PNG(i915, run_id, "src", &blt.src, width, height);
WRITE_PNG(i915, run_id, "mid", &blt.dst, width, height);
if (config->surfcopy && pext) {
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for Extend intel_blt to work on Xe (rev4)
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (20 preceding siblings ...)
2023-07-12 17:12 ` [igt-dev] [PATCH i-g-t v4 21/21] tests/gem_ccs: Avoid writing png twice Zbigniew Kempczyński
@ 2023-07-12 19:19 ` Patchwork
2023-07-12 19:29 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-07-12 19:19 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5139 bytes --]
== Series Details ==
Series: Extend intel_blt to work on Xe (rev4)
URL : https://patchwork.freedesktop.org/series/120162/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13378 -> IGTPW_9394
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
Participating hosts (43 -> 42)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9394 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- bat-adlp-11: NOTRUN -> [ABORT][1] ([i915#8011])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-adlp-11/igt@core_auth@basic-auth.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#7940])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][4] -> [DMESG-FAIL][5] ([i915#7059])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@workarounds:
- bat-dg1-7: [PASS][6] -> [ABORT][7] ([i915#4983])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/bat-dg1-7/igt@i915_selftest@live@workarounds.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-dg1-7/igt@i915_selftest@live@workarounds.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][8] ([i915#6687] / [i915#7978] / [i915#8668])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [ABORT][9] ([i915#7677]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/bat-rpls-1/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-rpls-1/igt@i915_selftest@live@hangcheck.html
- fi-skl-guc: [DMESG-FAIL][11] ([i915#8723]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_module_load@load:
- bat-adlp-11: [ABORT][13] ([i915#4423]) -> [DMESG-WARN][14] ([i915#4423])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/bat-adlp-11/igt@i915_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-adlp-11/igt@i915_module_load@load.html
* igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: [SKIP][15] ([i915#1072]) -> [ABORT][16] ([i915#8442] / [i915#8712])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
[i915#8723]: https://gitlab.freedesktop.org/drm/intel/issues/8723
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7382 -> IGTPW_9394
CI-20190529: 20190529
CI_DRM_13378: 57ea1a97c50c63c77e3bfa46ee486e8a451be5e7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9394: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
IGT_7382: 1016723d49ff0ce3326af31468245f7b56930cc4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_ccs@block-copy-compressed
+igt@xe_ccs@block-copy-uncompressed
+igt@xe_ccs@block-multicopy-compressed
+igt@xe_ccs@block-multicopy-inplace
+igt@xe_ccs@ctrl-surf-copy
+igt@xe_ccs@ctrl-surf-copy-new-ctx
+igt@xe_ccs@suspend-resume
+igt@xe_exercise_blt@fast-copy
+igt@xe_exercise_blt@fast-copy-emit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
[-- Attachment #2: Type: text/html, Size: 6053 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* [igt-dev] ○ CI.xeBAT: info for Extend intel_blt to work on Xe (rev4)
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (21 preceding siblings ...)
2023-07-12 19:19 ` [igt-dev] ✓ Fi.CI.BAT: success for Extend intel_blt to work on Xe (rev4) Patchwork
@ 2023-07-12 19:29 ` Patchwork
2023-07-12 22:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-07-12 19:29 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 335 bytes --]
== Series Details ==
Series: Extend intel_blt to work on Xe (rev4)
URL : https://patchwork.freedesktop.org/series/120162/
State : info
== Summary ==
Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9394](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9394/index.html)
[-- Attachment #2: Type: text/html, Size: 851 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for Extend intel_blt to work on Xe (rev4)
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (22 preceding siblings ...)
2023-07-12 19:29 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
@ 2023-07-12 22:52 ` Patchwork
2023-07-13 5:51 ` Zbigniew Kempczyński
2023-07-13 7:30 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
2023-07-14 5:02 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
25 siblings, 1 reply; 41+ messages in thread
From: Patchwork @ 2023-07-12 22:52 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 55323 bytes --]
== Series Details ==
Series: Extend intel_blt to work on Xe (rev4)
URL : https://patchwork.freedesktop.org/series/120162/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13378_full -> IGTPW_9394_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_9394_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9394_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): pig-kbl-iris
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9394_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-snb: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
Known issues
------------
Here are the changes found in IGTPW_9394_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][4] -> [FAIL][5] ([i915#7742]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@drm_fdinfo@virtual-busy-hang-all.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][7] -> [ABORT][8] ([i915#7461] / [i915#8211])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk3/igt@gem_barrier_race@remote-request@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_create@create-ext-set-pat:
- shard-snb: NOTRUN -> [FAIL][9] ([i915#8621])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@gem_create@create-ext-set-pat.html
* igt@gem_create@hog-create@smem0:
- shard-dg2: NOTRUN -> [FAIL][10] ([i915#5892] / [i915#8758])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_create@hog-create@smem0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-mtlp: [PASS][11] -> [FAIL][12] ([i915#6121] / [i915#7916])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@gem_ctx_exec@basic-nohangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-mtlp: NOTRUN -> [SKIP][13] ([fdo#109314])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_exec_balancer@parallel:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#4525])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [PASS][16] -> [FAIL][17] ([i915#2842]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#3539] / [i915#4852])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#3281]) +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#3281])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: NOTRUN -> [ABORT][23] ([i915#7975] / [i915#8213])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [PASS][24] -> [TIMEOUT][25] ([i915#8628])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@gem_exec_whisper@basic-contexts-forked-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-mtlp: [PASS][26] -> [TIMEOUT][27] ([i915#7392])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-2/igt@gem_exec_whisper@basic-contexts-priority-all.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#4613] / [i915#7582])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#4077]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4083]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#3282]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3282]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gem_partial_pwrite_pread@write-display.html
* igt@gem_render_copy@y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#8428])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@gem_render_copy@y-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#4885])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#3297]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#3297])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-dg2: NOTRUN -> [FAIL][37] ([i915#3318])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-offset:
- shard-mtlp: NOTRUN -> [SKIP][38] ([fdo#109289])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][39] -> [ABORT][40] ([i915#5566])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl7/igt@gen9_exec_parse@allowed-all.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#2856]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglu: NOTRUN -> [SKIP][42] ([i915#2527] / [i915#2856]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-2/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [PASS][43] -> [FAIL][44] ([i915#8691])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][45] -> [SKIP][46] ([fdo#109271])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#1937])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-dg2: NOTRUN -> [SKIP][48] ([fdo#109506])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][49] -> [SKIP][50] ([i915#1397]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][51] -> [DMESG-FAIL][52] ([i915#6763])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4212])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1:
- shard-apl: [PASS][54] -> [FAIL][55] ([i915#2521])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-mtlp: [PASS][56] -> [FAIL][57] ([i915#2521])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#8502]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [FAIL][59] ([i915#8247]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][60] ([i915#8247]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#1769])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#5286]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][63] ([fdo#111614]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [PASS][64] -> [FAIL][65] ([i915#5138])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][66] -> [FAIL][67] ([i915#3743])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][68] ([fdo#111615] / [i915#5286])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#5190]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][70] ([fdo#111614])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][71] ([fdo#111615]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-tglu: NOTRUN -> [SKIP][72] ([fdo#111615])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#3689] / [i915#5354]) +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3689] / [i915#3886] / [i915#5354]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#3886] / [i915#5354] / [i915#6095])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][76] ([i915#3734] / [i915#5354] / [i915#6095])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#5354] / [i915#6095]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][78] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-8/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][79] ([i915#5354] / [i915#6095]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#5354]) +20 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#5354]) +4 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#6095]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#7828]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#7828]) +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#7828]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#7118])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content_type_change:
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#6944])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#3299]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][89] ([i915#7173]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_content_protection@lic@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-tglu: NOTRUN -> [SKIP][90] ([i915#3555]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#3555])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][92] ([fdo#109274] / [fdo#111767] / [i915#5354]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
- shard-rkl: NOTRUN -> [SKIP][93] ([fdo#111767] / [fdo#111825]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-mtlp: [PASS][94] -> [FAIL][95] ([i915#8248])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#3546]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][97] -> [FAIL][98] ([i915#2346])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-move@all-pipes:
- shard-mtlp: [PASS][99] -> [DMESG-WARN][100] ([i915#2017])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][101] ([fdo#109271])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#3555] / [i915#3840])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_dsc@dsc-with-bpc-formats.html
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#3555] / [i915#3840])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][104] ([fdo#109274] / [fdo#111767])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][105] ([fdo#109274]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-snb: NOTRUN -> [SKIP][106] ([fdo#109271] / [fdo#111767])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-rkl: NOTRUN -> [SKIP][107] ([fdo#111825]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
- shard-glk: [PASS][108] -> [FAIL][109] ([i915#79])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp4:
- shard-dg2: NOTRUN -> [FAIL][110] ([fdo#103375] / [i915#6121])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_flip@flip-vs-suspend@c-dp4.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#2672])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#2672]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][113] ([fdo#111825] / [i915#1825]) +4 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][114] ([fdo#109280])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3458]) +9 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#3023]) +6 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#8708]) +4 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#1825]) +4 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#3555] / [i915#8228])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@kms_hdr@static-toggle.html
- shard-tglu: NOTRUN -> [SKIP][120] ([i915#3555] / [i915#8228])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-suspend:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#8228]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#6953])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#5176]) +11 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#5176]) +5 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#5235]) +11 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#5235]) +5 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_psr@cursor_mmap_cpu:
- shard-tglu: NOTRUN -> [SKIP][127] ([fdo#110189]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@kms_psr@cursor_mmap_cpu.html
* igt@kms_psr@sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#1072]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_psr@sprite_plane_move.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#4235]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-rkl: [PASS][130] -> [ABORT][131] ([i915#7461])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-2/igt@kms_rotation_crc@sprite-rotation-270.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#4070] / [i915#533] / [i915#6768])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-c-query-busy-hang:
- shard-snb: NOTRUN -> [SKIP][133] ([fdo#109271]) +274 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb1/igt@kms_vblank@pipe-c-query-busy-hang.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#7387])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@perf@global-sseu-config.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-tglu: NOTRUN -> [SKIP][135] ([fdo#109289])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-7/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6-suspend:
- shard-snb: NOTRUN -> [DMESG-WARN][136] ([i915#8841]) +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb2/igt@perf_pmu@rc6-suspend.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [PASS][137] -> [FAIL][138] ([i915#6015]) +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#2575]) +2 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@v3d/v3d_perfmon@create-perfmon-exceed.html
* igt@v3d/v3d_submit_cl@multi-and-single-sync:
- shard-tglu: NOTRUN -> [SKIP][140] ([fdo#109315] / [i915#2575]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-3/igt@v3d/v3d_submit_cl@multi-and-single-sync.html
* igt@v3d/v3d_submit_csd@bad-multisync-pad:
- shard-rkl: NOTRUN -> [SKIP][141] ([fdo#109315]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@v3d/v3d_submit_csd@bad-multisync-pad.html
* igt@v3d/v3d_submit_csd@bad-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#2575]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@v3d/v3d_submit_csd@bad-perfmon.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#7711]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_tiling@get-bad-flags:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#7711])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@vc4/vc4_tiling@get-bad-flags.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-hang@vcs0:
- shard-mtlp: [FAIL][145] ([i915#2410]) -> [PASS][146] +3 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@gem_ctx_persistence@engines-hang@vcs0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_ctx_persistence@engines-hang@vcs0.html
* igt@gem_ctx_persistence@saturated-hostile@vecs0:
- shard-mtlp: [FAIL][147] ([i915#7816]) -> [PASS][148] +2 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@gem_ctx_persistence@saturated-hostile@vecs0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@gem_ctx_persistence@saturated-hostile@vecs0.html
* igt@gem_eio@hibernate:
- {shard-dg1}: [ABORT][149] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-14/igt@gem_eio@hibernate.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-16/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- shard-tglu: [TIMEOUT][151] ([i915#3063] / [i915#7941]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-tglu-9/igt@gem_eio@unwedge-stress.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-rkl: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@gem_exec_fair@basic-throttle@rcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-tglu: [FAIL][155] ([i915#2842]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-tglu-9/igt@gem_exec_fair@basic-throttle@rcs0.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@preemptive-hang@vcs0:
- shard-mtlp: [FAIL][157] ([i915#7327]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@gem_exec_schedule@preemptive-hang@vcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-dg2: [FAIL][159] ([fdo#103375] / [i915#6121]) -> [PASS][160] +1 similar issue
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-5/igt@gem_workarounds@suspend-resume-context.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_hangman@gt-engine-error@vcs0:
- shard-mtlp: [FAIL][161] ([i915#7069]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@i915_hangman@gt-engine-error@vcs0.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@i915_hangman@gt-engine-error@vcs0.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [ABORT][163] ([i915#4528] / [i915#8393]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb1/igt@i915_module_load@reload-no-display.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][165] ([i915#1397]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-rkl: [SKIP][167] ([i915#1397]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [FAIL][169] ([i915#5138]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][171] ([i915#2346]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][173] ([i915#79]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-dg2: [FAIL][175] ([i915#6880]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: [FAIL][177] ([i915#8292]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_vblank@pipe-c-query-idle-hang:
- shard-apl: [SKIP][179] ([fdo#109271]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl7/igt@kms_vblank@pipe-c-query-idle-hang.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@kms_vblank@pipe-c-query-idle-hang.html
- shard-glk: [SKIP][181] ([fdo#109271]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk3/igt@kms_vblank@pipe-c-query-idle-hang.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk9/igt@kms_vblank@pipe-c-query-idle-hang.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-dg2: [FAIL][183] ([i915#4349]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-5/igt@perf_pmu@busy-double-start@rcs0.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@busy-idle-check-all@vcs0:
- shard-dg2: [FAIL][185] ([i915#4521]) -> [PASS][186] +7 similar issues
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-1/igt@perf_pmu@busy-idle-check-all@vcs0.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@perf_pmu@busy-idle-check-all@vcs0.html
* igt@perf_pmu@busy-idle-check-all@vecs0:
- {shard-dg1}: [FAIL][187] ([i915#4521]) -> [PASS][188] +2 similar issues
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-15/igt@perf_pmu@busy-idle-check-all@vecs0.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-16/igt@perf_pmu@busy-idle-check-all@vecs0.html
* igt@perf_pmu@render-node-busy-idle@ccs0:
- shard-mtlp: [FAIL][189] ([i915#4349]) -> [PASS][190] +1 similar issue
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@perf_pmu@render-node-busy-idle@ccs0.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle@ccs0.html
* igt@syncobj_wait@wait-all-for-submit-delayed-submit:
- {shard-dg1}: [DMESG-WARN][191] ([i915#1982]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-12/igt@syncobj_wait@wait-all-for-submit-delayed-submit.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-18/igt@syncobj_wait@wait-all-for-submit-delayed-submit.html
#### Warnings ####
* igt@gem_workarounds@suspend-resume:
- shard-snb: [DMESG-FAIL][193] ([fdo#103375]) -> [DMESG-WARN][194] ([i915#8841])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb7/igt@gem_workarounds@suspend-resume.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb6/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-mtlp: [SKIP][195] ([fdo#109289] / [i915#8403]) -> [SKIP][196] ([fdo#109289])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][197] ([i915#8561]) -> [DMESG-FAIL][198] ([i915#1982] / [i915#8561])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_async_flips@crc@pipe-a-edp-1.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][199] ([i915#7118] / [i915#7162]) -> [SKIP][200] ([i915#7118])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-12/igt@kms_content_protection@content_type_change.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: [SKIP][201] ([i915#7118]) -> [SKIP][202] ([i915#7118] / [i915#7162])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-1/igt@kms_content_protection@mei_interface.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [FAIL][203] ([i915#2346]) -> [DMESG-FAIL][204] ([i915#2017] / [i915#5954])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][205] ([i915#3955]) -> [SKIP][206] ([fdo#110189] / [i915#3955])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][207] ([fdo#109285]) -> [SKIP][208] ([fdo#109285] / [i915#4098])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7327]: https://gitlab.freedesktop.org/drm/intel/issues/7327
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8393]: https://gitlab.freedesktop.org/drm/intel/issues/8393
[i915#8403]: https://gitlab.freedesktop.org/drm/intel/issues/8403
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7382 -> IGTPW_9394
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13378: 57ea1a97c50c63c77e3bfa46ee486e8a451be5e7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9394: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
IGT_7382: 1016723d49ff0ce3326af31468245f7b56930cc4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Extend intel_blt to work on Xe (rev4)
2023-07-12 22:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-07-13 5:51 ` Zbigniew Kempczyński
2023-07-14 5:13 ` Yedireswarapu, SaiX Nandan
0 siblings, 1 reply; 41+ messages in thread
From: Zbigniew Kempczyński @ 2023-07-13 5:51 UTC (permalink / raw)
To: igt-dev; +Cc: SaiX Nandan Yedireswarapu
On Wed, Jul 12, 2023 at 10:52:11PM +0000, Patchwork wrote:
> Patch Details
>
> Series: Extend intel_blt to work on Xe (rev4)
> URL: https://patchwork.freedesktop.org/series/120162/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
>
> CI Bug Log - changes from CI_DRM_13378_full -> IGTPW_9394_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_9394_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_9394_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
>
> Participating hosts (10 -> 9)
>
> Missing (1): pig-kbl-iris
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_9394_full:
>
> IGT changes
>
> Possible regressions
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> * shard-snb: PASS -> ABORT
Unrelated to the change.
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_9394_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@api_intel_bb@blit-reloc-purge-cache:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#8411)
> * igt@drm_fdinfo@most-busy-check-all@rcs0:
>
> * shard-rkl: PASS -> FAIL (i915#7742) +1 similar issue
> * igt@drm_fdinfo@virtual-busy-hang-all:
>
> * shard-dg2: NOTRUN -> SKIP (i915#8414)
> * igt@gem_barrier_race@remote-request@rcs0:
>
> * shard-glk: PASS -> ABORT (i915#7461 / i915#8211)
> * igt@gem_create@create-ext-set-pat:
>
> * shard-snb: NOTRUN -> FAIL (i915#8621)
> * igt@gem_create@hog-create@smem0:
>
> * shard-dg2: NOTRUN -> FAIL (i915#5892 / i915#8758)
> * igt@gem_ctx_exec@basic-nohangcheck:
>
> * shard-mtlp: PASS -> FAIL (i915#6121 / i915#7916)
> * igt@gem_ctx_param@set-priority-not-supported:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#109314)
> * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1099) +2 similar
> issues
> * igt@gem_exec_balancer@parallel:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4525)
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
>
> * shard-rkl: PASS -> FAIL (i915#2842) +2 similar issues
> * igt@gem_exec_fair@basic-pace@rcs0:
>
> * shard-glk: PASS -> FAIL (i915#2842)
> * igt@gem_exec_flush@basic-uc-ro-default:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3539 / i915#4852)
> * igt@gem_exec_reloc@basic-gtt-cpu-active:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3281) +4 similar issues
> * igt@gem_exec_reloc@basic-gtt-noreloc:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3281)
> * igt@gem_exec_suspend@basic-s4-devices@lmem0:
>
> * shard-dg2: NOTRUN -> ABORT (i915#7975 / i915#8213)
> * igt@gem_exec_whisper@basic-contexts-forked-all:
>
> * shard-mtlp: PASS -> TIMEOUT (i915#8628)
> * igt@gem_exec_whisper@basic-contexts-priority-all:
>
> * shard-mtlp: PASS -> TIMEOUT (i915#7392)
> * igt@gem_lmem_evict@dontneed-evict-race:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4613 / i915#7582)
> * igt@gem_mmap_gtt@fault-concurrent:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#4077) +3 similar issues
> * igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4083) +2 similar issues
> * igt@gem_partial_pwrite_pread@reads-display:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3282) +2 similar issues
> * igt@gem_partial_pwrite_pread@write-display:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3282) +1 similar issue
> * igt@gem_render_copy@y-tiled:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#8428)
> * igt@gem_softpin@evict-snoop-interruptible:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4885)
> * igt@gem_userptr_blits@dmabuf-sync:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3297) +1 similar issue
> * igt@gem_userptr_blits@readonly-unsync:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3297)
> * igt@gem_userptr_blits@vma-merge:
>
> * shard-dg2: NOTRUN -> FAIL (i915#3318)
> * igt@gen7_exec_parse@basic-offset:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#109289)
> * igt@gen9_exec_parse@allowed-all:
>
> * shard-apl: PASS -> ABORT (i915#5566)
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2856) +2 similar issues
> * igt@gen9_exec_parse@unaligned-jump:
>
> * shard-tglu: NOTRUN -> SKIP (i915#2527 / i915#2856) +1 similar
> issue
> * igt@i915_pipe_stress@stress-xrgb8888-untiled:
>
> * shard-mtlp: PASS -> FAIL (i915#8691)
> * igt@i915_pm_dc@dc9-dpms:
>
> * shard-apl: PASS -> SKIP (fdo#109271)
> * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
>
> * shard-rkl: NOTRUN -> SKIP (i915#1937)
> * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109506)
> * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
>
> * shard-rkl: PASS -> SKIP (i915#1397) +1 similar issue
> * igt@i915_selftest@live@workarounds:
>
> * shard-mtlp: PASS -> DMESG-FAIL (i915#6763)
> * igt@kms_addfb_basic@basic-x-tiled-legacy:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4212)
> * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1:
>
> * shard-apl: PASS -> FAIL (i915#2521)
> * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
>
> * shard-mtlp: PASS -> FAIL (i915#2521)
> * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#8502) +3 similar issues
> * igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
>
> * shard-dg2: NOTRUN -> FAIL (i915#8247) +3 similar issues
> * igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
>
> * shard-rkl: NOTRUN -> FAIL (i915#8247) +1 similar issue
> * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1769)
> * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5286) +1 similar issue
> * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#111614) +1 similar issue
> * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
>
> * shard-mtlp: PASS -> FAIL (i915#5138)
> * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
>
> * shard-mtlp: PASS -> FAIL (i915#3743)
> * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#5286)
> * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5190) +4 similar issues
> * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111614)
> * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#111615) +2 similar issues
> * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615)
> * igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#5354) +5 similar
> issues
> * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#3886 / i915#5354) +1
> similar issue
>
> * shard-rkl: NOTRUN -> SKIP (i915#3886 / i915#5354 / i915#6095)
>
> * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3734 / i915#5354 / i915#6095)
> * igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5354 / i915#6095) +2 similar
> issues
> * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#3689 / i915#5354 /
> i915#6095)
> * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs:
>
> * shard-tglu: NOTRUN -> SKIP (i915#5354 / i915#6095) +1 similar
> issue
> * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5354) +20 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#5354) +4 similar issues
>
> * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6095) +2 similar issues
> * igt@kms_chamelium_hpd@common-hpd-after-suspend:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#7828) +1 similar issue
> * igt@kms_chamelium_hpd@vga-hpd-after-suspend:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7828) +3 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#7828) +1 similar issue
>
> * igt@kms_content_protection@atomic:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7118)
> * igt@kms_content_protection@content_type_change:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6944)
> * igt@kms_content_protection@dp-mst-type-0:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3299) +1 similar issue
> * igt@kms_content_protection@lic@pipe-a-dp-4:
>
> * shard-dg2: NOTRUN -> TIMEOUT (i915#7173) +1 similar issue
> * igt@kms_cursor_crc@cursor-onscreen-max-size:
>
> * shard-tglu: NOTRUN -> SKIP (i915#3555) +1 similar issue
> * igt@kms_cursor_crc@cursor-random-32x10:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555)
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274 / fdo#111767 / i915#5354)
> +1 similar issue
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111767 / fdo#111825) +1 similar
> issue
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
>
> * shard-mtlp: PASS -> FAIL (i915#8248)
> * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3546) +1 similar issue
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-glk: PASS -> FAIL (i915#2346)
> * igt@kms_cursor_legacy@single-move@all-pipes:
>
> * shard-mtlp: PASS -> DMESG-WARN (i915#2017)
> * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271)
> * igt@kms_dsc@dsc-with-bpc-formats:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555 / i915#3840)
>
> * shard-rkl: NOTRUN -> SKIP (i915#3555 / i915#3840)
>
> * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274 / fdo#111767)
> * igt@kms_flip@2x-flip-vs-panning-vs-hang:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274) +2 similar issues
> * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / fdo#111767)
> * igt@kms_flip@2x-plain-flip-interruptible:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111825) +1 similar issue
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
>
> * shard-glk: PASS -> FAIL (i915#79)
> * igt@kms_flip@flip-vs-suspend@c-dp4:
>
> * shard-dg2: NOTRUN -> FAIL (fdo#103375 / i915#6121)
> * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
>
> * shard-rkl: NOTRUN -> SKIP (i915#2672)
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2672) +1 similar issue
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111825 / i915#1825) +4 similar
> issues
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109280)
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3458) +9 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#3023) +6 similar issues
>
> * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-dg2: NOTRUN -> SKIP (i915#8708) +4 similar issues
> * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#1825) +4 similar issues
> * igt@kms_hdr@static-toggle:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555 / i915#8228)
>
> * shard-tglu: NOTRUN -> SKIP (i915#3555 / i915#8228)
>
> * igt@kms_hdr@static-toggle-suspend:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3555 / i915#8228) +1 similar
> issue
> * igt@kms_plane_scaling@intel-max-src-size:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6953)
> * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5176) +11 similar issues
> * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5176) +5 similar issues
> * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5235) +11 similar issues
> * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5235) +5 similar issues
> * igt@kms_psr@cursor_mmap_cpu:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#110189) +1 similar issue
> * igt@kms_psr@sprite_plane_move:
>
> * shard-dg2: NOTRUN -> SKIP (i915#1072) +1 similar issue
> * igt@kms_rotation_crc@bad-pixel-format:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#4235) +1 similar issue
> * igt@kms_rotation_crc@sprite-rotation-270:
>
> * shard-rkl: PASS -> ABORT (i915#7461)
> * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4070 / i915#533 / i915#6768)
> * igt@kms_vblank@pipe-c-query-busy-hang:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271) +274 similar issues
> * igt@perf@global-sseu-config:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7387)
> * igt@perf@unprivileged-single-ctx-counters:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109289)
> * igt@perf_pmu@rc6-suspend:
>
> * shard-snb: NOTRUN -> DMESG-WARN (i915#8841) +2 similar issues
> * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
>
> * shard-mtlp: PASS -> FAIL (i915#6015) +2 similar issues
> * igt@v3d/v3d_perfmon@create-perfmon-exceed:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2575) +2 similar issues
> * igt@v3d/v3d_submit_cl@multi-and-single-sync:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109315 / i915#2575) +1 similar
> issue
> * igt@v3d/v3d_submit_csd@bad-multisync-pad:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#109315) +1 similar issue
> * igt@v3d/v3d_submit_csd@bad-perfmon:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#2575) +1 similar issue
> * igt@vc4/vc4_label_bo@set-kernel-name:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7711) +2 similar issues
> * igt@vc4/vc4_tiling@get-bad-flags:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#7711)
>
> Possible fixes
>
> * igt@gem_ctx_persistence@engines-hang@vcs0:
>
> * shard-mtlp: FAIL (i915#2410) -> PASS +3 similar issues
> * igt@gem_ctx_persistence@saturated-hostile@vecs0:
>
> * shard-mtlp: FAIL (i915#7816) -> PASS +2 similar issues
> * igt@gem_eio@hibernate:
>
> * {shard-dg1}: ABORT (i915#4391 / i915#7975 / i915#8213) -> PASS
> * igt@gem_eio@unwedge-stress:
>
> * shard-tglu: TIMEOUT (i915#3063 / i915#7941) -> PASS
> * igt@gem_exec_fair@basic-throttle@rcs0:
>
> * shard-rkl: FAIL (i915#2842) -> PASS
>
> * shard-tglu: FAIL (i915#2842) -> PASS
>
> * igt@gem_exec_schedule@preemptive-hang@vcs0:
>
> * shard-mtlp: FAIL (i915#7327) -> PASS
> * igt@gem_workarounds@suspend-resume-context:
>
> * shard-dg2: FAIL (fdo#103375 / i915#6121) -> PASS +1 similar issue
> * igt@i915_hangman@gt-engine-error@vcs0:
>
> * shard-mtlp: FAIL (i915#7069) -> PASS
> * igt@i915_module_load@reload-no-display:
>
> * shard-snb: ABORT (i915#4528 / i915#8393) -> PASS
> * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
>
> * shard-dg2: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rpm@modeset-non-lpsp:
>
> * shard-rkl: SKIP (i915#1397) -> PASS
> * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
>
> * shard-mtlp: FAIL (i915#5138) -> PASS
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-apl: FAIL (i915#2346) -> PASS
> * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
>
> * shard-glk: FAIL (i915#79) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
>
> * shard-dg2: FAIL (i915#6880) -> PASS
> * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
>
> * shard-rkl: FAIL (i915#8292) -> PASS
> * igt@kms_vblank@pipe-c-query-idle-hang:
>
> * shard-apl: SKIP (fdo#109271) -> PASS
>
> * shard-glk: SKIP (fdo#109271) -> PASS
>
> * igt@perf_pmu@busy-double-start@rcs0:
>
> * shard-dg2: FAIL (i915#4349) -> PASS
> * igt@perf_pmu@busy-idle-check-all@vcs0:
>
> * shard-dg2: FAIL (i915#4521) -> PASS +7 similar issues
> * igt@perf_pmu@busy-idle-check-all@vecs0:
>
> * {shard-dg1}: FAIL (i915#4521) -> PASS +2 similar issues
> * igt@perf_pmu@render-node-busy-idle@ccs0:
>
> * shard-mtlp: FAIL (i915#4349) -> PASS +1 similar issue
> * igt@syncobj_wait@wait-all-for-submit-delayed-submit:
>
> * {shard-dg1}: DMESG-WARN (i915#1982) -> PASS
>
> Warnings
>
> * igt@gem_workarounds@suspend-resume:
>
> * shard-snb: DMESG-FAIL (fdo#103375) -> DMESG-WARN (i915#8841)
> * igt@i915_pm_rc6_residency@media-rc6-accuracy:
>
> * shard-mtlp: SKIP (fdo#109289 / i915#8403) -> SKIP (fdo#109289)
> * igt@kms_async_flips@crc@pipe-a-edp-1:
>
> * shard-mtlp: DMESG-FAIL (i915#8561) -> DMESG-FAIL (i915#1982 /
> i915#8561)
> * igt@kms_content_protection@content_type_change:
>
> * shard-dg2: SKIP (i915#7118 / i915#7162) -> SKIP (i915#7118)
> * igt@kms_content_protection@mei_interface:
>
> * shard-dg2: SKIP (i915#7118) -> SKIP (i915#7118 / i915#7162)
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-mtlp: FAIL (i915#2346) -> DMESG-FAIL (i915#2017 /
> i915#5954)
> * igt@kms_fbcon_fbt@psr-suspend:
>
> * shard-rkl: SKIP (i915#3955) -> SKIP (fdo#110189 / i915#3955)
> * igt@kms_force_connector_basic@force-load-detect:
>
> * shard-rkl: SKIP (fdo#109285) -> SKIP (fdo#109285 / i915#4098)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_7382 -> IGTPW_9394
> * Piglit: piglit_4509 -> None
>
> CI-20190529: 20190529
> CI_DRM_13378: 57ea1a97c50c63c77e3bfa46ee486e8a451be5e7 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_9394: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
> IGT_7382: 1016723d49ff0ce3326af31468245f7b56930cc4 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Extend intel_blt to work on Xe (rev4)
2023-07-13 5:51 ` Zbigniew Kempczyński
@ 2023-07-14 5:13 ` Yedireswarapu, SaiX Nandan
0 siblings, 0 replies; 41+ messages in thread
From: Yedireswarapu, SaiX Nandan @ 2023-07-14 5:13 UTC (permalink / raw)
To: Kempczynski, Zbigniew, igt-dev@lists.freedesktop.org
Hi,
Issue re-reported, https://patchwork.freedesktop.org/series/120162/#rev4
Thanks,
Y Sai Nandan
-----Original Message-----
From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
Sent: Thursday, July 13, 2023 11:21 AM
To: igt-dev@lists.freedesktop.org
Cc: Yedireswarapu, SaiX Nandan <saix.nandan.yedireswarapu@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for Extend intel_blt to work on Xe (rev4)
On Wed, Jul 12, 2023 at 10:52:11PM +0000, Patchwork wrote:
> Patch Details
>
> Series: Extend intel_blt to work on Xe (rev4)
> URL: https://patchwork.freedesktop.org/series/120162/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
>
> CI Bug Log - changes from CI_DRM_13378_full -> IGTPW_9394_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_9394_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_9394_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
>
> Participating hosts (10 -> 9)
>
> Missing (1): pig-kbl-iris
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_9394_full:
>
> IGT changes
>
> Possible regressions
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> * shard-snb: PASS -> ABORT
Unrelated to the change.
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_9394_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@api_intel_bb@blit-reloc-purge-cache:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#8411)
> * igt@drm_fdinfo@most-busy-check-all@rcs0:
>
> * shard-rkl: PASS -> FAIL (i915#7742) +1 similar issue
> * igt@drm_fdinfo@virtual-busy-hang-all:
>
> * shard-dg2: NOTRUN -> SKIP (i915#8414)
> * igt@gem_barrier_race@remote-request@rcs0:
>
> * shard-glk: PASS -> ABORT (i915#7461 / i915#8211)
> * igt@gem_create@create-ext-set-pat:
>
> * shard-snb: NOTRUN -> FAIL (i915#8621)
> * igt@gem_create@hog-create@smem0:
>
> * shard-dg2: NOTRUN -> FAIL (i915#5892 / i915#8758)
> * igt@gem_ctx_exec@basic-nohangcheck:
>
> * shard-mtlp: PASS -> FAIL (i915#6121 / i915#7916)
> * igt@gem_ctx_param@set-priority-not-supported:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#109314)
> * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1099) +2 similar
> issues
> * igt@gem_exec_balancer@parallel:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4525)
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
>
> * shard-rkl: PASS -> FAIL (i915#2842) +2 similar issues
> * igt@gem_exec_fair@basic-pace@rcs0:
>
> * shard-glk: PASS -> FAIL (i915#2842)
> * igt@gem_exec_flush@basic-uc-ro-default:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3539 / i915#4852)
> * igt@gem_exec_reloc@basic-gtt-cpu-active:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3281) +4 similar issues
> * igt@gem_exec_reloc@basic-gtt-noreloc:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3281)
> * igt@gem_exec_suspend@basic-s4-devices@lmem0:
>
> * shard-dg2: NOTRUN -> ABORT (i915#7975 / i915#8213)
> * igt@gem_exec_whisper@basic-contexts-forked-all:
>
> * shard-mtlp: PASS -> TIMEOUT (i915#8628)
> * igt@gem_exec_whisper@basic-contexts-priority-all:
>
> * shard-mtlp: PASS -> TIMEOUT (i915#7392)
> * igt@gem_lmem_evict@dontneed-evict-race:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4613 / i915#7582)
> * igt@gem_mmap_gtt@fault-concurrent:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#4077) +3 similar issues
> * igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4083) +2 similar issues
> * igt@gem_partial_pwrite_pread@reads-display:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3282) +2 similar issues
> * igt@gem_partial_pwrite_pread@write-display:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3282) +1 similar issue
> * igt@gem_render_copy@y-tiled:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#8428)
> * igt@gem_softpin@evict-snoop-interruptible:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4885)
> * igt@gem_userptr_blits@dmabuf-sync:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3297) +1 similar issue
> * igt@gem_userptr_blits@readonly-unsync:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3297)
> * igt@gem_userptr_blits@vma-merge:
>
> * shard-dg2: NOTRUN -> FAIL (i915#3318)
> * igt@gen7_exec_parse@basic-offset:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#109289)
> * igt@gen9_exec_parse@allowed-all:
>
> * shard-apl: PASS -> ABORT (i915#5566)
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2856) +2 similar issues
> * igt@gen9_exec_parse@unaligned-jump:
>
> * shard-tglu: NOTRUN -> SKIP (i915#2527 / i915#2856) +1 similar
> issue
> * igt@i915_pipe_stress@stress-xrgb8888-untiled:
>
> * shard-mtlp: PASS -> FAIL (i915#8691)
> * igt@i915_pm_dc@dc9-dpms:
>
> * shard-apl: PASS -> SKIP (fdo#109271)
> * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
>
> * shard-rkl: NOTRUN -> SKIP (i915#1937)
> * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109506)
> * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
>
> * shard-rkl: PASS -> SKIP (i915#1397) +1 similar issue
> * igt@i915_selftest@live@workarounds:
>
> * shard-mtlp: PASS -> DMESG-FAIL (i915#6763)
> * igt@kms_addfb_basic@basic-x-tiled-legacy:
>
> * shard-dg2: NOTRUN -> SKIP (i915#4212)
> * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1:
>
> * shard-apl: PASS -> FAIL (i915#2521)
> * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
>
> * shard-mtlp: PASS -> FAIL (i915#2521)
> * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#8502) +3 similar issues
> * igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
>
> * shard-dg2: NOTRUN -> FAIL (i915#8247) +3 similar issues
> * igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
>
> * shard-rkl: NOTRUN -> FAIL (i915#8247) +1 similar issue
> * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1769)
> * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5286) +1 similar issue
> * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#111614) +1 similar issue
> * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
>
> * shard-mtlp: PASS -> FAIL (i915#5138)
> * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
>
> * shard-mtlp: PASS -> FAIL (i915#3743)
> * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#5286)
> * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5190) +4 similar issues
> * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111614)
> * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
>
> * shard-mtlp: NOTRUN -> SKIP (fdo#111615) +2 similar issues
> * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615)
> * igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#5354) +5 similar
> issues
> * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#3886 / i915#5354) +1
> similar issue
>
> * shard-rkl: NOTRUN -> SKIP (i915#3886 / i915#5354 / i915#6095)
>
> * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3734 / i915#5354 / i915#6095)
> * igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5354 / i915#6095) +2 similar
> issues
> * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#3689 / i915#5354 /
> i915#6095)
> * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs:
>
> * shard-tglu: NOTRUN -> SKIP (i915#5354 / i915#6095) +1 similar
> issue
> * igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5354) +20 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#5354) +4 similar issues
>
> * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6095) +2 similar issues
> * igt@kms_chamelium_hpd@common-hpd-after-suspend:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#7828) +1 similar issue
> * igt@kms_chamelium_hpd@vga-hpd-after-suspend:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7828) +3 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#7828) +1 similar issue
>
> * igt@kms_content_protection@atomic:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7118)
> * igt@kms_content_protection@content_type_change:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6944)
> * igt@kms_content_protection@dp-mst-type-0:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3299) +1 similar issue
> * igt@kms_content_protection@lic@pipe-a-dp-4:
>
> * shard-dg2: NOTRUN -> TIMEOUT (i915#7173) +1 similar issue
> * igt@kms_cursor_crc@cursor-onscreen-max-size:
>
> * shard-tglu: NOTRUN -> SKIP (i915#3555) +1 similar issue
> * igt@kms_cursor_crc@cursor-random-32x10:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555)
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274 / fdo#111767 / i915#5354)
> +1 similar issue
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111767 / fdo#111825) +1 similar
> issue
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
>
> * shard-mtlp: PASS -> FAIL (i915#8248)
> * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#3546) +1 similar issue
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-glk: PASS -> FAIL (i915#2346)
> * igt@kms_cursor_legacy@single-move@all-pipes:
>
> * shard-mtlp: PASS -> DMESG-WARN (i915#2017)
> * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271)
> * igt@kms_dsc@dsc-with-bpc-formats:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555 / i915#3840)
>
> * shard-rkl: NOTRUN -> SKIP (i915#3555 / i915#3840)
>
> * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274 / fdo#111767)
> * igt@kms_flip@2x-flip-vs-panning-vs-hang:
>
> * shard-dg2: NOTRUN -> SKIP (fdo#109274) +2 similar issues
> * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / fdo#111767)
> * igt@kms_flip@2x-plain-flip-interruptible:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111825) +1 similar issue
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
>
> * shard-glk: PASS -> FAIL (i915#79)
> * igt@kms_flip@flip-vs-suspend@c-dp4:
>
> * shard-dg2: NOTRUN -> FAIL (fdo#103375 / i915#6121)
> * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
>
> * shard-rkl: NOTRUN -> SKIP (i915#2672)
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2672) +1 similar issue
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#111825 / i915#1825) +4 similar
> issues
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109280)
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3458) +9 similar issues
>
> * shard-rkl: NOTRUN -> SKIP (i915#3023) +6 similar issues
>
> * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-dg2: NOTRUN -> SKIP (i915#8708) +4 similar issues
> * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#1825) +4 similar issues
> * igt@kms_hdr@static-toggle:
>
> * shard-dg2: NOTRUN -> SKIP (i915#3555 / i915#8228)
>
> * shard-tglu: NOTRUN -> SKIP (i915#3555 / i915#8228)
>
> * igt@kms_hdr@static-toggle-suspend:
>
> * shard-rkl: NOTRUN -> SKIP (i915#3555 / i915#8228) +1 similar
> issue
> * igt@kms_plane_scaling@intel-max-src-size:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#6953)
> * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5176) +11 similar issues
> * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5176) +5 similar issues
> * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2:
>
> * shard-dg2: NOTRUN -> SKIP (i915#5235) +11 similar issues
> * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2:
>
> * shard-rkl: NOTRUN -> SKIP (i915#5235) +5 similar issues
> * igt@kms_psr@cursor_mmap_cpu:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#110189) +1 similar issue
> * igt@kms_psr@sprite_plane_move:
>
> * shard-dg2: NOTRUN -> SKIP (i915#1072) +1 similar issue
> * igt@kms_rotation_crc@bad-pixel-format:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#4235) +1 similar issue
> * igt@kms_rotation_crc@sprite-rotation-270:
>
> * shard-rkl: PASS -> ABORT (i915#7461)
> * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
>
> * shard-rkl: NOTRUN -> SKIP (i915#4070 / i915#533 / i915#6768)
> * igt@kms_vblank@pipe-c-query-busy-hang:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271) +274 similar issues
> * igt@perf@global-sseu-config:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7387)
> * igt@perf@unprivileged-single-ctx-counters:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109289)
> * igt@perf_pmu@rc6-suspend:
>
> * shard-snb: NOTRUN -> DMESG-WARN (i915#8841) +2 similar issues
> * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
>
> * shard-mtlp: PASS -> FAIL (i915#6015) +2 similar issues
> * igt@v3d/v3d_perfmon@create-perfmon-exceed:
>
> * shard-dg2: NOTRUN -> SKIP (i915#2575) +2 similar issues
> * igt@v3d/v3d_submit_cl@multi-and-single-sync:
>
> * shard-tglu: NOTRUN -> SKIP (fdo#109315 / i915#2575) +1 similar
> issue
> * igt@v3d/v3d_submit_csd@bad-multisync-pad:
>
> * shard-rkl: NOTRUN -> SKIP (fdo#109315) +1 similar issue
> * igt@v3d/v3d_submit_csd@bad-perfmon:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#2575) +1 similar issue
> * igt@vc4/vc4_label_bo@set-kernel-name:
>
> * shard-dg2: NOTRUN -> SKIP (i915#7711) +2 similar issues
> * igt@vc4/vc4_tiling@get-bad-flags:
>
> * shard-mtlp: NOTRUN -> SKIP (i915#7711)
>
> Possible fixes
>
> * igt@gem_ctx_persistence@engines-hang@vcs0:
>
> * shard-mtlp: FAIL (i915#2410) -> PASS +3 similar issues
> * igt@gem_ctx_persistence@saturated-hostile@vecs0:
>
> * shard-mtlp: FAIL (i915#7816) -> PASS +2 similar issues
> * igt@gem_eio@hibernate:
>
> * {shard-dg1}: ABORT (i915#4391 / i915#7975 / i915#8213) -> PASS
> * igt@gem_eio@unwedge-stress:
>
> * shard-tglu: TIMEOUT (i915#3063 / i915#7941) -> PASS
> * igt@gem_exec_fair@basic-throttle@rcs0:
>
> * shard-rkl: FAIL (i915#2842) -> PASS
>
> * shard-tglu: FAIL (i915#2842) -> PASS
>
> * igt@gem_exec_schedule@preemptive-hang@vcs0:
>
> * shard-mtlp: FAIL (i915#7327) -> PASS
> * igt@gem_workarounds@suspend-resume-context:
>
> * shard-dg2: FAIL (fdo#103375 / i915#6121) -> PASS +1 similar issue
> * igt@i915_hangman@gt-engine-error@vcs0:
>
> * shard-mtlp: FAIL (i915#7069) -> PASS
> * igt@i915_module_load@reload-no-display:
>
> * shard-snb: ABORT (i915#4528 / i915#8393) -> PASS
> * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
>
> * shard-dg2: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rpm@modeset-non-lpsp:
>
> * shard-rkl: SKIP (i915#1397) -> PASS
> * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
>
> * shard-mtlp: FAIL (i915#5138) -> PASS
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-apl: FAIL (i915#2346) -> PASS
> * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
>
> * shard-glk: FAIL (i915#79) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
>
> * shard-dg2: FAIL (i915#6880) -> PASS
> * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
>
> * shard-rkl: FAIL (i915#8292) -> PASS
> * igt@kms_vblank@pipe-c-query-idle-hang:
>
> * shard-apl: SKIP (fdo#109271) -> PASS
>
> * shard-glk: SKIP (fdo#109271) -> PASS
>
> * igt@perf_pmu@busy-double-start@rcs0:
>
> * shard-dg2: FAIL (i915#4349) -> PASS
> * igt@perf_pmu@busy-idle-check-all@vcs0:
>
> * shard-dg2: FAIL (i915#4521) -> PASS +7 similar issues
> * igt@perf_pmu@busy-idle-check-all@vecs0:
>
> * {shard-dg1}: FAIL (i915#4521) -> PASS +2 similar issues
> * igt@perf_pmu@render-node-busy-idle@ccs0:
>
> * shard-mtlp: FAIL (i915#4349) -> PASS +1 similar issue
> * igt@syncobj_wait@wait-all-for-submit-delayed-submit:
>
> * {shard-dg1}: DMESG-WARN (i915#1982) -> PASS
>
> Warnings
>
> * igt@gem_workarounds@suspend-resume:
>
> * shard-snb: DMESG-FAIL (fdo#103375) -> DMESG-WARN (i915#8841)
> * igt@i915_pm_rc6_residency@media-rc6-accuracy:
>
> * shard-mtlp: SKIP (fdo#109289 / i915#8403) -> SKIP (fdo#109289)
> * igt@kms_async_flips@crc@pipe-a-edp-1:
>
> * shard-mtlp: DMESG-FAIL (i915#8561) -> DMESG-FAIL (i915#1982 /
> i915#8561)
> * igt@kms_content_protection@content_type_change:
>
> * shard-dg2: SKIP (i915#7118 / i915#7162) -> SKIP (i915#7118)
> * igt@kms_content_protection@mei_interface:
>
> * shard-dg2: SKIP (i915#7118) -> SKIP (i915#7118 / i915#7162)
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-mtlp: FAIL (i915#2346) -> DMESG-FAIL (i915#2017 /
> i915#5954)
> * igt@kms_fbcon_fbt@psr-suspend:
>
> * shard-rkl: SKIP (i915#3955) -> SKIP (fdo#110189 / i915#3955)
> * igt@kms_force_connector_basic@force-load-detect:
>
> * shard-rkl: SKIP (fdo#109285) -> SKIP (fdo#109285 / i915#4098)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_7382 -> IGTPW_9394
> * Piglit: piglit_4509 -> None
>
> CI-20190529: 20190529
> CI_DRM_13378: 57ea1a97c50c63c77e3bfa46ee486e8a451be5e7 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_9394: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
> IGT_7382: 1016723d49ff0ce3326af31468245f7b56930cc4 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
^ permalink raw reply [flat|nested] 41+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for Extend intel_blt to work on Xe (rev4)
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (23 preceding siblings ...)
2023-07-12 22:52 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-07-13 7:30 ` Patchwork
2023-07-14 5:02 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
25 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-07-13 7:30 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 335 bytes --]
== Series Details ==
Series: Extend intel_blt to work on Xe (rev4)
URL : https://patchwork.freedesktop.org/series/120162/
State : info
== Summary ==
Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9394](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9394/index.html)
[-- Attachment #2: Type: text/html, Size: 851 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* [igt-dev] ✓ Fi.CI.IGT: success for Extend intel_blt to work on Xe (rev4)
2023-07-12 17:12 [igt-dev] [PATCH i-g-t v4 00/21] Extend intel_blt to work on Xe Zbigniew Kempczyński
` (24 preceding siblings ...)
2023-07-13 7:30 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
@ 2023-07-14 5:02 ` Patchwork
25 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2023-07-14 5:02 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 54925 bytes --]
== Series Details ==
Series: Extend intel_blt to work on Xe (rev4)
URL : https://patchwork.freedesktop.org/series/120162/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13378_full -> IGTPW_9394_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): pig-kbl-iris
Known issues
------------
Here are the changes found in IGTPW_9394_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][2] -> [FAIL][3] ([i915#7742]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@drm_fdinfo@virtual-busy-hang-all.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][5] -> [ABORT][6] ([i915#7461] / [i915#8211])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk3/igt@gem_barrier_race@remote-request@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_create@create-ext-set-pat:
- shard-snb: NOTRUN -> [FAIL][7] ([i915#8621])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@gem_create@create-ext-set-pat.html
* igt@gem_create@hog-create@smem0:
- shard-dg2: NOTRUN -> [FAIL][8] ([i915#5892] / [i915#8758])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_create@hog-create@smem0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-mtlp: [PASS][9] -> [FAIL][10] ([i915#6121] / [i915#7916])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@gem_ctx_exec@basic-nohangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-mtlp: NOTRUN -> [SKIP][11] ([fdo#109314])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_exec_balancer@parallel:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#4525])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [PASS][14] -> [FAIL][15] ([i915#2842]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#3539] / [i915#4852])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#3281]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#3281])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: NOTRUN -> [ABORT][21] ([i915#7975] / [i915#8213])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [PASS][22] -> [TIMEOUT][23] ([i915#8628])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@gem_exec_whisper@basic-contexts-forked-all.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-mtlp: [PASS][24] -> [TIMEOUT][25] ([i915#7392])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-2/igt@gem_exec_whisper@basic-contexts-priority-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#4613] / [i915#7582])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#4077]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#4083]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#3282]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@gem_partial_pwrite_pread@reads-display.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3282]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gem_partial_pwrite_pread@write-display.html
* igt@gem_render_copy@y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#8428])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@gem_render_copy@y-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4885])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#3297]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#3297])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-dg2: NOTRUN -> [FAIL][35] ([i915#3318])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-offset:
- shard-mtlp: NOTRUN -> [SKIP][36] ([fdo#109289])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][37] -> [ABORT][38] ([i915#5566])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl7/igt@gen9_exec_parse@allowed-all.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#2856]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglu: NOTRUN -> [SKIP][40] ([i915#2527] / [i915#2856]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-2/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [PASS][41] -> [FAIL][42] ([i915#8691])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][43] -> [SKIP][44] ([fdo#109271])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#1937])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-dg2: NOTRUN -> [SKIP][46] ([fdo#109506])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][47] -> [SKIP][48] ([i915#1397]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][49] -> [DMESG-FAIL][50] ([i915#6763])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4212])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1:
- shard-apl: [PASS][52] -> [FAIL][53] ([i915#2521])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-1.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-mtlp: [PASS][54] -> [FAIL][55] ([i915#2521])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#8502]) +3 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [FAIL][57] ([i915#8247]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][58] ([i915#8247]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-snb: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#1769])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#5286]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][61] ([fdo#111614]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [PASS][62] -> [FAIL][63] ([i915#5138])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][64] -> [FAIL][65] ([i915#3743])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][66] ([fdo#111615] / [i915#5286])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#5190]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][68] ([fdo#111614])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][69] ([fdo#111615]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-tglu: NOTRUN -> [SKIP][70] ([fdo#111615])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#3689] / [i915#5354]) +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#3689] / [i915#3886] / [i915#5354]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#3886] / [i915#5354] / [i915#6095])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#3734] / [i915#5354] / [i915#6095])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#5354] / [i915#6095]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_ccs@pipe-b-missing-ccs-buffer-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][76] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-8/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][77] ([i915#5354] / [i915#6095]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#5354]) +20 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#5354]) +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_ccs@pipe-d-missing-ccs-buffer-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#6095]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#7828]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#7828]) +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#7828]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#7118])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content_type_change:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#6944])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3299]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][87] ([i915#7173]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_content_protection@lic@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#3555]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#3555])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][90] ([fdo#109274] / [fdo#111767] / [i915#5354]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
- shard-rkl: NOTRUN -> [SKIP][91] ([fdo#111767] / [fdo#111825]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-mtlp: [PASS][92] -> [FAIL][93] ([i915#8248])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#3546]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][95] -> [FAIL][96] ([i915#2346])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-move@all-pipes:
- shard-mtlp: [PASS][97] -> [DMESG-WARN][98] ([i915#2017])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#3555] / [i915#3840])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_dsc@dsc-with-bpc-formats.html
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#3555] / [i915#3840])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][102] ([fdo#109274] / [fdo#111767])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][103] ([fdo#109274]) +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-snb: NOTRUN -> [SKIP][104] ([fdo#109271] / [fdo#111767])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-rkl: NOTRUN -> [SKIP][105] ([fdo#111825]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
- shard-glk: [PASS][106] -> [FAIL][107] ([i915#79])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp4:
- shard-dg2: NOTRUN -> [FAIL][108] ([fdo#103375] / [i915#6121])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_flip@flip-vs-suspend@c-dp4.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][109] ([i915#2672])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#2672]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-snb: [PASS][111] -> [ABORT][112] ([i915#8865])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][113] ([fdo#111825] / [i915#1825]) +4 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][114] ([fdo#109280])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3458]) +9 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#3023]) +6 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#8708]) +4 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#1825]) +4 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#3555] / [i915#8228])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@kms_hdr@static-toggle.html
- shard-tglu: NOTRUN -> [SKIP][120] ([i915#3555] / [i915#8228])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-4/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-suspend:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#8228]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#6953])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#5176]) +11 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#5176]) +5 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#5235]) +11 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#5235]) +5 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_psr@cursor_mmap_cpu:
- shard-tglu: NOTRUN -> [SKIP][127] ([fdo#110189]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@kms_psr@cursor_mmap_cpu.html
* igt@kms_psr@sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#1072]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-7/igt@kms_psr@sprite_plane_move.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#4235]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-rkl: [PASS][130] -> [ABORT][131] ([i915#7461])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-2/igt@kms_rotation_crc@sprite-rotation-270.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#4070] / [i915#533] / [i915#6768])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-c-query-busy-hang:
- shard-snb: NOTRUN -> [SKIP][133] ([fdo#109271]) +274 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb1/igt@kms_vblank@pipe-c-query-busy-hang.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#7387])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-2/igt@perf@global-sseu-config.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-tglu: NOTRUN -> [SKIP][135] ([fdo#109289])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-7/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6-suspend:
- shard-snb: NOTRUN -> [DMESG-WARN][136] ([i915#8841]) +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb2/igt@perf_pmu@rc6-suspend.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [PASS][137] -> [FAIL][138] ([i915#6015]) +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#2575]) +2 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@v3d/v3d_perfmon@create-perfmon-exceed.html
* igt@v3d/v3d_submit_cl@multi-and-single-sync:
- shard-tglu: NOTRUN -> [SKIP][140] ([fdo#109315] / [i915#2575]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-3/igt@v3d/v3d_submit_cl@multi-and-single-sync.html
* igt@v3d/v3d_submit_csd@bad-multisync-pad:
- shard-rkl: NOTRUN -> [SKIP][141] ([fdo#109315]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-7/igt@v3d/v3d_submit_csd@bad-multisync-pad.html
* igt@v3d/v3d_submit_csd@bad-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#2575]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@v3d/v3d_submit_csd@bad-perfmon.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#7711]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_tiling@get-bad-flags:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#7711])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@vc4/vc4_tiling@get-bad-flags.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-hang@vcs0:
- shard-mtlp: [FAIL][145] ([i915#2410]) -> [PASS][146] +3 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@gem_ctx_persistence@engines-hang@vcs0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-6/igt@gem_ctx_persistence@engines-hang@vcs0.html
* igt@gem_ctx_persistence@saturated-hostile@vecs0:
- shard-mtlp: [FAIL][147] ([i915#7816]) -> [PASS][148] +2 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@gem_ctx_persistence@saturated-hostile@vecs0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@gem_ctx_persistence@saturated-hostile@vecs0.html
* igt@gem_eio@hibernate:
- {shard-dg1}: [ABORT][149] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-14/igt@gem_eio@hibernate.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-16/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- shard-tglu: [TIMEOUT][151] ([i915#3063] / [i915#7941]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-tglu-9/igt@gem_eio@unwedge-stress.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-rkl: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@gem_exec_fair@basic-throttle@rcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-tglu: [FAIL][155] ([i915#2842]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-tglu-9/igt@gem_exec_fair@basic-throttle@rcs0.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-tglu-10/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@preemptive-hang@vcs0:
- shard-mtlp: [FAIL][157] ([i915#7327]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@gem_exec_schedule@preemptive-hang@vcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-dg2: [FAIL][159] ([fdo#103375] / [i915#6121]) -> [PASS][160] +1 similar issue
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-5/igt@gem_workarounds@suspend-resume-context.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_hangman@gt-engine-error@vcs0:
- shard-mtlp: [FAIL][161] ([i915#7069]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-7/igt@i915_hangman@gt-engine-error@vcs0.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-2/igt@i915_hangman@gt-engine-error@vcs0.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [ABORT][163] ([i915#4528] / [i915#8393]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb1/igt@i915_module_load@reload-no-display.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb4/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][165] ([i915#1397]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-rkl: [SKIP][167] ([i915#1397]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [FAIL][169] ([i915#5138]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][171] ([i915#2346]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][173] ([i915#79]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-dg2: [FAIL][175] ([i915#6880]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: [FAIL][177] ([i915#8292]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_vblank@pipe-c-query-idle-hang:
- shard-apl: [SKIP][179] ([fdo#109271]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-apl7/igt@kms_vblank@pipe-c-query-idle-hang.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-apl1/igt@kms_vblank@pipe-c-query-idle-hang.html
- shard-glk: [SKIP][181] ([fdo#109271]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-glk3/igt@kms_vblank@pipe-c-query-idle-hang.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-glk9/igt@kms_vblank@pipe-c-query-idle-hang.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-dg2: [FAIL][183] ([i915#4349]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-5/igt@perf_pmu@busy-double-start@rcs0.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-8/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@busy-idle-check-all@vcs0:
- shard-dg2: [FAIL][185] ([i915#4521]) -> [PASS][186] +7 similar issues
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-1/igt@perf_pmu@busy-idle-check-all@vcs0.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-6/igt@perf_pmu@busy-idle-check-all@vcs0.html
* igt@perf_pmu@busy-idle-check-all@vecs0:
- {shard-dg1}: [FAIL][187] ([i915#4521]) -> [PASS][188] +2 similar issues
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-15/igt@perf_pmu@busy-idle-check-all@vecs0.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-16/igt@perf_pmu@busy-idle-check-all@vecs0.html
* igt@perf_pmu@render-node-busy-idle@ccs0:
- shard-mtlp: [FAIL][189] ([i915#4349]) -> [PASS][190] +1 similar issue
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-1/igt@perf_pmu@render-node-busy-idle@ccs0.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle@ccs0.html
* igt@syncobj_wait@wait-all-for-submit-delayed-submit:
- {shard-dg1}: [DMESG-WARN][191] ([i915#1982]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg1-12/igt@syncobj_wait@wait-all-for-submit-delayed-submit.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg1-18/igt@syncobj_wait@wait-all-for-submit-delayed-submit.html
#### Warnings ####
* igt@gem_workarounds@suspend-resume:
- shard-snb: [DMESG-FAIL][193] ([fdo#103375]) -> [DMESG-WARN][194] ([i915#8841])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-snb7/igt@gem_workarounds@suspend-resume.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-snb6/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-mtlp: [SKIP][195] ([fdo#109289] / [i915#8403]) -> [SKIP][196] ([fdo#109289])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][197] ([i915#8561]) -> [DMESG-FAIL][198] ([i915#1982] / [i915#8561])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-4/igt@kms_async_flips@crc@pipe-a-edp-1.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-7/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][199] ([i915#7118] / [i915#7162]) -> [SKIP][200] ([i915#7118])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-12/igt@kms_content_protection@content_type_change.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-5/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: [SKIP][201] ([i915#7118]) -> [SKIP][202] ([i915#7118] / [i915#7162])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-dg2-1/igt@kms_content_protection@mei_interface.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-dg2-12/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [FAIL][203] ([i915#2346]) -> [DMESG-FAIL][204] ([i915#2017] / [i915#5954])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][205] ([i915#3955]) -> [SKIP][206] ([fdo#110189] / [i915#3955])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][207] ([fdo#109285]) -> [SKIP][208] ([fdo#109285] / [i915#4098])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13378/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7327]: https://gitlab.freedesktop.org/drm/intel/issues/7327
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8393]: https://gitlab.freedesktop.org/drm/intel/issues/8393
[i915#8403]: https://gitlab.freedesktop.org/drm/intel/issues/8403
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7382 -> IGTPW_9394
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13378: 57ea1a97c50c63c77e3bfa46ee486e8a451be5e7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9394: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
IGT_7382: 1016723d49ff0ce3326af31468245f7b56930cc4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9394/index.html
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