* [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940
@ 2024-05-13 13:57 Sathishkumar S
2024-05-13 13:57 ` [PATCH i-g-t 2/2] tests/amdgpu: use 64x64 jpeg bitstream Sathishkumar S
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Sathishkumar S @ 2024-05-13 13:57 UTC (permalink / raw)
To: igt-dev; +Cc: Sathishkumar S, Leo Liu
update jpeg specific register offsets
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
---
tests/amdgpu/amd_jpeg_dec.c | 167 +++++++++++++++++++++++++++---------
1 file changed, 127 insertions(+), 40 deletions(-)
diff --git a/tests/amdgpu/amd_jpeg_dec.c b/tests/amdgpu/amd_jpeg_dec.c
index bb2a8e97e530..12f5bfcff556 100644
--- a/tests/amdgpu/amd_jpeg_dec.c
+++ b/tests/amdgpu/amd_jpeg_dec.c
@@ -53,6 +53,47 @@
#define vcnipUVD_JPEG_RB_RPTR 0x4003
#define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d
+#define vcnipUVD_JPEG_DEC_SOFT_RST_1 0x4051
+#define vcnipUVD_JPEG_PITCH_1 0x4043
+#define vcnipUVD_JPEG_UV_PITCH_1 0x4044
+#define vcnipJPEG_DEC_ADDR_MODE_1 0x404B
+#define vcnipUVD_JPEG_TIER_CNTL2_1 0x400E
+#define vcnipUVD_JPEG_OUTBUF_CNTL_1 0x4040
+#define vcnipUVD_JPEG_OUTBUF_WPTR_1 0x4041
+#define vcnipUVD_JPEG_OUTBUF_RPTR_1 0x4042
+#define vcnipUVD_JPEG_LUMA_BASE0_0 0x41C0
+#define vcnipUVD_JPEG_CHROMA_BASE0_0 0x41C1
+#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1 0x4048
+#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1 0x4049
+#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1 0x40B5
+#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1 0x40B4
+#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1 0x40B3
+#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1 0x40B2
+
+static uint32_t jpeg_dec_soft_rst;
+static uint32_t jrbc_ib_cond_rd_timer;
+static uint32_t jrbc_ib_ref_data;
+static uint32_t lmi_jpeg_read_64bit_bar_high;
+static uint32_t lmi_jpeg_read_64bit_bar_low;
+static uint32_t jpeg_rb_base;
+static uint32_t jpeg_rb_size;
+static uint32_t jpeg_rb_wptr;
+static uint32_t jpeg_pitch;
+static uint32_t jpeg_uv_pitch;
+static uint32_t dec_addr_mode;
+static uint32_t dec_y_gfx10_tiling_surface;
+static uint32_t dec_uv_gfx10_tiling_surface;
+static uint32_t lmi_jpeg_write_64bit_bar_high;
+static uint32_t lmi_jpeg_write_64bit_bar_low;
+static uint32_t jpeg_tier_cntl2;
+static uint32_t jpeg_outbuf_rptr;
+static uint32_t jpeg_outbuf_cntl;
+static uint32_t jpeg_int_en;
+static uint32_t jpeg_cntl;
+static uint32_t jpeg_rb_rptr;
+static uint32_t jpeg_outbuf_wptr;
+static uint32_t jpeg_luma_base0_0;
+static uint32_t jpeg_chroma_base0_0;
#define RDECODE_PKT_REG_J(x) ((unsigned int)(x)&0x3FFFF)
#define RDECODE_PKT_RES_J(x) (((unsigned int)(x)&0x3F) << 18)
@@ -104,6 +145,50 @@ is_jpeg_tests_enable(amdgpu_device_handle device_handle,
else
return false;
+ jrbc_ib_cond_rd_timer = vcnipUVD_JRBC_IB_COND_RD_TIMER;
+ jrbc_ib_ref_data = vcnipUVD_JRBC_IB_REF_DATA;
+ jpeg_rb_base = vcnipUVD_JPEG_RB_BASE;
+ jpeg_rb_size = vcnipUVD_JPEG_RB_SIZE;
+ jpeg_rb_wptr = vcnipUVD_JPEG_RB_WPTR;
+ jpeg_int_en = vcnipUVD_JPEG_INT_EN;
+ jpeg_cntl = vcnipUVD_JPEG_CNTL;
+ jpeg_rb_rptr = vcnipUVD_JPEG_RB_RPTR;
+
+ if (context->family_id == AMDGPU_FAMILY_AI &&
+ (context->chip_id - context->chip_rev) > 0x3c) { /* gfx940 */
+ jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST_1;
+ lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1;
+ lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1;
+ jpeg_pitch = vcnipUVD_JPEG_PITCH_1;
+ jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH_1;
+ dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE_1;
+ dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1;
+ dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1;
+ lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1;
+ lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1;
+ jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2_1;
+ jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL_1;
+ jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR_1;
+ jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR_1;
+ jpeg_luma_base0_0 = vcnipUVD_JPEG_LUMA_BASE0_0;
+ jpeg_chroma_base0_0 = vcnipUVD_JPEG_CHROMA_BASE0_0;
+ } else {
+ jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST;
+ lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH;
+ lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW;
+ jpeg_pitch = vcnipUVD_JPEG_PITCH;
+ jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH;
+ dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE;
+ dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE;
+ dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE;
+ lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH;
+ lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW;
+ jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2;
+ jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL;
+ jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR;
+ jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR;
+ }
+
return true;
}
@@ -277,39 +362,34 @@ send_cmd_bitstream_direct(struct mmd_context *context, uint64_t addr,
{
/* jpeg soft reset */
- set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1, idx);
+ set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 1, idx);
/* ensuring the Reset is asserted in SCLK domain */
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
- 0x01400200, idx);
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
- (0x1 << 0x10), idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
- (0x1 << 0x10), idx);
+ set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200, idx);
+ set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10), idx);
+ set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
/* wait mem */
- set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0, idx);
+ set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 0, idx);
/* ensuring the Reset is de-asserted in SCLK domain */
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10),
- idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
- (0x1 << 0x10), idx);
+ set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10), idx);
+ set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
/* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
- set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0,
+ set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_high, COND0, TYPE0,
(addr >> 32), idx);
- set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0,
+ set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_low, COND0, TYPE0,
addr, idx);
/* set jpeg_rb_base */
- set_reg_jpeg(context, vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0, idx);
+ set_reg_jpeg(context, jpeg_rb_base, COND0, TYPE0, 0, idx);
/* set jpeg_rb_base */
- set_reg_jpeg(context, vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0, idx);
+ set_reg_jpeg(context, jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0, idx);
/* set jpeg_rb_wptr */
- set_reg_jpeg(context, vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0,
+ set_reg_jpeg(context, jpeg_rb_wptr, COND0, TYPE0,
(JPEG_DEC_BSD_SIZE >> 2), idx);
}
@@ -319,59 +399,66 @@ send_cmd_target_direct(struct mmd_context *context, uint64_t addr,
uint32_t *idx)
{
- set_reg_jpeg(context, vcnipUVD_JPEG_PITCH, COND0, TYPE0,
+ set_reg_jpeg(context, jpeg_pitch, COND0, TYPE0,
(JPEG_DEC_DT_PITCH >> 4), idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0,
+ set_reg_jpeg(context, jpeg_uv_pitch, COND0, TYPE0,
(JPEG_DEC_DT_PITCH >> 4), idx);
- set_reg_jpeg(context, vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0, idx);
- set_reg_jpeg(context, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0,
+ set_reg_jpeg(context, dec_addr_mode, COND0, TYPE0, 0, idx);
+ set_reg_jpeg(context, dec_y_gfx10_tiling_surface, COND0, TYPE0,
0, idx);
- set_reg_jpeg(context, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0,
+ set_reg_jpeg(context, dec_uv_gfx10_tiling_surface, COND0, TYPE0,
0, idx);
/* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
- set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0,
+ set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_high, COND0, TYPE0,
(addr >> 32), idx);
- set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0,
+ set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_low, COND0, TYPE0,
addr, idx);
/* set output buffer data address */
- set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET,
- idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
+ if (jpeg_luma_base0_0) {
+ set_reg_jpeg(context, jpeg_luma_base0_0, COND0, TYPE0,
+ JPEG_DEC_LUMA_OFFSET, idx);
+ set_reg_jpeg(context, jpeg_chroma_base0_0, COND0, TYPE0,
JPEG_DEC_CHROMA_OFFSET, idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0, idx);
+ } else {
+ set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
+ set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
+ JPEG_DEC_LUMA_OFFSET, idx);
+ set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
+ set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
+ JPEG_DEC_CHROMA_OFFSET, idx);
+ }
+ set_reg_jpeg(context, jpeg_tier_cntl2, COND0, 0, 0, idx);
/* set output buffer read pointer */
- set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0, idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
+ set_reg_jpeg(context, jpeg_outbuf_rptr, COND0, TYPE0, 0, idx);
+ set_reg_jpeg(context, jpeg_outbuf_cntl, COND0, TYPE0,
((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)),
idx);
/* enable error interrupts */
- set_reg_jpeg(context, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE, idx);
+ set_reg_jpeg(context, jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE, idx);
/* start engine command */
- set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE, idx);
+ set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0xE, idx);
/* wait for job completion, wait for job JBSI fetch done */
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
+ set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0,
(JPEG_DEC_BSD_SIZE >> 2), idx);
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
+ set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0,
0x01400200, idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF, idx);
+ set_reg_jpeg(context, jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF, idx);
/* wait for job jpeg outbuf idle */
- set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF,
+ set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF,
idx);
- set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001,
+ set_reg_jpeg(context, jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001,
idx);
/* stop engine */
- set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4, idx);
+ set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0x4, idx);
}
static void
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH i-g-t 2/2] tests/amdgpu: use 64x64 jpeg bitstream
2024-05-13 13:57 [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940 Sathishkumar S
@ 2024-05-13 13:57 ` Sathishkumar S
2024-05-13 14:51 ` ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940 Patchwork
2024-05-15 17:16 ` [PATCH i-g-t 1/2] " Kamil Konieczny
2 siblings, 0 replies; 6+ messages in thread
From: Sathishkumar S @ 2024-05-13 13:57 UTC (permalink / raw)
To: igt-dev; +Cc: Sathishkumar S, Leo Liu
height to be aligned to mcu boundary on chroma plane as well.
tested on jpeg_1, jpeg_2, jpeg_3, jpeg_4_0_5, jpeg_4_0_3
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
---
lib/amdgpu/amd_mmd_decode_messages.h | 51 +++++++++++++++-------------
tests/amdgpu/amd_jpeg_dec.c | 31 +++++++++--------
2 files changed, 43 insertions(+), 39 deletions(-)
diff --git a/lib/amdgpu/amd_mmd_decode_messages.h b/lib/amdgpu/amd_mmd_decode_messages.h
index 22f223aaf733..20428d98549f 100644
--- a/lib/amdgpu/amd_mmd_decode_messages.h
+++ b/lib/amdgpu/amd_mmd_decode_messages.h
@@ -833,30 +833,33 @@ static const uint8_t feedback_msg[] = {
};
static const uint8_t jpeg_bitstream[] = {
- 0xFF, 0xD8, 0xFF, 0xDB, 0x01, 0x06, 0x00, 0x08, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05,
- 0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
- 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x08,
- 0x08, 0x09, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0B,
- 0x0B, 0x0E, 0x0E, 0x0E, 0x11, 0x11, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC4, 0x00, 0x4B, 0x00, 0x01,
- 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x08, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x08, 0x00, 0x08,
- 0x03, 0x00, 0x22, 0x00, 0x01, 0x11, 0x00, 0x02, 0x11, 0x00, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x00,
- 0x00, 0x01, 0x11, 0x02, 0x11, 0x00, 0x3F, 0x00, 0x9F, 0xC0, 0x07, 0xFF, 0xD9, 0xFF, 0xD9,
+ 0xFF,0xD8,0xFF,0xDB,0x01,0x06,0x00,0x08,0x04,0x04,0x04,0x04,0x04,0x05,0x05,0x05,
+ 0x05,0x05,0x05,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,
+ 0x07,0x07,0x07,0x08,0x08,0x08,0x07,0x07,0x07,0x06,0x06,0x07,0x07,0x08,0x08,0x08,
+ 0x08,0x09,0x09,0x09,0x08,0x08,0x08,0x08,0x09,0x09,0x0A,0x0A,0x0A,0x0C,0x0C,0x0B,
+ 0x0B,0x0E,0x0E,0x0E,0x11,0x11,0x14,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xC4,0x00,0x4B,0x00,0x01,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x08,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x11,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xC0,0x00,0x11,0x08,0x00,0x40,0x00,0x40,
+ 0x03,0x00,0x22,0x00,0x01,0x11,0x00,0x02,0x11,0x00,0xFF,0xDA,0x00,0x0C,0x03,0x00,
+ 0x00,0x01,0x11,0x02,0x11,0x00,0x3F,0x00,0x9F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x7F,0xFF,0xD9,0xFF,0xD9,
};
+
#endif /* _AMD_MMD_DECODE_MESSAGES_H_ */
diff --git a/tests/amdgpu/amd_jpeg_dec.c b/tests/amdgpu/amd_jpeg_dec.c
index 12f5bfcff556..8fcc471b8a88 100644
--- a/tests/amdgpu/amd_jpeg_dec.c
+++ b/tests/amdgpu/amd_jpeg_dec.c
@@ -113,13 +113,14 @@ static uint32_t jpeg_chroma_base0_0;
#define TYPE0 0
#define TYPE1 1
#define TYPE3 3
-#define JPEG_DEC_DT_PITCH 0x100
-#define JPEG_DEC_BSD_SIZE 0x180
-#define JPEG_DEC_LUMA_OFFSET 0
-#define JPEG_DEC_CHROMA_OFFSET 0x1000
-#define JPEG_DEC_SUM 4096
-#define IB_SIZE 4096
-#define MAX_RESOURCES 16
+#define JPEG_DEC_DT_PITCH 0x100
+#define WIDTH 64
+#define JPEG_DEC_BSD_SIZE 0x200
+#define JPEG_DEC_LUMA_OFFSET 0
+#define JPEG_DEC_CHROMA_OFFSET 0x4000
+#define JPEG_DEC_SUM 262144
+#define IB_SIZE 4096
+#define MAX_RESOURCES 16
static bool
is_jpeg_tests_enable(amdgpu_device_handle device_handle,
@@ -472,7 +473,7 @@ amdgpu_cs_jpeg_decode(amdgpu_device_handle device_handle,
int sum = 0, i, j;
uint32_t idx;
- size = 16 * 1024; /* 8K bitstream + 8K output */
+ size = 32 * 1024; /* 8K bitstream + 24K output */
context->num_resources = 0;
alloc_resource(device_handle, &dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM);
@@ -486,10 +487,10 @@ amdgpu_cs_jpeg_decode(amdgpu_device_handle device_handle,
if (context->jpeg_direct_reg == true) {
send_cmd_bitstream_direct(context, dec_buf.addr, &idx);
- send_cmd_target_direct(context, dec_buf.addr + (size / 2), &idx);
+ send_cmd_target_direct(context, dec_buf.addr + (size / 4), &idx);
} else {
send_cmd_bitstream(context, dec_buf.addr, &idx);
- send_cmd_target(context, dec_buf.addr + (size / 2), &idx);
+ send_cmd_target(context, dec_buf.addr + (size / 4), &idx);
}
amdgpu_bo_cpu_unmap(dec_buf.handle);
@@ -499,14 +500,14 @@ amdgpu_cs_jpeg_decode(amdgpu_device_handle device_handle,
r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
igt_assert_eq(r, 0);
- dec = dec_buf.ptr + (size / 2);
+ dec = dec_buf.ptr + (size / 4);
/* calculate result checksum */
- for (i = 0; i < 8; i++)
- for (j = 0; j < 8; j++)
+ for (i = 0; i < WIDTH; i++)
+ for (j = 0; j < WIDTH; j++)
sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
- for (i = 0; i < 4; i++)
- for (j = 0; j < 8; j++)
+ for (i = 0; i < (WIDTH/2); i++)
+ for (j = 0; j < WIDTH; j++)
sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
amdgpu_bo_cpu_unmap(dec_buf.handle);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940
2024-05-13 13:57 [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940 Sathishkumar S
2024-05-13 13:57 ` [PATCH i-g-t 2/2] tests/amdgpu: use 64x64 jpeg bitstream Sathishkumar S
@ 2024-05-13 14:51 ` Patchwork
2024-05-15 17:14 ` Kamil Konieczny
2024-05-15 17:16 ` [PATCH i-g-t 1/2] " Kamil Konieczny
2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2024-05-13 14:51 UTC (permalink / raw)
To: Sathishkumar S; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5564 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940
URL : https://patchwork.freedesktop.org/series/133544/
State : failure
== Summary ==
CI Bug Log - changes from IGT_7848 -> IGTPW_11133
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_11133 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_11133, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/index.html
Participating hosts (43 -> 40)
------------------------------
Additional (1): bat-mtlp-9
Missing (4): bat-mtlp-8 bat-arls-2 bat-jsl-1 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_11133:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@active:
- fi-glk-j4005: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/fi-glk-j4005/igt@i915_selftest@live@active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/fi-glk-j4005/igt@i915_selftest@live@active.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-a-dp-6:
- {bat-mtlp-9}: NOTRUN -> [FAIL][3] +2 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-a-dp-6.html
Known issues
------------
Here are the changes found in IGTPW_11133 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][4] -> [FAIL][5] ([i915#10378])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
* igt@i915_module_load@load:
- bat-arls-3: [PASS][6] -> [ABORT][7] ([i915#11041])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/bat-arls-3/igt@i915_module_load@load.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-arls-3/igt@i915_module_load@load.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][8] -> [ABORT][9] ([i915#10594])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/fi-bsw-nick/igt@i915_selftest@live@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9970]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9970
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7848 -> IGTPW_11133
CI-20190529: 20190529
CI_DRM_14754: 7def831e1e6b6d95c92e0a4fad9539a95141403d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_11133: 11133
IGT_7848: dc2d7fb4f978048b87707ea9ec32da748b01b378 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/index.html
[-- Attachment #2: Type: text/html, Size: 4478 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940
2024-05-13 14:51 ` ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940 Patchwork
@ 2024-05-15 17:14 ` Kamil Konieczny
0 siblings, 0 replies; 6+ messages in thread
From: Kamil Konieczny @ 2024-05-15 17:14 UTC (permalink / raw)
To: igt-dev; +Cc: Sathishkumar S, I915-ci-infra
Hi igt-dev,
On 2024-05-13 at 14:51:59 -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940
> URL : https://patchwork.freedesktop.org/series/133544/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from IGT_7848 -> IGTPW_11133
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with IGTPW_11133 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_11133, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/index.html
>
> Participating hosts (43 -> 40)
> ------------------------------
>
> Additional (1): bat-mtlp-9
> Missing (4): bat-mtlp-8 bat-arls-2 bat-jsl-1 fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in IGTPW_11133:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live@active:
> - fi-glk-j4005: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/fi-glk-j4005/igt@i915_selftest@live@active.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/fi-glk-j4005/igt@i915_selftest@live@active.html
>
>
Unrelated to amdgpu.
Regards
Kamil
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-a-dp-6:
> - {bat-mtlp-9}: NOTRUN -> [FAIL][3] +2 other tests fail
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-a-dp-6.html
>
>
> Known issues
> ------------
>
> Here are the changes found in IGTPW_11133 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_lmem_swapping@basic@lmem0:
> - bat-dg2-9: [PASS][4] -> [FAIL][5] ([i915#10378])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
>
> * igt@i915_module_load@load:
> - bat-arls-3: [PASS][6] -> [ABORT][7] ([i915#11041])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/bat-arls-3/igt@i915_module_load@load.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/bat-arls-3/igt@i915_module_load@load.html
>
> * igt@i915_selftest@live@execlists:
> - fi-bsw-nick: [PASS][8] -> [ABORT][9] ([i915#10594])
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7848/fi-bsw-nick/igt@i915_selftest@live@execlists.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/fi-bsw-nick/igt@i915_selftest@live@execlists.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
> [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
> [i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
> [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
> [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
> [i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
> [i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
> [i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
> [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
> [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
> [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
> [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
> [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
> [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
> [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
> [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
> [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
> [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
> [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
> [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
> [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
> [i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
> [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
> [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
> [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
> [i915#9970]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9970
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * IGT: IGT_7848 -> IGTPW_11133
>
> CI-20190529: 20190529
> CI_DRM_14754: 7def831e1e6b6d95c92e0a4fad9539a95141403d @ git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_11133: 11133
> IGT_7848: dc2d7fb4f978048b87707ea9ec32da748b01b378 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_11133/index.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940
2024-05-13 13:57 [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940 Sathishkumar S
2024-05-13 13:57 ` [PATCH i-g-t 2/2] tests/amdgpu: use 64x64 jpeg bitstream Sathishkumar S
2024-05-13 14:51 ` ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940 Patchwork
@ 2024-05-15 17:16 ` Kamil Konieczny
2024-05-16 9:11 ` Sundararaju, Sathishkumar
2 siblings, 1 reply; 6+ messages in thread
From: Kamil Konieczny @ 2024-05-15 17:16 UTC (permalink / raw)
To: igt-dev; +Cc: Sathishkumar S, Leo Liu
Hi Sathishkumar,
On 2024-05-13 at 19:27:04 +0530, Sathishkumar S wrote:
> update jpeg specific register offsets
--^
Start sentence with uppercase. No need for resend,
this can be corrected at merge.
Regards,
Kamil
>
> Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
> Acked-by: Leo Liu <leo.liu@amd.com>
> ---
> tests/amdgpu/amd_jpeg_dec.c | 167 +++++++++++++++++++++++++++---------
> 1 file changed, 127 insertions(+), 40 deletions(-)
>
> diff --git a/tests/amdgpu/amd_jpeg_dec.c b/tests/amdgpu/amd_jpeg_dec.c
> index bb2a8e97e530..12f5bfcff556 100644
> --- a/tests/amdgpu/amd_jpeg_dec.c
> +++ b/tests/amdgpu/amd_jpeg_dec.c
> @@ -53,6 +53,47 @@
> #define vcnipUVD_JPEG_RB_RPTR 0x4003
> #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d
>
> +#define vcnipUVD_JPEG_DEC_SOFT_RST_1 0x4051
> +#define vcnipUVD_JPEG_PITCH_1 0x4043
> +#define vcnipUVD_JPEG_UV_PITCH_1 0x4044
> +#define vcnipJPEG_DEC_ADDR_MODE_1 0x404B
> +#define vcnipUVD_JPEG_TIER_CNTL2_1 0x400E
> +#define vcnipUVD_JPEG_OUTBUF_CNTL_1 0x4040
> +#define vcnipUVD_JPEG_OUTBUF_WPTR_1 0x4041
> +#define vcnipUVD_JPEG_OUTBUF_RPTR_1 0x4042
> +#define vcnipUVD_JPEG_LUMA_BASE0_0 0x41C0
> +#define vcnipUVD_JPEG_CHROMA_BASE0_0 0x41C1
> +#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1 0x4048
> +#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1 0x4049
> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1 0x40B5
> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1 0x40B4
> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1 0x40B3
> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1 0x40B2
> +
> +static uint32_t jpeg_dec_soft_rst;
> +static uint32_t jrbc_ib_cond_rd_timer;
> +static uint32_t jrbc_ib_ref_data;
> +static uint32_t lmi_jpeg_read_64bit_bar_high;
> +static uint32_t lmi_jpeg_read_64bit_bar_low;
> +static uint32_t jpeg_rb_base;
> +static uint32_t jpeg_rb_size;
> +static uint32_t jpeg_rb_wptr;
> +static uint32_t jpeg_pitch;
> +static uint32_t jpeg_uv_pitch;
> +static uint32_t dec_addr_mode;
> +static uint32_t dec_y_gfx10_tiling_surface;
> +static uint32_t dec_uv_gfx10_tiling_surface;
> +static uint32_t lmi_jpeg_write_64bit_bar_high;
> +static uint32_t lmi_jpeg_write_64bit_bar_low;
> +static uint32_t jpeg_tier_cntl2;
> +static uint32_t jpeg_outbuf_rptr;
> +static uint32_t jpeg_outbuf_cntl;
> +static uint32_t jpeg_int_en;
> +static uint32_t jpeg_cntl;
> +static uint32_t jpeg_rb_rptr;
> +static uint32_t jpeg_outbuf_wptr;
> +static uint32_t jpeg_luma_base0_0;
> +static uint32_t jpeg_chroma_base0_0;
>
> #define RDECODE_PKT_REG_J(x) ((unsigned int)(x)&0x3FFFF)
> #define RDECODE_PKT_RES_J(x) (((unsigned int)(x)&0x3F) << 18)
> @@ -104,6 +145,50 @@ is_jpeg_tests_enable(amdgpu_device_handle device_handle,
> else
> return false;
>
> + jrbc_ib_cond_rd_timer = vcnipUVD_JRBC_IB_COND_RD_TIMER;
> + jrbc_ib_ref_data = vcnipUVD_JRBC_IB_REF_DATA;
> + jpeg_rb_base = vcnipUVD_JPEG_RB_BASE;
> + jpeg_rb_size = vcnipUVD_JPEG_RB_SIZE;
> + jpeg_rb_wptr = vcnipUVD_JPEG_RB_WPTR;
> + jpeg_int_en = vcnipUVD_JPEG_INT_EN;
> + jpeg_cntl = vcnipUVD_JPEG_CNTL;
> + jpeg_rb_rptr = vcnipUVD_JPEG_RB_RPTR;
> +
> + if (context->family_id == AMDGPU_FAMILY_AI &&
> + (context->chip_id - context->chip_rev) > 0x3c) { /* gfx940 */
> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST_1;
> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1;
> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1;
> + jpeg_pitch = vcnipUVD_JPEG_PITCH_1;
> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH_1;
> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE_1;
> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1;
> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1;
> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1;
> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1;
> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2_1;
> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL_1;
> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR_1;
> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR_1;
> + jpeg_luma_base0_0 = vcnipUVD_JPEG_LUMA_BASE0_0;
> + jpeg_chroma_base0_0 = vcnipUVD_JPEG_CHROMA_BASE0_0;
> + } else {
> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST;
> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH;
> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW;
> + jpeg_pitch = vcnipUVD_JPEG_PITCH;
> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH;
> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE;
> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE;
> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE;
> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH;
> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW;
> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2;
> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL;
> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR;
> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR;
> + }
> +
> return true;
> }
>
> @@ -277,39 +362,34 @@ send_cmd_bitstream_direct(struct mmd_context *context, uint64_t addr,
> {
>
> /* jpeg soft reset */
> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1, idx);
> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 1, idx);
>
> /* ensuring the Reset is asserted in SCLK domain */
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
> - 0x01400200, idx);
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
> - (0x1 << 0x10), idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
> - (0x1 << 0x10), idx);
> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200, idx);
> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10), idx);
> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
>
> /* wait mem */
> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0, idx);
> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 0, idx);
>
> /* ensuring the Reset is de-asserted in SCLK domain */
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10),
> - idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
> - (0x1 << 0x10), idx);
> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10), idx);
> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
>
> /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0,
> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_high, COND0, TYPE0,
> (addr >> 32), idx);
> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0,
> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_low, COND0, TYPE0,
> addr, idx);
>
> /* set jpeg_rb_base */
> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0, idx);
> + set_reg_jpeg(context, jpeg_rb_base, COND0, TYPE0, 0, idx);
>
> /* set jpeg_rb_base */
> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0, idx);
> + set_reg_jpeg(context, jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0, idx);
>
> /* set jpeg_rb_wptr */
> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0,
> + set_reg_jpeg(context, jpeg_rb_wptr, COND0, TYPE0,
> (JPEG_DEC_BSD_SIZE >> 2), idx);
> }
>
> @@ -319,59 +399,66 @@ send_cmd_target_direct(struct mmd_context *context, uint64_t addr,
> uint32_t *idx)
> {
>
> - set_reg_jpeg(context, vcnipUVD_JPEG_PITCH, COND0, TYPE0,
> + set_reg_jpeg(context, jpeg_pitch, COND0, TYPE0,
> (JPEG_DEC_DT_PITCH >> 4), idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0,
> + set_reg_jpeg(context, jpeg_uv_pitch, COND0, TYPE0,
> (JPEG_DEC_DT_PITCH >> 4), idx);
>
> - set_reg_jpeg(context, vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0, idx);
> - set_reg_jpeg(context, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0,
> + set_reg_jpeg(context, dec_addr_mode, COND0, TYPE0, 0, idx);
> + set_reg_jpeg(context, dec_y_gfx10_tiling_surface, COND0, TYPE0,
> 0, idx);
> - set_reg_jpeg(context, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0,
> + set_reg_jpeg(context, dec_uv_gfx10_tiling_surface, COND0, TYPE0,
> 0, idx);
>
> /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0,
> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_high, COND0, TYPE0,
> (addr >> 32), idx);
> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0,
> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_low, COND0, TYPE0,
> addr, idx);
>
> /* set output buffer data address */
> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET,
> - idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
> + if (jpeg_luma_base0_0) {
> + set_reg_jpeg(context, jpeg_luma_base0_0, COND0, TYPE0,
> + JPEG_DEC_LUMA_OFFSET, idx);
> + set_reg_jpeg(context, jpeg_chroma_base0_0, COND0, TYPE0,
> JPEG_DEC_CHROMA_OFFSET, idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0, idx);
> + } else {
> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
> + JPEG_DEC_LUMA_OFFSET, idx);
> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
> + JPEG_DEC_CHROMA_OFFSET, idx);
> + }
> + set_reg_jpeg(context, jpeg_tier_cntl2, COND0, 0, 0, idx);
>
> /* set output buffer read pointer */
> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0, idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
> + set_reg_jpeg(context, jpeg_outbuf_rptr, COND0, TYPE0, 0, idx);
> + set_reg_jpeg(context, jpeg_outbuf_cntl, COND0, TYPE0,
> ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)),
> idx);
>
> /* enable error interrupts */
> - set_reg_jpeg(context, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE, idx);
> + set_reg_jpeg(context, jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE, idx);
>
> /* start engine command */
> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE, idx);
> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0xE, idx);
>
> /* wait for job completion, wait for job JBSI fetch done */
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0,
> (JPEG_DEC_BSD_SIZE >> 2), idx);
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0,
> 0x01400200, idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF, idx);
> + set_reg_jpeg(context, jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF, idx);
>
> /* wait for job jpeg outbuf idle */
> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF,
> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF,
> idx);
> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001,
> + set_reg_jpeg(context, jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001,
> idx);
>
> /* stop engine */
> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4, idx);
> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0x4, idx);
> }
>
> static void
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940
2024-05-15 17:16 ` [PATCH i-g-t 1/2] " Kamil Konieczny
@ 2024-05-16 9:11 ` Sundararaju, Sathishkumar
0 siblings, 0 replies; 6+ messages in thread
From: Sundararaju, Sathishkumar @ 2024-05-16 9:11 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Sathishkumar S, Leo Liu
Hi Kamil,
On 5/15/2024 10:46 PM, Kamil Konieczny wrote:
> Hi Sathishkumar,
> On 2024-05-13 at 19:27:04 +0530, Sathishkumar S wrote:
>> update jpeg specific register offsets
> --^
>
> Start sentence with uppercase. No need for resend,
> this can be corrected at merge.
Noted, I will update this, thank you.
Regards,
Sathish
>
> Regards,
> Kamil
>
>> Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
>> Acked-by: Leo Liu <leo.liu@amd.com>
>> ---
>> tests/amdgpu/amd_jpeg_dec.c | 167 +++++++++++++++++++++++++++---------
>> 1 file changed, 127 insertions(+), 40 deletions(-)
>>
>> diff --git a/tests/amdgpu/amd_jpeg_dec.c b/tests/amdgpu/amd_jpeg_dec.c
>> index bb2a8e97e530..12f5bfcff556 100644
>> --- a/tests/amdgpu/amd_jpeg_dec.c
>> +++ b/tests/amdgpu/amd_jpeg_dec.c
>> @@ -53,6 +53,47 @@
>> #define vcnipUVD_JPEG_RB_RPTR 0x4003
>> #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d
>>
>> +#define vcnipUVD_JPEG_DEC_SOFT_RST_1 0x4051
>> +#define vcnipUVD_JPEG_PITCH_1 0x4043
>> +#define vcnipUVD_JPEG_UV_PITCH_1 0x4044
>> +#define vcnipJPEG_DEC_ADDR_MODE_1 0x404B
>> +#define vcnipUVD_JPEG_TIER_CNTL2_1 0x400E
>> +#define vcnipUVD_JPEG_OUTBUF_CNTL_1 0x4040
>> +#define vcnipUVD_JPEG_OUTBUF_WPTR_1 0x4041
>> +#define vcnipUVD_JPEG_OUTBUF_RPTR_1 0x4042
>> +#define vcnipUVD_JPEG_LUMA_BASE0_0 0x41C0
>> +#define vcnipUVD_JPEG_CHROMA_BASE0_0 0x41C1
>> +#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1 0x4048
>> +#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1 0x4049
>> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1 0x40B5
>> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1 0x40B4
>> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1 0x40B3
>> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1 0x40B2
>> +
>> +static uint32_t jpeg_dec_soft_rst;
>> +static uint32_t jrbc_ib_cond_rd_timer;
>> +static uint32_t jrbc_ib_ref_data;
>> +static uint32_t lmi_jpeg_read_64bit_bar_high;
>> +static uint32_t lmi_jpeg_read_64bit_bar_low;
>> +static uint32_t jpeg_rb_base;
>> +static uint32_t jpeg_rb_size;
>> +static uint32_t jpeg_rb_wptr;
>> +static uint32_t jpeg_pitch;
>> +static uint32_t jpeg_uv_pitch;
>> +static uint32_t dec_addr_mode;
>> +static uint32_t dec_y_gfx10_tiling_surface;
>> +static uint32_t dec_uv_gfx10_tiling_surface;
>> +static uint32_t lmi_jpeg_write_64bit_bar_high;
>> +static uint32_t lmi_jpeg_write_64bit_bar_low;
>> +static uint32_t jpeg_tier_cntl2;
>> +static uint32_t jpeg_outbuf_rptr;
>> +static uint32_t jpeg_outbuf_cntl;
>> +static uint32_t jpeg_int_en;
>> +static uint32_t jpeg_cntl;
>> +static uint32_t jpeg_rb_rptr;
>> +static uint32_t jpeg_outbuf_wptr;
>> +static uint32_t jpeg_luma_base0_0;
>> +static uint32_t jpeg_chroma_base0_0;
>>
>> #define RDECODE_PKT_REG_J(x) ((unsigned int)(x)&0x3FFFF)
>> #define RDECODE_PKT_RES_J(x) (((unsigned int)(x)&0x3F) << 18)
>> @@ -104,6 +145,50 @@ is_jpeg_tests_enable(amdgpu_device_handle device_handle,
>> else
>> return false;
>>
>> + jrbc_ib_cond_rd_timer = vcnipUVD_JRBC_IB_COND_RD_TIMER;
>> + jrbc_ib_ref_data = vcnipUVD_JRBC_IB_REF_DATA;
>> + jpeg_rb_base = vcnipUVD_JPEG_RB_BASE;
>> + jpeg_rb_size = vcnipUVD_JPEG_RB_SIZE;
>> + jpeg_rb_wptr = vcnipUVD_JPEG_RB_WPTR;
>> + jpeg_int_en = vcnipUVD_JPEG_INT_EN;
>> + jpeg_cntl = vcnipUVD_JPEG_CNTL;
>> + jpeg_rb_rptr = vcnipUVD_JPEG_RB_RPTR;
>> +
>> + if (context->family_id == AMDGPU_FAMILY_AI &&
>> + (context->chip_id - context->chip_rev) > 0x3c) { /* gfx940 */
>> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST_1;
>> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1;
>> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1;
>> + jpeg_pitch = vcnipUVD_JPEG_PITCH_1;
>> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH_1;
>> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE_1;
>> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1;
>> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1;
>> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1;
>> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1;
>> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2_1;
>> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL_1;
>> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR_1;
>> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR_1;
>> + jpeg_luma_base0_0 = vcnipUVD_JPEG_LUMA_BASE0_0;
>> + jpeg_chroma_base0_0 = vcnipUVD_JPEG_CHROMA_BASE0_0;
>> + } else {
>> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST;
>> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH;
>> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW;
>> + jpeg_pitch = vcnipUVD_JPEG_PITCH;
>> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH;
>> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE;
>> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE;
>> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE;
>> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH;
>> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW;
>> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2;
>> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL;
>> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR;
>> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR;
>> + }
>> +
>> return true;
>> }
>>
>> @@ -277,39 +362,34 @@ send_cmd_bitstream_direct(struct mmd_context *context, uint64_t addr,
>> {
>>
>> /* jpeg soft reset */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1, idx);
>> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 1, idx);
>>
>> /* ensuring the Reset is asserted in SCLK domain */
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
>> - 0x01400200, idx);
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
>> - (0x1 << 0x10), idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
>> - (0x1 << 0x10), idx);
>> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200, idx);
>> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10), idx);
>> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
>>
>> /* wait mem */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0, idx);
>> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 0, idx);
>>
>> /* ensuring the Reset is de-asserted in SCLK domain */
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10),
>> - idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3,
>> - (0x1 << 0x10), idx);
>> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10), idx);
>> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx);
>>
>> /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
>> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0,
>> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_high, COND0, TYPE0,
>> (addr >> 32), idx);
>> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0,
>> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_low, COND0, TYPE0,
>> addr, idx);
>>
>> /* set jpeg_rb_base */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0, idx);
>> + set_reg_jpeg(context, jpeg_rb_base, COND0, TYPE0, 0, idx);
>>
>> /* set jpeg_rb_base */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0, idx);
>> + set_reg_jpeg(context, jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0, idx);
>>
>> /* set jpeg_rb_wptr */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0,
>> + set_reg_jpeg(context, jpeg_rb_wptr, COND0, TYPE0,
>> (JPEG_DEC_BSD_SIZE >> 2), idx);
>> }
>>
>> @@ -319,59 +399,66 @@ send_cmd_target_direct(struct mmd_context *context, uint64_t addr,
>> uint32_t *idx)
>> {
>>
>> - set_reg_jpeg(context, vcnipUVD_JPEG_PITCH, COND0, TYPE0,
>> + set_reg_jpeg(context, jpeg_pitch, COND0, TYPE0,
>> (JPEG_DEC_DT_PITCH >> 4), idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0,
>> + set_reg_jpeg(context, jpeg_uv_pitch, COND0, TYPE0,
>> (JPEG_DEC_DT_PITCH >> 4), idx);
>>
>> - set_reg_jpeg(context, vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0, idx);
>> - set_reg_jpeg(context, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0,
>> + set_reg_jpeg(context, dec_addr_mode, COND0, TYPE0, 0, idx);
>> + set_reg_jpeg(context, dec_y_gfx10_tiling_surface, COND0, TYPE0,
>> 0, idx);
>> - set_reg_jpeg(context, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0,
>> + set_reg_jpeg(context, dec_uv_gfx10_tiling_surface, COND0, TYPE0,
>> 0, idx);
>>
>> /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
>> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0,
>> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_high, COND0, TYPE0,
>> (addr >> 32), idx);
>> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0,
>> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_low, COND0, TYPE0,
>> addr, idx);
>>
>> /* set output buffer data address */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET,
>> - idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
>> + if (jpeg_luma_base0_0) {
>> + set_reg_jpeg(context, jpeg_luma_base0_0, COND0, TYPE0,
>> + JPEG_DEC_LUMA_OFFSET, idx);
>> + set_reg_jpeg(context, jpeg_chroma_base0_0, COND0, TYPE0,
>> JPEG_DEC_CHROMA_OFFSET, idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0, idx);
>> + } else {
>> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx);
>> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
>> + JPEG_DEC_LUMA_OFFSET, idx);
>> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx);
>> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0,
>> + JPEG_DEC_CHROMA_OFFSET, idx);
>> + }
>> + set_reg_jpeg(context, jpeg_tier_cntl2, COND0, 0, 0, idx);
>>
>> /* set output buffer read pointer */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0, idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
>> + set_reg_jpeg(context, jpeg_outbuf_rptr, COND0, TYPE0, 0, idx);
>> + set_reg_jpeg(context, jpeg_outbuf_cntl, COND0, TYPE0,
>> ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)),
>> idx);
>>
>> /* enable error interrupts */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE, idx);
>> + set_reg_jpeg(context, jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE, idx);
>>
>> /* start engine command */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE, idx);
>> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0xE, idx);
>>
>> /* wait for job completion, wait for job JBSI fetch done */
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
>> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0,
>> (JPEG_DEC_BSD_SIZE >> 2), idx);
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0,
>> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0,
>> 0x01400200, idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF, idx);
>> + set_reg_jpeg(context, jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF, idx);
>>
>> /* wait for job jpeg outbuf idle */
>> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF,
>> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF,
>> idx);
>> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001,
>> + set_reg_jpeg(context, jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001,
>> idx);
>>
>> /* stop engine */
>> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4, idx);
>> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0x4, idx);
>> }
>>
>> static void
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-16 9:11 UTC | newest]
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2024-05-13 13:57 [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940 Sathishkumar S
2024-05-13 13:57 ` [PATCH i-g-t 2/2] tests/amdgpu: use 64x64 jpeg bitstream Sathishkumar S
2024-05-13 14:51 ` ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/2] tests/amdgpu: support jpeg test on gfx940 Patchwork
2024-05-15 17:14 ` Kamil Konieczny
2024-05-15 17:16 ` [PATCH i-g-t 1/2] " Kamil Konieczny
2024-05-16 9:11 ` Sundararaju, Sathishkumar
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