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From: "Thasleem, Mohammed" <mohammed.thasleem@intel.com>
To: Jeevan B <jeevan.b@intel.com>, <igt-dev@lists.freedesktop.org>
Cc: <animesh.manna@intel.com>,
	<dibin.moolakadan.subrahmanian@intel.com>,
	<ramanaidu.naladala@intel.com>, <jani.nikula@intel.com>
Subject: Re: [PATCH i-g-t v3 4/6] tests/kms_vrr: Add new test for DC3CO validation with LOBF
Date: Mon, 4 May 2026 12:58:38 +0530	[thread overview]
Message-ID: <7c8cb284-3db3-4aaf-974d-8ec6ca6c0948@intel.com> (raw)
In-Reply-To: <20260423173403.123706-5-jeevan.b@intel.com>


On 23-04-2026 11:04 pm, Jeevan B wrote:
> Add lobf-dc3co subtest to validate DC3CO entry during link-off
> between frames.
>
> v2: Fix the flow logic.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>   tests/kms_vrr.c | 33 +++++++++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>
> diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
> index 30bda3244..b98672520 100644
> --- a/tests/kms_vrr.c
> +++ b/tests/kms_vrr.c
> @@ -29,6 +29,7 @@
>    */
>   
>   #include "igt.h"
> +#include "igt_pm.h"
>   #include "igt_psr.h"
>   #include "i915/intel_drrs.h"
>   #include "sw_sync.h"
> @@ -80,6 +81,9 @@
>    *
>    * SUBTEST: negative-basic
>    * Description: Make sure that VRR should not be enabled on the Non-VRR panel.
> + *
> + * SUBTEST: lobf-dc3co
> + * Description: Test DC3CO entry during LOBF.
>    */
>   
>   #define NSECS_PER_SEC (1000000000ull)
> @@ -947,6 +951,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
>   	igt_assert_f(lobf_enabled, "LOBF not enabled\n");
>   }
>   
> +static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
> +			    igt_output_t *output, uint32_t flags)
> +{
> +	unsigned long dc3co_count_before, dc3co_count_after;
> +
> +	dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
> +						 IGT_INTEL_CHECK_DC3CO);
> +
> +	test_lobf(data, crtc, output, flags);
> +
> +	dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
> +						IGT_INTEL_CHECK_DC3CO);
> +
> +	igt_assert_f(dc3co_count_after > dc3co_count_before,
> +		     "DC3CO should be entered during link-off periods. "
> +		     "Before: %lu, After: %lu\n",
> +		     dc3co_count_before, dc3co_count_after);
> +}
> +
>   static void
>   test_cmrr(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
>   	  uint32_t flags)
> @@ -1242,6 +1265,16 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
>   
>   			run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
>   		}
> +
> +		igt_describe("Test to validate DC3CO entry during link-off between active "
> +			     "frames in non-PSR operation.");
--> Better to have message like: This test validates DC3CO entry during 
LOBF (Link-Off Between Frames) periods while VRR is active or similar.
With this changes,  LGTM:
Reviewed-by: Mohammed Thasleem <mohammed.thasleem@intel.com>

> +		igt_subtest_with_dynamic("lobf-dc3co") {
> +			igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
> +
> +			igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
> +
> +			run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF);
> +		}
>   	}
>   
>   	igt_fixture() {

  reply	other threads:[~2026-05-04  7:29 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-23 17:33 [PATCH i-g-t v3 0/6] Enable and Add new tests for DC3CO Jeevan B
2026-04-23 17:33 ` [PATCH i-g-t v3 1/6] tests: s/check_dc_counter/assert_dc_counter Jeevan B
2026-04-28  8:04   ` Thasleem, Mohammed
2026-04-23 17:33 ` [PATCH i-g-t v3 2/6] tests/intel/kms_pm_dc: Replace require with proper assertion Jeevan B
2026-04-23 17:34 ` [PATCH i-g-t v3 3/6] tests/intel/kms_pm_dc: Enable DC3CO test for PSR2/PR modes Jeevan B
2026-05-04  6:51   ` Thasleem, Mohammed
2026-04-23 17:34 ` [PATCH i-g-t v3 4/6] tests/kms_vrr: Add new test for DC3CO validation with LOBF Jeevan B
2026-05-04  7:28   ` Thasleem, Mohammed [this message]
2026-04-23 17:34 ` [PATCH i-g-t v3 5/6] tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation Jeevan B
2026-04-23 17:34 ` [PATCH i-g-t v3 6/6] RFC: tests/intel/kms_pm_dc: Add new test for DC3CO recovery after DC6 Jeevan B
2026-04-23 18:34 ` ✓ Xe.CI.BAT: success for Enable and Add new tests for DC3CO (rev4) Patchwork
2026-04-23 18:36 ` ✗ i915.CI.BAT: failure " Patchwork
2026-04-24  2:10 ` ✗ Xe.CI.FULL: " Patchwork

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