* [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream
@ 2023-12-15 15:50 Francois Dugast
2023-12-15 15:50 ` [PATCH v1 01/10] drm-uapi/xe: Align header with current kernel uAPI Francois Dugast
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw)
To: igt-dev
This is a combined submission of series which have been sent and
reviewed separately. It aligns with this kernel series:
https://patchwork.freedesktop.org/series/127878/
Bommu Krishnaiah (2):
drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence
structure
drm-uapi/xe: Don't wait on user_fence during exec queue reset
Francois Dugast (6):
drm-uapi/xe: Align header with current kernel uAPI
drm-uapi/xe: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY
drm-uapi/xe: Remove DRM_XE_UFENCE_WAIT_MASK_*
drm-uapi/xe: Remove PMU from Xe till uapi is finalized
drm-uapi/xe: Ensure every uapi struct has drm_xe prefix
drm-uapi/xe: Update header after documentation updates
Matthew Brost (1):
drm-uapi/xe: Remove sync binds
Rodrigo Vivi (1):
tests/intel/xe: Remove xe_uevent for now
benchmarks/gem_wsim.c | 3 +-
include/drm-uapi/xe_drm.h | 829 +++++++++++++++++----------
lib/igt_fb.c | 2 +-
lib/intel_batchbuffer.c | 7 +-
lib/intel_compute.c | 2 +-
lib/xe/xe_ioctl.c | 77 ++-
lib/xe/xe_ioctl.h | 22 +-
lib/xe/xe_query.c | 3 +-
lib/xe/xe_util.c | 4 +-
tests/intel/xe_access_counter.c | 2 +-
tests/intel/xe_ccs.c | 4 +-
tests/intel/xe_copy_basic.c | 2 +-
tests/intel/xe_create.c | 8 +-
tests/intel/xe_drm_fdinfo.c | 4 +-
tests/intel/xe_evict.c | 29 +-
tests/intel/xe_evict_ccs.c | 2 +-
tests/intel/xe_exec_balancer.c | 22 +-
tests/intel/xe_exec_basic.c | 6 +-
tests/intel/xe_exec_compute_mode.c | 25 +-
tests/intel/xe_exec_fault_mode.c | 26 +-
tests/intel/xe_exec_queue_property.c | 2 +-
tests/intel/xe_exec_reset.c | 19 +-
tests/intel/xe_exec_store.c | 6 +-
tests/intel/xe_exec_threads.c | 29 +-
tests/intel/xe_exercise_blt.c | 2 +-
tests/intel/xe_huc_copy.c | 2 +-
tests/intel/xe_intel_bb.c | 2 +-
tests/intel/xe_mmap.c | 2 +-
tests/intel/xe_noexec_ping_pong.c | 4 +-
tests/intel/xe_pat.c | 4 +-
tests/intel/xe_peer2peer.c | 4 +-
tests/intel/xe_pm.c | 2 +-
tests/intel/xe_spin_batch.c | 2 +-
tests/intel/xe_uevent.c | 129 -----
tests/intel/xe_vm.c | 24 +-
tests/intel/xe_waitfence.c | 122 +++-
tests/meson.build | 1 -
37 files changed, 789 insertions(+), 646 deletions(-)
delete mode 100644 tests/intel/xe_uevent.c
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v1 01/10] drm-uapi/xe: Align header with current kernel uAPI 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 02/10] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Francois Dugast ` (12 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi A few non functional changes from kernel commits below were missing: drm/xe/uapi: support pat_index selection with vm_bind drm/xe: Make DRM_XE_DEVICE_QUERY_ENGINES future proof Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 590f7b7af..313e555d2 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -129,7 +129,6 @@ struct xe_user_extension { * It is returned as part of the @drm_xe_engine, but it also is used as * the input of engine selection for both @drm_xe_exec_queue_create and * @drm_xe_query_engine_cycles - * */ struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0 @@ -143,9 +142,11 @@ struct drm_xe_engine_class_instance { */ #define DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC 5 #define DRM_XE_ENGINE_CLASS_VM_BIND_SYNC 6 + /** @engine_class: engine class id */ __u16 engine_class; - + /** @engine_instance: engine instance id */ __u16 engine_instance; + /** @gt_id: Unique ID of this GT within the PCI Device */ __u16 gt_id; /** @pad: MBZ */ __u16 pad; @@ -736,6 +737,12 @@ struct drm_xe_vm_bind_op { * * Note: For userptr and externally imported dma-buf the kernel expects * either 1WAY or 2WAY for the @pat_index. + * + * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions + * on the @pat_index. For such mappings there is no actual memory being + * mapped (the address in the PTE is invalid), so the various PAT memory + * attributes likely do not apply. Simply leaving as zero is one + * option (still a valid pat_index). */ __u16 pat_index; -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 02/10] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast 2023-12-15 15:50 ` [PATCH v1 01/10] drm-uapi/xe: Align header with current kernel uAPI Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 03/10] drm-uapi/xe: Don't wait on user_fence during exec queue reset Francois Dugast ` (11 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Bommu Krishnaiah, Rodrigo Vivi From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> remove the num_engines/instances members from drm_xe_wait_user_fence structure and add a exec_queue_id member Right now this is only checking if the engine list is sane and nothing else. In the end every operation with this IOCTL is a soft check. So, let's formalize that and only use this IOCTL to wait on the fence. exec_queue_id member will help to user space to get proper error code from kernel while in exec_queue reset v2: Also fix test invalid_flag (Francois Dugast) v3: Replace -ETIME with -EIO in test_compute_mode (Brian Welty) Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 17 +++++----------- lib/xe/xe_ioctl.c | 29 ++++++++++++--------------- lib/xe/xe_ioctl.h | 11 ++++------ tests/intel/xe_evict.c | 4 ++-- tests/intel/xe_exec_balancer.c | 15 +++++++------- tests/intel/xe_exec_compute_mode.c | 18 ++++++++--------- tests/intel/xe_exec_fault_mode.c | 21 +++++++++++--------- tests/intel/xe_exec_reset.c | 10 +++++----- tests/intel/xe_exec_threads.c | 15 +++++++------- tests/intel/xe_waitfence.c | 32 ++++++++++++++---------------- 10 files changed, 81 insertions(+), 91 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 313e555d2..fd06e4920 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -1031,8 +1031,7 @@ struct drm_xe_wait_user_fence { /** @op: wait operation (type of comparison) */ __u16 op; -#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */ -#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) +#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) /** @flags: wait flags */ __u16 flags; @@ -1065,17 +1064,11 @@ struct drm_xe_wait_user_fence { */ __s64 timeout; - /** - * @num_engines: number of engine instances to wait on, must be zero - * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set - */ - __u64 num_engines; + /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ + __u32 exec_queue_id; - /** - * @instances: user pointer to array of drm_xe_engine_class_instance to - * wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set - */ - __u64 instances; + /** @pad2: MBZ */ + __u32 pad2; /** @reserved: Reserved */ __u64 reserved[2]; diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index cdad3d7e2..8f466318d 100644 --- a/lib/xe/xe_ioctl.c +++ b/lib/xe/xe_ioctl.c @@ -481,7 +481,7 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr) * @fd: xe device fd * @addr: address of value to compare * @value: expected value (equal) in @address - * @eci: engine class instance + * @exec_queue: exec_queue id * @timeout: pointer to time to wait in nanoseconds * * Function compares @value with memory pointed by @addr until they are equal. @@ -490,17 +490,15 @@ void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr) * signalled. Returns 0 on success, -errno of ioctl on error. */ int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t *timeout) + uint32_t exec_queue, int64_t *timeout) { struct drm_xe_wait_user_fence wait = { .addr = to_user_pointer(addr), .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0, + .flags = 0, .value = value, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, - .num_engines = eci ? 1 :0, - .instances = eci ? to_user_pointer(eci) : 0, + .exec_queue_id = exec_queue, }; igt_assert(timeout); @@ -518,7 +516,7 @@ int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, * @fd: xe device fd * @addr: address of value to compare * @value: expected value (equal) in @address - * @eci: engine class instance + * @exec_queue: exec_queue id * @timeout: time to wait in nanoseconds * * Function compares @value with memory pointed by @addr until they are equal. @@ -527,10 +525,9 @@ int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, * Returns elapsed time in nanoseconds if user fence was signalled. */ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) + uint32_t exec_queue, int64_t timeout) { - igt_assert_eq(__xe_wait_ufence(fd, addr, value, eci, &timeout), 0); + igt_assert_eq(__xe_wait_ufence(fd, addr, value, exec_queue, &timeout), 0); return timeout; } @@ -539,8 +536,9 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, * @fd: xe device fd * @addr: address of value to compare * @value: expected value (equal) in @address - * @eci: engine class instance + * @exec_queue: exec_queue id * @timeout: absolute time when wait expire + * @flag: wait flag * * Function compares @value with memory pointed by @addr until they are equal. * Asserts that ioctl returned without error. @@ -548,18 +546,17 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, * Returns elapsed time in nanoseconds if user fence was signalled. */ int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) + uint32_t exec_queue, int64_t timeout, + uint16_t flag) { struct drm_xe_wait_user_fence wait = { .addr = to_user_pointer(addr), .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0, + .flags = flag, .value = value, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = timeout, - .num_engines = eci ? 1 : 0, - .instances = eci ? to_user_pointer(eci) : 0, + .exec_queue_id = exec_queue, }; struct timespec ts; diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index c8d46fb29..05480e40b 100644 --- a/lib/xe/xe_ioctl.h +++ b/lib/xe/xe_ioctl.h @@ -92,14 +92,11 @@ void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr, struct drm_xe_sync *sync, uint32_t num_syncs); void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr); int __xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t *timeout); + uint32_t exec_queue, int64_t *timeout); int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout); -int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout); + uint32_t exec_queue, int64_t timeout); +int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value, uint32_t + exec_queue, int64_t timeout, uint16_t flag); void xe_force_gt_reset(int fd, int gt); #endif /* XE_IOCTL_H */ diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index 89dc46fae..0ac83a3f7 100644 --- a/tests/intel/xe_evict.c +++ b/tests/intel/xe_evict.c @@ -317,7 +317,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, } #define TWENTY_SEC MS_TO_NS(20000) xe_wait_ufence(fd, &data[i].vm_sync, USER_FENCE_VALUE, - NULL, TWENTY_SEC); + bind_exec_queues[0], TWENTY_SEC); } sync[0].addr = addr + (char *)&data[i].exec_sync - (char *)data; @@ -352,7 +352,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, data = xe_bo_map(fd, __bo, ALIGN(sizeof(*data) * n_execs, 0x1000)); xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, TWENTY_SEC); + exec_queues[i % n_exec_queues], TWENTY_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } munmap(data, ALIGN(sizeof(*data) * n_execs, 0x1000)); diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c index 79ff65e89..5dded3ce4 100644 --- a/tests/intel/xe_exec_balancer.c +++ b/tests/intel/xe_exec_balancer.c @@ -483,7 +483,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, bo_size, sync, 1); #define ONE_SEC MS_TO_NS(1000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -514,7 +514,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + exec_queues[e], ONE_SEC); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, NULL, 0); @@ -529,7 +529,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + 0, ONE_SEC); data[0].vm_sync = 0; } @@ -542,7 +542,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + USER_FENCE_VALUE, exec_queues[e], + ONE_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -571,8 +572,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, j = flags & INVALIDATE && n_execs ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, - ONE_SEC); + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, + exec_queues[i % n_exec_queues], ONE_SEC); /* Wait for all execs to complete */ if (flags & INVALIDATE) @@ -580,7 +581,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC); for (i = (flags & INVALIDATE && n_execs) ? n_execs - 1 : 0; i < n_execs; i++) diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c index 7d3004d65..6123d2b29 100644 --- a/tests/intel/xe_exec_compute_mode.c +++ b/tests/intel/xe_exec_compute_mode.c @@ -171,8 +171,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, fence_timeout = igt_run_in_simulation() ? HUNDRED_SEC : ONE_SEC; - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, - fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, + bind_exec_queues[0], fence_timeout); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -198,7 +198,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], fence_timeout); xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, addr, bo_size, NULL, 0); @@ -214,7 +214,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + bind_exec_queues[e], fence_timeout); data[0].vm_sync = 0; } @@ -227,7 +227,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, + USER_FENCE_VALUE, exec_queues[e], fence_timeout); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { @@ -257,8 +257,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, j = flags & INVALIDATE ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, - fence_timeout); + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, + exec_queues[i % n_exec_queues], fence_timeout); /* Wait for all execs to complete */ if (flags & INVALIDATE) @@ -267,8 +267,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, - fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, + bind_exec_queues[0], fence_timeout); for (i = j; i < n_execs; i++) igt_assert_eq(data[i].data, 0xc0ffee); diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c index ee7cbb604..3dda33469 100644 --- a/tests/intel/xe_exec_fault_mode.c +++ b/tests/intel/xe_exec_fault_mode.c @@ -195,15 +195,16 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, } #define ONE_SEC MS_TO_NS(1000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, + bind_exec_queues[0], ONE_SEC); data[0].vm_sync = 0; if (flags & PREFETCH) { /* Should move to system memory */ xe_vm_prefetch_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1, 0); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, - ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, + bind_exec_queues[0], ONE_SEC); data[0].vm_sync = 0; } @@ -230,7 +231,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (flags & REBIND && i + 1 != n_execs) { xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + exec_queues[e], ONE_SEC); xe_vm_unbind_async(fd, vm, bind_exec_queues[e], 0, addr, bo_size, NULL, 0); @@ -246,7 +247,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, ONE_SEC); + bind_exec_queues[e], ONE_SEC); data[0].vm_sync = 0; } @@ -259,7 +260,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, * an invalidate. */ xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + USER_FENCE_VALUE, exec_queues[e], + ONE_SEC); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -289,14 +291,15 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, if (!(flags & INVALID_FAULT)) { j = flags & INVALIDATE ? n_execs - 1 : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, - USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, + exec_queues[i % n_exec_queues], ONE_SEC); } sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, ONE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, + bind_exec_queues[0], ONE_SEC); if (!(flags & INVALID_FAULT)) { for (i = j; i < n_execs; i++) diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c index 094b34896..9d0c7658b 100644 --- a/tests/intel/xe_exec_reset.c +++ b/tests/intel/xe_exec_reset.c @@ -564,7 +564,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1); #define THREE_SEC MS_TO_NS(3000) - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -621,17 +621,17 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, int err; err = __xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, - NULL, &timeout); + exec_queues[i % n_exec_queues], &timeout); if (flags & GT_RESET) - /* exec races with reset: may timeout or complete */ - igt_assert(err == -ETIME || !err); + /* exec races with reset: may return -EIO or complete */ + igt_assert(err == -EIO || !err); else igt_assert_eq(err, 0); } sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, THREE_SEC); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, THREE_SEC); if (!(flags & GT_RESET)) { for (i = 1; i < n_execs; i++) diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index fcb926698..ca2dd421e 100644 --- a/tests/intel/xe_exec_threads.c +++ b/tests/intel/xe_exec_threads.c @@ -331,7 +331,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, fence_timeout = igt_run_in_simulation() ? THIRTY_SEC : THREE_SEC; - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); data[0].vm_sync = 0; for (i = 0; i < n_execs; i++) { @@ -359,7 +359,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, for (j = i - 0x20; j <= i; ++j) xe_wait_ufence(fd, &data[j].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], fence_timeout); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, NULL, 0); @@ -374,7 +374,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, addr, bo_size, sync, 1); xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + 0, fence_timeout); data[0].vm_sync = 0; } @@ -389,7 +389,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, for (j = i == 0x20 ? 0 : i - 0x1f; j <= i; ++j) xe_wait_ufence(fd, &data[j].exec_sync, USER_FENCE_VALUE, - NULL, fence_timeout); + exec_queues[e], + fence_timeout); igt_assert_eq(data[i].data, 0xc0ffee); } else if (i * 2 != n_execs) { /* @@ -421,8 +422,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, j = flags & INVALIDATE ? (flags & RACE ? n_execs / 2 + 1 : n_execs - 1) : 0; for (i = j; i < n_execs; i++) - xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, NULL, - fence_timeout); + xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, + exec_queues[i % n_exec_queues], fence_timeout); /* Wait for all execs to complete */ if (flags & INVALIDATE) @@ -430,7 +431,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, sync[0].addr = to_user_pointer(&data[0].vm_sync); xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1); - xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, NULL, fence_timeout); + xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, fence_timeout); for (i = j; i < n_execs; i++) igt_assert_eq(data[i].data, 0xc0ffee); diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index 3be987954..d7e2008c5 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -37,22 +37,20 @@ static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset, } static int64_t wait_with_eci_abstime(int fd, uint64_t *addr, uint64_t value, - struct drm_xe_engine_class_instance *eci, - int64_t timeout) + uint32_t exec_queue, int64_t timeout, + uint16_t flag) { struct drm_xe_wait_user_fence wait = { .addr = to_user_pointer(addr), .op = DRM_XE_UFENCE_WAIT_OP_EQ, - .flags = !eci ? 0 : DRM_XE_UFENCE_WAIT_FLAG_ABSTIME, + .flags = flag, .value = value, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = timeout, - .num_engines = eci ? 1 : 0, - .instances = eci ? to_user_pointer(eci) : 0, + .exec_queue_id = exec_queue, }; struct timespec ts; - igt_assert(eci); igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait), 0); igt_assert_eq(clock_gettime(CLOCK_MONOTONIC, &ts), 0); @@ -82,7 +80,7 @@ enum waittype { static void waitfence(int fd, enum waittype wt) { - struct drm_xe_engine *engine = NULL; + uint32_t exec_queue; struct timespec ts; int64_t current, signalled; uint32_t bo_1; @@ -111,15 +109,17 @@ waitfence(int fd, enum waittype wt) do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7); if (wt == RELTIME) { - timeout = xe_wait_ufence(fd, &wait_fence, 7, NULL, MS_TO_NS(10)); + timeout = xe_wait_ufence(fd, &wait_fence, 7, 0, MS_TO_NS(10)); igt_debug("wait type: RELTIME - timeout: %ld, timeout left: %ld\n", MS_TO_NS(10), timeout); } else if (wt == ENGINE) { - engine = xe_engine(fd, 1); + exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); clock_gettime(CLOCK_MONOTONIC, &ts); current = ts.tv_sec * 1e9 + ts.tv_nsec; timeout = current + MS_TO_NS(10); - signalled = wait_with_eci_abstime(fd, &wait_fence, 7, &engine->instance, timeout); + signalled = wait_with_eci_abstime(fd, &wait_fence, 7, + exec_queue, timeout, + DRM_XE_UFENCE_WAIT_FLAG_ABSTIME); igt_debug("wait type: ENGINE ABSTIME - timeout: %" PRId64 ", signalled: %" PRId64 ", elapsed: %" PRId64 "\n", @@ -128,7 +128,8 @@ waitfence(int fd, enum waittype wt) clock_gettime(CLOCK_MONOTONIC, &ts); current = ts.tv_sec * 1e9 + ts.tv_nsec; timeout = current + MS_TO_NS(10); - signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, NULL, timeout); + signalled = xe_wait_ufence_abstime(fd, &wait_fence, 7, 0, + timeout, 0); igt_debug("wait type: ABSTIME - timeout: %" PRId64 ", signalled: %" PRId64 ", elapsed: %" PRId64 "\n", @@ -166,8 +167,7 @@ invalid_flag(int fd) .value = 1, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = -1, - .num_engines = 0, - .instances = 0, + .exec_queue_id = 0, }; uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); @@ -191,8 +191,7 @@ invalid_ops(int fd) .value = 1, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = 1, - .num_engines = 0, - .instances = 0, + .exec_queue_id = 0, }; uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); @@ -216,8 +215,7 @@ invalid_engine(int fd) .value = 1, .mask = DRM_XE_UFENCE_WAIT_MASK_U64, .timeout = -1, - .num_engines = 1, - .instances = 0, + .exec_queue_id = 0, }; uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 03/10] drm-uapi/xe: Don't wait on user_fence during exec queue reset 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast 2023-12-15 15:50 ` [PATCH v1 01/10] drm-uapi/xe: Align header with current kernel uAPI Francois Dugast 2023-12-15 15:50 ` [PATCH v1 02/10] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 04/10] drm-uapi/xe: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY Francois Dugast ` (10 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Bommu Krishnaiah, Rodrigo Vivi From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Don't wait till timeout on user fence when exec_queue reset is detected and return return proper error code v2: s/drm_xe_wait_user_fence1/drm_xe_wait_user_fence/ (Francois Dugast) Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> --- tests/intel/xe_waitfence.c | 82 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index d7e2008c5..4421e571a 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -153,6 +153,9 @@ waitfence(int fd, enum waittype wt) * * SUBTEST: invalid-engine * Description: Check query with invalid engine info returns expected error code + * + * SUBTEST: exec_queue-reset-wait + * Description: Don’t wait till timeout on user fence when exec_queue reset is detected and return return proper error */ static void @@ -227,6 +230,82 @@ invalid_engine(int fd) do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EFAULT); } +static void +exec_queue_reset_wait(int fd) +{ + uint32_t bo, b; + uint64_t batch_offset; + uint64_t batch_addr; + uint64_t sdi_offset; + uint64_t sdi_addr; + uint64_t addr = 0x1a0000; + + struct { + uint32_t batch[16]; + uint64_t pad; + uint64_t vm_sync; + uint64_t exec_sync; + uint32_t data; + } *data; + +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + struct drm_xe_sync sync[1] = { + { .flags = DRM_XE_SYNC_TYPE_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL, + .timeline_value = USER_FENCE_VALUE }, + }; + + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(sync), + }; + + uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); + struct drm_xe_wait_user_fence wait = { + .op = DRM_XE_UFENCE_WAIT_OP_EQ, + .flags = 0, + .value = 0xc0ffee, + .mask = DRM_XE_UFENCE_WAIT_MASK_U64, + .timeout = -1, + .exec_queue_id = exec_queue, + }; + + bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); + data = xe_bo_map(fd, bo, 0x40000); + + batch_offset = (char *)&data[0].batch - (char *)data; + batch_addr = addr + batch_offset; + sdi_offset = (char *)&data[0].data - (char *)data; + sdi_addr = addr + sdi_offset; + + b = 0; + data[0].batch[b++] = MI_STORE_DWORD_IMM_GEN4; + data[0].batch[b++] = sdi_addr; + data[0].batch[b++] = sdi_addr >> 32; + data[0].batch[b++] = 0xc0ffee; + data[0].batch[b++] = MI_BATCH_BUFFER_END; + igt_assert(b <= ARRAY_SIZE(data[0].batch)); + + wait.addr = to_user_pointer(&data[0].exec_sync); + exec.exec_queue_id = exec_queue; + exec.address = batch_addr; + + xe_exec(fd, &exec); + + /** + * Don't do the GPU mapping(vm_bind) for object, so that exec_queue + * reset will happen and xe_wait_ufence will return EIO not ETIME + */ + do_ioctl_err(fd, DRM_IOCTL_XE_WAIT_USER_FENCE, &wait, EIO); + + xe_exec_queue_destroy(fd, exec_queue); + + if (bo) { + munmap(data, 0x40000); + gem_close(fd, bo); + } +} igt_main { @@ -253,6 +332,9 @@ igt_main igt_subtest("invalid-engine") invalid_engine(fd); + igt_subtest("exec_queue-reset-wait") + exec_queue_reset_wait(fd); + igt_fixture drm_close_driver(fd); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 04/10] drm-uapi/xe: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (2 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 03/10] drm-uapi/xe: Don't wait on user_fence during exec queue reset Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 05/10] drm-uapi/xe: Remove DRM_XE_UFENCE_WAIT_MASK_* Francois Dugast ` (9 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi Align with commit ("drm/xe/uapi: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY") Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index fd06e4920..b543207bf 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -118,7 +118,6 @@ struct xe_user_extension { #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) -#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 05/10] drm-uapi/xe: Remove DRM_XE_UFENCE_WAIT_MASK_* 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (3 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 04/10] drm-uapi/xe: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 06/10] drm-uapi/xe: Remove PMU from Xe till uapi is finalized Francois Dugast ` (8 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi Align with commit ("drm/xe/uapi: Remove DRM_XE_UFENCE_WAIT_MASK_*") Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 12 +++++++----- lib/xe/xe_ioctl.h | 2 ++ 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index b543207bf..8f09e9681 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -1040,11 +1040,13 @@ struct drm_xe_wait_user_fence { /** @value: compare value */ __u64 value; -#define DRM_XE_UFENCE_WAIT_MASK_U8 0xffu -#define DRM_XE_UFENCE_WAIT_MASK_U16 0xffffu -#define DRM_XE_UFENCE_WAIT_MASK_U32 0xffffffffu -#define DRM_XE_UFENCE_WAIT_MASK_U64 0xffffffffffffffffu - /** @mask: comparison mask */ + /** + * @mask: comparison mask, values can be for example: + * - 0xffu for u8 + * - 0xffffu for u16 + * - 0xffffffffu for u32 + * - 0xffffffffffffffffu for u64 + */ __u64 mask; /** diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index 05480e40b..7dcc20e57 100644 --- a/lib/xe/xe_ioctl.h +++ b/lib/xe/xe_ioctl.h @@ -15,6 +15,8 @@ #include <stdint.h> #include <xe_drm.h> +#define DRM_XE_UFENCE_WAIT_MASK_U64 0xffffffffffffffffu + uint32_t xe_cs_prefetch_size(int fd); uint32_t xe_vm_create(int fd, uint32_t flags, uint64_t ext); int __xe_vm_bind(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo, -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 06/10] drm-uapi/xe: Remove PMU from Xe till uapi is finalized 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (4 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 05/10] drm-uapi/xe: Remove DRM_XE_UFENCE_WAIT_MASK_* Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 07/10] drm-uapi/xe: Ensure every uapi struct has drm_xe prefix Francois Dugast ` (7 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi Align with commit ("drm/xe/pmu: Remove PMU from Xe till uapi is finalized") Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 40 --------------------------------------- 1 file changed, 40 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 8f09e9681..b1839df48 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -1074,46 +1074,6 @@ struct drm_xe_wait_user_fence { /** @reserved: Reserved */ __u64 reserved[2]; }; - -/** - * DOC: XE PMU event config IDs - * - * Check 'man perf_event_open' to use the ID's DRM_XE_PMU_XXXX listed in xe_drm.h - * in 'struct perf_event_attr' as part of perf_event_open syscall to read a - * particular event. - * - * For example to open the DRMXE_PMU_RENDER_GROUP_BUSY(0): - * - * .. code-block:: C - * - * struct perf_event_attr attr; - * long long count; - * int cpu = 0; - * int fd; - * - * memset(&attr, 0, sizeof(struct perf_event_attr)); - * attr.type = type; // eg: /sys/bus/event_source/devices/xe_0000_56_00.0/type - * attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED; - * attr.use_clockid = 1; - * attr.clockid = CLOCK_MONOTONIC; - * attr.config = DRM_XE_PMU_RENDER_GROUP_BUSY(0); - * - * fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0); - */ - -/* - * Top bits of every counter are GT id. - */ -#define __DRM_XE_PMU_GT_SHIFT (56) - -#define ___DRM_XE_PMU_OTHER(gt, x) \ - (((__u64)(x)) | ((__u64)(gt) << __DRM_XE_PMU_GT_SHIFT)) - -#define DRM_XE_PMU_RENDER_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 0) -#define DRM_XE_PMU_COPY_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 1) -#define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 2) -#define DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 3) - #if defined(__cplusplus) } #endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 07/10] drm-uapi/xe: Ensure every uapi struct has drm_xe prefix 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (5 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 06/10] drm-uapi/xe: Remove PMU from Xe till uapi is finalized Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 08/10] drm-uapi/xe: Remove sync binds Francois Dugast ` (6 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi Align with commit ("drm/xe/uapi: Ensure every uapi struct has drm_xe prefix") Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 18 +++++++++--------- tests/intel/xe_mmap.c | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index b1839df48..9609194c1 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -27,7 +27,7 @@ extern "C" { #define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" /** - * struct xe_user_extension - Base class for defining a chain of extensions + * struct drm_xe_user_extension - Base class for defining a chain of extensions * * Many interfaces need to grow over time. In most cases we can simply * extend the struct and have userspace pass in more data. Another option, @@ -45,29 +45,29 @@ extern "C" { * * .. code-block:: C * - * struct xe_user_extension ext3 { + * struct drm_xe_user_extension ext3 { * .next_extension = 0, // end * .name = ..., * }; - * struct xe_user_extension ext2 { + * struct drm_xe_user_extension ext2 { * .next_extension = (uintptr_t)&ext3, * .name = ..., * }; - * struct xe_user_extension ext1 { + * struct drm_xe_user_extension ext1 { * .next_extension = (uintptr_t)&ext2, * .name = ..., * }; * - * Typically the struct xe_user_extension would be embedded in some uAPI + * Typically the struct drm_xe_user_extension would be embedded in some uAPI * struct, and in this case we would feed it the head of the chain(i.e ext1), * which would then apply all of the above extensions. * */ -struct xe_user_extension { +struct drm_xe_user_extension { /** * @next_extension: * - * Pointer to the next struct xe_user_extension, or zero if the end. + * Pointer to the next struct drm_xe_user_extension, or zero if the end. */ __u64 next_extension; @@ -78,7 +78,7 @@ struct xe_user_extension { * * Also note that the name space for this is not global for the whole * driver, but rather its scope/meaning is limited to the specific piece - * of uAPI which has embedded the struct xe_user_extension. + * of uAPI which has embedded the struct drm_xe_user_extension. */ __u32 name; @@ -625,7 +625,7 @@ struct drm_xe_gem_mmap_offset { /** struct drm_xe_ext_set_property - XE set property extension */ struct drm_xe_ext_set_property { /** @base: base user extension */ - struct xe_user_extension base; + struct drm_xe_user_extension base; /** @property: property to set */ __u32 property; diff --git a/tests/intel/xe_mmap.c b/tests/intel/xe_mmap.c index 63fdf46a8..e96192d23 100644 --- a/tests/intel/xe_mmap.c +++ b/tests/intel/xe_mmap.c @@ -92,7 +92,7 @@ static void test_bad_flags(int fd) static void test_bad_extensions(int fd) { uint64_t size = xe_get_default_alignment(fd); - struct xe_user_extension ext; + struct drm_xe_user_extension ext; struct drm_xe_gem_mmap_offset mmo = { .handle = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0), -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 08/10] drm-uapi/xe: Remove sync binds 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (6 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 07/10] drm-uapi/xe: Ensure every uapi struct has drm_xe prefix Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 09/10] drm-uapi/xe: Update header after documentation updates Francois Dugast ` (5 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi From: Matthew Brost <matthew.brost@intel.com> Align with commit ("drm/xe/uapi: Remove sync binds") v2: Fix exec_queue_reset_wait in xe_waitfence.c (Francois Dugast) Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- benchmarks/gem_wsim.c | 3 +- include/drm-uapi/xe_drm.h | 11 +++---- lib/igt_fb.c | 2 +- lib/intel_batchbuffer.c | 7 ++-- lib/intel_compute.c | 2 +- lib/xe/xe_ioctl.c | 48 ++++++++++++---------------- lib/xe/xe_ioctl.h | 9 +----- lib/xe/xe_query.c | 3 +- lib/xe/xe_util.c | 4 +-- tests/intel/xe_access_counter.c | 2 +- tests/intel/xe_ccs.c | 4 +-- tests/intel/xe_copy_basic.c | 2 +- tests/intel/xe_create.c | 8 ++--- tests/intel/xe_drm_fdinfo.c | 4 +-- tests/intel/xe_evict.c | 25 ++++++--------- tests/intel/xe_evict_ccs.c | 2 +- tests/intel/xe_exec_balancer.c | 7 ++-- tests/intel/xe_exec_basic.c | 6 ++-- tests/intel/xe_exec_compute_mode.c | 7 ++-- tests/intel/xe_exec_fault_mode.c | 5 ++- tests/intel/xe_exec_queue_property.c | 2 +- tests/intel/xe_exec_reset.c | 9 +++--- tests/intel/xe_exec_store.c | 6 ++-- tests/intel/xe_exec_threads.c | 14 +++----- tests/intel/xe_exercise_blt.c | 2 +- tests/intel/xe_huc_copy.c | 2 +- tests/intel/xe_intel_bb.c | 2 +- tests/intel/xe_noexec_ping_pong.c | 4 +-- tests/intel/xe_pat.c | 4 +-- tests/intel/xe_peer2peer.c | 4 +-- tests/intel/xe_pm.c | 2 +- tests/intel/xe_spin_batch.c | 2 +- tests/intel/xe_vm.c | 24 +++++++------- tests/intel/xe_waitfence.c | 10 +++--- 34 files changed, 105 insertions(+), 143 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 30673da8f..955b6799e 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -2037,8 +2037,7 @@ static void xe_vm_create_(struct xe_vm *vm) uint32_t flags = 0; if (vm->compute_mode) - flags |= DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE; + flags |= DRM_XE_VM_CREATE_FLAG_LR_MODE; vm->id = xe_vm_create(fd, flags, 0); } diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 9609194c1..c39d78a39 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -139,8 +139,7 @@ struct drm_xe_engine_class_instance { * Kernel only classes (not actual hardware engine class). Used for * creating ordered queues of VM bind operations. */ -#define DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC 5 -#define DRM_XE_ENGINE_CLASS_VM_BIND_SYNC 6 +#define DRM_XE_ENGINE_CLASS_VM_BIND 5 /** @engine_class: engine class id */ __u16 engine_class; /** @engine_instance: engine instance id */ @@ -660,7 +659,6 @@ struct drm_xe_vm_create { * still enable recoverable pagefaults if supported by the device. */ #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) -#define DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT (1 << 2) /* * DRM_XE_VM_CREATE_FLAG_FAULT_MODE requires also * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated @@ -668,7 +666,7 @@ struct drm_xe_vm_create { * The xe driver internally uses recoverable pagefaults to implement * this. */ -#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 3) +#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) /** @flags: Flags */ __u32 flags; @@ -776,12 +774,11 @@ struct drm_xe_vm_bind_op { __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) -#define DRM_XE_VM_BIND_FLAG_ASYNC (1 << 1) /* * Valid on a faulting VM only, do the MAP operation immediately rather * than deferring the MAP to the page fault handler. */ -#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 2) +#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) /* * When the NULL flag is set, the page tables are setup with a special * bit which indicates writes are dropped and all reads return zero. In @@ -789,7 +786,7 @@ struct drm_xe_vm_bind_op { * operations, the BO handle MBZ, and the BO offset MBZ. This flag is * intended to implement VK sparse bindings. */ -#define DRM_XE_VM_BIND_FLAG_NULL (1 << 3) +#define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) /** @flags: Bind flags */ __u32 flags; diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 0446cefc9..683eb176b 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -2897,7 +2897,7 @@ static void blitcopy(const struct igt_fb *dst_fb, &bb_size, mem_region) == 0); } else if (is_xe) { - vm = xe_vm_create(dst_fb->fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(dst_fb->fd, 0, 0); exec_queue = xe_exec_queue_create(dst_fb->fd, vm, &inst, 0); xe_ctx = intel_ctx_xe(dst_fb->fd, vm, exec_queue, 0, 0, 0); mem_region = vram_if_possible(dst_fb->fd, 0); diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 1268ac8f0..ccab55cec 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -967,7 +967,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg, if (!vm) { igt_assert_f(!ctx, "No vm provided for engine"); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); } ibb->uses_full_ppgtt = true; @@ -1347,9 +1347,8 @@ static void __unbind_xe_objects(struct intel_bb *ibb) if (ibb->num_objects > 1) { struct drm_xe_vm_bind_op *bind_ops; uint32_t op = DRM_XE_VM_BIND_OP_UNMAP; - uint32_t flags = DRM_XE_VM_BIND_FLAG_ASYNC; - bind_ops = xe_alloc_bind_ops(ibb, op, flags, 0); + bind_ops = xe_alloc_bind_ops(ibb, op, 0, 0); xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops, ibb->num_objects, syncs, 2); free(bind_ops); @@ -2395,7 +2394,7 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync) syncs[0].handle = syncobj_create(ibb->fd, 0); if (ibb->num_objects > 1) { - bind_ops = xe_alloc_bind_ops(ibb, DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC, 0); + bind_ops = xe_alloc_bind_ops(ibb, DRM_XE_VM_BIND_OP_MAP, 0, 0); xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops, ibb->num_objects, syncs, 1); free(bind_ops); diff --git a/lib/intel_compute.c b/lib/intel_compute.c index e657ae915..bf6a91109 100644 --- a/lib/intel_compute.c +++ b/lib/intel_compute.c @@ -73,7 +73,7 @@ static void bo_execenv_create(int fd, struct bo_execenv *execenv, execenv->driver = get_intel_driver(fd); if (execenv->driver == INTEL_DRIVER_XE) { - execenv->vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + execenv->vm = xe_vm_create(fd, 0, 0); if (eci) { execenv->exec_queue = xe_exec_queue_create(fd, execenv->vm, diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index 8f466318d..39605a019 100644 --- a/lib/xe/xe_ioctl.c +++ b/lib/xe/xe_ioctl.c @@ -68,7 +68,7 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t exec_queue, uint32_t num_syncs) { __xe_vm_bind_assert(fd, vm, exec_queue, bo, 0, 0, 0, - DRM_XE_VM_BIND_OP_UNMAP_ALL, DRM_XE_VM_BIND_FLAG_ASYNC, + DRM_XE_VM_BIND_OP_UNMAP_ALL, 0, sync, num_syncs, 0, 0); } @@ -129,29 +129,13 @@ void __xe_vm_bind_assert(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo, DEFAULT_PAT_INDEX, ext), 0); } -void xe_vm_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset, - uint64_t addr, uint64_t size, - struct drm_xe_sync *sync, uint32_t num_syncs) -{ - __xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size, - DRM_XE_VM_BIND_OP_MAP, 0, sync, num_syncs, 0, 0); -} - -void xe_vm_unbind(int fd, uint32_t vm, uint64_t offset, - uint64_t addr, uint64_t size, - struct drm_xe_sync *sync, uint32_t num_syncs) -{ - __xe_vm_bind_assert(fd, vm, 0, 0, offset, addr, size, - DRM_XE_VM_BIND_OP_UNMAP, 0, sync, num_syncs, 0, 0); -} - void xe_vm_prefetch_async(int fd, uint32_t vm, uint32_t exec_queue, uint64_t offset, uint64_t addr, uint64_t size, struct drm_xe_sync *sync, uint32_t num_syncs, uint32_t region) { __xe_vm_bind_assert(fd, vm, exec_queue, 0, offset, addr, size, - DRM_XE_VM_BIND_OP_PREFETCH, DRM_XE_VM_BIND_FLAG_ASYNC, + DRM_XE_VM_BIND_OP_PREFETCH, 0, sync, num_syncs, region, 0); } @@ -160,7 +144,7 @@ void xe_vm_bind_async(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo, struct drm_xe_sync *sync, uint32_t num_syncs) { __xe_vm_bind_assert(fd, vm, exec_queue, bo, offset, addr, size, - DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC, sync, + DRM_XE_VM_BIND_OP_MAP, 0, sync, num_syncs, 0, 0); } @@ -170,7 +154,7 @@ void xe_vm_bind_async_flags(int fd, uint32_t vm, uint32_t exec_queue, uint32_t b uint32_t flags) { __xe_vm_bind_assert(fd, vm, exec_queue, bo, offset, addr, size, - DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC | flags, + DRM_XE_VM_BIND_OP_MAP, flags, sync, num_syncs, 0, 0); } @@ -179,7 +163,7 @@ void xe_vm_bind_userptr_async(int fd, uint32_t vm, uint32_t exec_queue, struct drm_xe_sync *sync, uint32_t num_syncs) { __xe_vm_bind_assert(fd, vm, exec_queue, 0, userptr, addr, size, - DRM_XE_VM_BIND_OP_MAP_USERPTR, DRM_XE_VM_BIND_FLAG_ASYNC, + DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, sync, num_syncs, 0, 0); } @@ -189,8 +173,8 @@ void xe_vm_bind_userptr_async_flags(int fd, uint32_t vm, uint32_t exec_queue, uint32_t num_syncs, uint32_t flags) { __xe_vm_bind_assert(fd, vm, exec_queue, 0, userptr, addr, size, - DRM_XE_VM_BIND_OP_MAP_USERPTR, DRM_XE_VM_BIND_FLAG_ASYNC | - flags, sync, num_syncs, 0, 0); + DRM_XE_VM_BIND_OP_MAP_USERPTR, flags, + sync, num_syncs, 0, 0); } void xe_vm_unbind_async(int fd, uint32_t vm, uint32_t exec_queue, @@ -198,15 +182,24 @@ void xe_vm_unbind_async(int fd, uint32_t vm, uint32_t exec_queue, struct drm_xe_sync *sync, uint32_t num_syncs) { __xe_vm_bind_assert(fd, vm, exec_queue, 0, offset, addr, size, - DRM_XE_VM_BIND_OP_UNMAP, DRM_XE_VM_BIND_FLAG_ASYNC, sync, + DRM_XE_VM_BIND_OP_UNMAP, 0, sync, num_syncs, 0, 0); } static void __xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset, uint64_t addr, uint64_t size, uint32_t op) { - __xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size, op, 0, NULL, 0, + struct drm_xe_sync sync = { + .type = DRM_XE_SYNC_TYPE_SYNCOBJ, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + .handle = syncobj_create(fd, 0), + }; + + __xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size, op, 0, &sync, 1, 0, 0); + + igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL)); + syncobj_destroy(fd, sync.handle); } void xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset, @@ -315,11 +308,10 @@ uint32_t xe_bo_create_caching(int fd, uint32_t vm, uint64_t size, uint32_t place return handle; } -uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext, bool async) +uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext) { struct drm_xe_engine_class_instance instance = { - .engine_class = async ? DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC : - DRM_XE_ENGINE_CLASS_VM_BIND_SYNC, + .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND, }; struct drm_xe_exec_queue_create create = { .extensions = ext, diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index 7dcc20e57..8a92073b0 100644 --- a/lib/xe/xe_ioctl.h +++ b/lib/xe/xe_ioctl.h @@ -27,12 +27,6 @@ void __xe_vm_bind_assert(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo, uint64_t offset, uint64_t addr, uint64_t size, uint32_t op, uint32_t flags, struct drm_xe_sync *sync, uint32_t num_syncs, uint32_t prefetch_region, uint64_t ext); -void xe_vm_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset, - uint64_t addr, uint64_t size, - struct drm_xe_sync *sync, uint32_t num_syncs); -void xe_vm_unbind(int fd, uint32_t vm, uint64_t offset, - uint64_t addr, uint64_t size, - struct drm_xe_sync *sync, uint32_t num_syncs); void xe_vm_prefetch_async(int fd, uint32_t vm, uint32_t exec_queue, uint64_t offset, uint64_t addr, uint64_t size, struct drm_xe_sync *sync, uint32_t num_syncs, @@ -81,8 +75,7 @@ int __xe_exec_queue_create(int fd, uint32_t vm, uint32_t xe_exec_queue_create(int fd, uint32_t vm, struct drm_xe_engine_class_instance *instance, uint64_t ext); -uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext, - bool async); +uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext); uint32_t xe_exec_queue_create_class(int fd, uint32_t vm, uint16_t class); void xe_exec_queue_destroy(int fd, uint32_t exec_queue); uint64_t xe_bo_mmap_offset(int fd, uint32_t bo); diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c index 51d54753f..729fba6b1 100644 --- a/lib/xe/xe_query.c +++ b/lib/xe/xe_query.c @@ -311,8 +311,7 @@ bool xe_supports_faults(int fd) bool supports_faults; struct drm_xe_vm_create create = { - .flags = DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE | + .flags = DRM_XE_VM_CREATE_FLAG_LR_MODE | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, }; diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c index ba8eece71..e4c97c3a6 100644 --- a/lib/xe/xe_util.c +++ b/lib/xe/xe_util.c @@ -118,7 +118,7 @@ static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(int xe, { struct drm_xe_vm_bind_op *bind_ops, *ops; struct xe_object *obj; - uint32_t num_objects = 0, i = 0, op, flags; + uint32_t num_objects = 0, i = 0, op, flags = 0; igt_list_for_each_entry(obj, obj_list, link) num_objects++; @@ -137,11 +137,9 @@ static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(int xe, if (obj->bind_op == XE_OBJECT_BIND) { op = DRM_XE_VM_BIND_OP_MAP; - flags = DRM_XE_VM_BIND_FLAG_ASYNC; ops->obj = obj->handle; } else { op = DRM_XE_VM_BIND_OP_UNMAP; - flags = DRM_XE_VM_BIND_FLAG_ASYNC; } ops->op = op; diff --git a/tests/intel/xe_access_counter.c b/tests/intel/xe_access_counter.c index 8966bfc9c..91367f560 100644 --- a/tests/intel/xe_access_counter.c +++ b/tests/intel/xe_access_counter.c @@ -39,7 +39,7 @@ igt_main igt_subtest("invalid-param") { struct drm_xe_engine_class_instance instance = { - .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND_SYNC, + .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND, }; int ret; diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c index 77d3020bc..e9df5c2ef 100644 --- a/tests/intel/xe_ccs.c +++ b/tests/intel/xe_ccs.c @@ -345,7 +345,7 @@ static void block_copy(int xe, uint32_t vm, exec_queue; if (config->new_ctx) { - vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(xe, 0, 0); exec_queue = xe_exec_queue_create(xe, vm, &inst, 0); surf_ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0); surf_ahnd = intel_allocator_open(xe, surf_ctx->vm, @@ -553,7 +553,7 @@ static void block_copy_test(int xe, copyfns[copy_function].suffix) { uint32_t sync_bind, sync_out; - vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(xe, 0, 0); exec_queue = xe_exec_queue_create(xe, vm, &inst, 0); sync_bind = syncobj_create(xe, 0); sync_out = syncobj_create(xe, 0); diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c index d9c059e4d..1bde876cd 100644 --- a/tests/intel/xe_copy_basic.c +++ b/tests/intel/xe_copy_basic.c @@ -137,7 +137,7 @@ static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t reg src_handle = xe_bo_create(fd, 0, bo_size, region, 0); dst_handle = xe_bo_create(fd, 0, bo_size, region, 0); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); diff --git a/tests/intel/xe_create.c b/tests/intel/xe_create.c index 75f802247..0aa32c788 100644 --- a/tests/intel/xe_create.c +++ b/tests/intel/xe_create.c @@ -73,7 +73,7 @@ static void create_invalid_size(int fd) uint32_t handle; int ret; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); xe_for_each_mem_region(fd, memreg, region) { memregion = xe_mem_region(fd, region); @@ -172,7 +172,7 @@ static void create_execqueues(int fd, enum exec_queue_destroy ed) fd = drm_reopen_driver(fd); num_engines = xe_number_engines(fd); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); exec_queues_per_process = max_t(uint32_t, 1, MAXEXECQUEUES / nproc); igt_debug("nproc: %u, exec_queues per process: %u\n", nproc, exec_queues_per_process); @@ -239,7 +239,7 @@ static void create_massive_size(int fd) uint32_t handle; int ret; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); xe_for_each_mem_region(fd, memreg, region) { ret = __create_bo(fd, vm, -1ULL << 32, region, &handle); @@ -262,7 +262,7 @@ static void create_big_vram(int fd, int gt) uint64_t vm = 0; alignment = xe_get_default_alignment(fd); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); visible_avail_size = xe_visible_available_vram_size(fd, gt); igt_require(visible_avail_size); diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c index fd6c07410..36bb39a31 100644 --- a/tests/intel/xe_drm_fdinfo.c +++ b/tests/intel/xe_drm_fdinfo.c @@ -71,7 +71,7 @@ static void test_active(int fd, struct drm_xe_engine *engine) struct xe_spin_opts spin_opts = { .preempt = true }; int i, b, ret; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * N_EXEC_QUEUES; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -91,7 +91,7 @@ static void test_active(int fd, struct drm_xe_engine *engine) for (i = 0; i < N_EXEC_QUEUES; i++) { exec_queues[i] = xe_exec_queue_create(fd, vm, &engine->instance, 0); - bind_exec_queues[i] = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_exec_queues[i] = xe_bind_exec_queue_create(fd, vm, 0); syncobjs[i] = syncobj_create(fd, 0); } syncobjs[N_EXEC_QUEUES] = syncobj_create(fd, 0); diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c index 0ac83a3f7..4de82c3bd 100644 --- a/tests/intel/xe_evict.c +++ b/tests/intel/xe_evict.c @@ -63,17 +63,15 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci, fd = drm_open_driver(DRIVER_XE); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); if (flags & BIND_EXEC_QUEUE) - bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0); if (flags & MULTI_VM) { - vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); - vm3 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm2 = xe_vm_create(fd, 0, 0); + vm3 = xe_vm_create(fd, 0, 0); if (flags & BIND_EXEC_QUEUE) { - bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2, - 0, true); - bind_exec_queues[2] = xe_bind_exec_queue_create(fd, vm3, - 0, true); + bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2, 0); + bind_exec_queues[2] = xe_bind_exec_queue_create(fd, vm3, 0); } } @@ -245,16 +243,13 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci, fd = drm_open_driver(DRIVER_XE); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); if (flags & BIND_EXEC_QUEUE) - bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0); if (flags & MULTI_VM) { - vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); if (flags & BIND_EXEC_QUEUE) - bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2, - 0, true); + bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2, 0); } for (i = 0; i < n_exec_queues; i++) { diff --git a/tests/intel/xe_evict_ccs.c b/tests/intel/xe_evict_ccs.c index 674c8537e..5dd438cad 100644 --- a/tests/intel/xe_evict_ccs.c +++ b/tests/intel/xe_evict_ccs.c @@ -227,7 +227,7 @@ static void evict_single(int fd, int child, const struct config *config) uint32_t kb_left = config->mb_per_proc * SZ_1K; uint32_t min_alloc_kb = config->param->min_size_kb; uint32_t max_alloc_kb = config->param->max_size_kb; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); uint64_t ahnd = intel_allocator_open(fd, vm, INTEL_ALLOCATOR_RELOC); uint8_t uc_mocs = intel_get_uc_mocs_index(fd); struct object *obj, *tmp; diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c index 5dded3ce4..664e6da59 100644 --- a/tests/intel/xe_exec_balancer.c +++ b/tests/intel/xe_exec_balancer.c @@ -66,7 +66,7 @@ static void test_all_active(int fd, int gt, int class) if (num_placements < 2) return; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * num_placements; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -208,7 +208,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs, if (num_placements < 2) return; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -435,8 +435,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs, if (num_placements < 2) return; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c index 2defd1e35..8994859fa 100644 --- a/tests/intel/xe_exec_basic.c +++ b/tests/intel/xe_exec_basic.c @@ -109,7 +109,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, igt_assert(n_vm <= MAX_N_EXEC_QUEUES); for (i = 0; i < n_vm; ++i) - vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm[i] = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -152,8 +152,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, exec_queues[i] = xe_exec_queue_create(fd, __vm, eci, 0); if (flags & BIND_EXEC_QUEUE) bind_exec_queues[i] = xe_bind_exec_queue_create(fd, - __vm, 0, - true); + __vm, 0); else bind_exec_queues[i] = 0; syncobjs[i] = syncobj_create(fd, 0); @@ -173,7 +172,6 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, __xe_vm_bind_assert(fd, vm[i], bind_exec_queues[i], 0, 0, sparse_addr[i], bo_size, DRM_XE_VM_BIND_OP_MAP, - DRM_XE_VM_BIND_FLAG_ASYNC | DRM_XE_VM_BIND_FLAG_NULL, sync, 1, 0, 0); } diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c index 6123d2b29..b935ee0bc 100644 --- a/tests/intel/xe_exec_compute_mode.c +++ b/tests/intel/xe_exec_compute_mode.c @@ -114,8 +114,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, igt_assert(n_exec_queues <= MAX_N_EXECQUEUES); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -124,7 +123,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0); if (flags & BIND_EXECQUEUE) bind_exec_queues[i] = - xe_bind_exec_queue_create(fd, vm, 0, true); + xe_bind_exec_queue_create(fd, vm, 0); else bind_exec_queues[i] = 0; }; @@ -153,7 +152,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0); if (flags & BIND_EXECQUEUE) bind_exec_queues[i] = - xe_bind_exec_queue_create(fd, vm, 0, true); + xe_bind_exec_queue_create(fd, vm, 0); else bind_exec_queues[i] = 0; }; diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c index 3dda33469..f19e939e3 100644 --- a/tests/intel/xe_exec_fault_mode.c +++ b/tests/intel/xe_exec_fault_mode.c @@ -131,8 +131,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE | + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), @@ -168,7 +167,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0); if (flags & BIND_EXEC_QUEUE) bind_exec_queues[i] = - xe_bind_exec_queue_create(fd, vm, 0, true); + xe_bind_exec_queue_create(fd, vm, 0); else bind_exec_queues[i] = 0; }; diff --git a/tests/intel/xe_exec_queue_property.c b/tests/intel/xe_exec_queue_property.c index 0b578510c..53e08fb0e 100644 --- a/tests/intel/xe_exec_queue_property.c +++ b/tests/intel/xe_exec_queue_property.c @@ -56,7 +56,7 @@ static void test_set_property(int xe, int property_name, int property_value, int err_val) { struct drm_xe_engine_class_instance instance = { - .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND_SYNC, + .engine_class = DRM_XE_ENGINE_CLASS_VM_BIND, }; struct drm_xe_ext_set_property ext = { .base.next_extension = 0, diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c index 9d0c7658b..0cd5b1051 100644 --- a/tests/intel/xe_exec_reset.c +++ b/tests/intel/xe_exec_reset.c @@ -45,7 +45,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci) struct xe_spin *spin; struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false }; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*spin); bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -177,7 +177,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs, if (num_placements < 2) return; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -364,7 +364,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, if (flags & CLOSE_FD) fd = drm_open_driver(DRIVER_XE); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -531,8 +531,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci, if (flags & CLOSE_FD) fd = drm_open_driver(DRIVER_XE); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c index 7a66d744c..ec875cffc 100644 --- a/tests/intel/xe_exec_store.c +++ b/tests/intel/xe_exec_store.c @@ -106,7 +106,7 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc syncobj = syncobj_create(fd, 0); sync.handle = syncobj; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data); bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -116,7 +116,7 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); exec_queue = xe_exec_queue_create(fd, vm, eci, 0); - bind_engine = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_engine = xe_bind_exec_queue_create(fd, vm, 0); xe_vm_bind_async(fd, vm, bind_engine, bo, 0, addr, bo_size, &sync, 1); data = xe_bo_map(fd, bo, bo_size); @@ -185,7 +185,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci, size_t bo_size = 4096; bo_size = ALIGN(bo_size, xe_get_default_alignment(fd)); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE); exec_queues = xe_exec_queue_create(fd, vm, eci, 0); syncobjs = syncobj_create(fd, 0); diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c index ca2dd421e..17ee57a49 100644 --- a/tests/intel/xe_exec_threads.c +++ b/tests/intel/xe_exec_threads.c @@ -77,7 +77,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr, } if (!vm) { - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); owns_vm = true; } @@ -286,8 +286,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, } if (!vm) { - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | - DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); owns_vm = true; } @@ -492,7 +491,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, } if (!vm) { - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); owns_vm = true; } @@ -536,7 +535,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr, exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0); if (flags & BIND_EXEC_QUEUE) bind_exec_queues[i] = xe_bind_exec_queue_create(fd, vm, - 0, true); + 0); else bind_exec_queues[i] = 0; syncobjs[i] = syncobj_create(fd, 0); @@ -1004,11 +1003,8 @@ static void threads(int fd, int flags) pthread_cond_init(&cond, 0); if (flags & SHARED_VM) { - vm_legacy_mode = xe_vm_create(fd, - DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, - 0); + vm_legacy_mode = xe_vm_create(fd, 0, 0); vm_compute_mode = xe_vm_create(fd, - DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT | DRM_XE_VM_CREATE_FLAG_LR_MODE, 0); } diff --git a/tests/intel/xe_exercise_blt.c b/tests/intel/xe_exercise_blt.c index 655e9a3ea..cc9060b1b 100644 --- a/tests/intel/xe_exercise_blt.c +++ b/tests/intel/xe_exercise_blt.c @@ -280,7 +280,7 @@ static void fast_copy_test(int xe, region1 = igt_collection_get_value(regions, 0); region2 = igt_collection_get_value(regions, 1); - vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(xe, 0, 0); exec_queue = xe_exec_queue_create(xe, vm, &inst, 0); ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0); diff --git a/tests/intel/xe_huc_copy.c b/tests/intel/xe_huc_copy.c index 035d86ea8..ca045c41b 100644 --- a/tests/intel/xe_huc_copy.c +++ b/tests/intel/xe_huc_copy.c @@ -157,7 +157,7 @@ test_huc_copy(int fd) uint32_t vm; uint32_t tested_gts = 0; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); xe_for_each_engine(fd, hwe) { if (hwe->engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE && diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c index 804e176ee..d3d7a4fb6 100644 --- a/tests/intel/xe_intel_bb.c +++ b/tests/intel/xe_intel_bb.c @@ -192,7 +192,7 @@ static void simple_bb(struct buf_ops *bops, bool new_context) intel_bb_reset(ibb, true); if (new_context) { - vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(xe, 0, 0); ctx = xe_exec_queue_create(xe, vm, &xe_engine(xe, 0)->instance, 0); intel_bb_destroy(ibb); diff --git a/tests/intel/xe_noexec_ping_pong.c b/tests/intel/xe_noexec_ping_pong.c index c91340784..c372cc82d 100644 --- a/tests/intel/xe_noexec_ping_pong.c +++ b/tests/intel/xe_noexec_ping_pong.c @@ -72,8 +72,8 @@ static void test_ping_pong(int fd, struct drm_xe_engine *engine) bo[i][j] = xe_bo_create(fd, vm[i], bo_size, vram_memory(fd, 0), 0); - xe_vm_bind(fd, vm[i], bo[i][j], 0, 0x40000 + j*bo_size, - bo_size, NULL, 0); + xe_vm_bind_async(fd, vm[i], 0, bo[i][j], 0, + 0x40000 + j*bo_size, bo_size, NULL, 0); } exec_queues[i] = xe_exec_queue_create(fd, vm[i], &engine->instance, 0); diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c index 7273242b0..c5187bb94 100644 --- a/tests/intel/xe_pat.c +++ b/tests/intel/xe_pat.c @@ -254,7 +254,7 @@ static void pat_index_blt(struct xe_pat_param *p) igt_require(blt_has_fast_copy(fd)); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); exec_queue = xe_exec_queue_create(fd, vm, &inst, 0); ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0); ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0, @@ -470,7 +470,7 @@ static void pat_index_dw(struct xe_pat_param *p) break; } - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); ctx = xe_exec_queue_create(fd, vm, hwe, 0); ibb = intel_bb_create_full(fd, ctx, vm, NULL, xe_get_default_alignment(fd), diff --git a/tests/intel/xe_peer2peer.c b/tests/intel/xe_peer2peer.c index 6cf80f7b5..44fea6eb1 100644 --- a/tests/intel/xe_peer2peer.c +++ b/tests/intel/xe_peer2peer.c @@ -121,7 +121,7 @@ static void test_read(struct gpu_info *ex_gpu, struct gpu_info *im_gpu, }; intel_ctx_t *ctx; - vm = xe_vm_create(im_xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(im_xe, 0, 0); exec_queue = xe_exec_queue_create(im_xe, vm, &inst, 0); ctx = intel_ctx_xe(im_xe, vm, exec_queue, 0, 0, 0); ahnd = intel_allocator_open_full(im_xe, ctx->vm, 0, 0, @@ -203,7 +203,7 @@ static void test_write(struct gpu_info *ex_gpu, struct gpu_info *im_gpu, }; intel_ctx_t *ctx; - vm = xe_vm_create(im_xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(im_xe, 0, 0); exec_queue = xe_exec_queue_create(im_xe, vm, &inst, 0); ctx = intel_ctx_xe(im_xe, vm, exec_queue, 0, 0, 0); ahnd = intel_allocator_open_full(im_xe, ctx->vm, 0, 0, diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c index c899bd67a..602729daf 100644 --- a/tests/intel/xe_pm.c +++ b/tests/intel/xe_pm.c @@ -259,7 +259,7 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci, if (check_rpm) igt_assert(in_d3(device, d_state)); - vm = xe_vm_create(device.fd_xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(device.fd_xe, 0, 0); if (check_rpm) igt_assert(out_of_d3(device, d_state)); diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c index e8dca7826..3f3283829 100644 --- a/tests/intel/xe_spin_batch.c +++ b/tests/intel/xe_spin_batch.c @@ -190,7 +190,7 @@ static void preempter(int fd, struct drm_xe_engine_class_instance *hwe) syncobj = syncobj_create(fd, 0); sync.handle = syncobj; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data); bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c index fb65793d1..2200040ac 100644 --- a/tests/intel/xe_vm.c +++ b/tests/intel/xe_vm.c @@ -268,7 +268,7 @@ test_bind_one_bo_many_times_many_vm(int fd) static void test_partial_unbinds(int fd) { - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); size_t bo_size = 3 * xe_get_default_alignment(fd); uint32_t bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0), 0); uint64_t unbind_size = bo_size / 3; @@ -318,7 +318,7 @@ static void unbind_all(int fd, int n_vmas) { .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, }, }; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0), 0); for (i = 0; i < n_vmas; ++i) @@ -416,7 +416,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo, data = malloc(sizeof(*data) * n_bo); igt_assert(data); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(struct shared_pte_page_data); bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -601,7 +601,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec struct xe_spin_opts spin_opts = { .preempt = true }; int i, b; - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * N_EXEC_QUEUES; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -612,7 +612,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec for (i = 0; i < N_EXEC_QUEUES; i++) { exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0); - bind_exec_queues[i] = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_exec_queues[i] = xe_bind_exec_queue_create(fd, vm, 0); syncobjs[i] = syncobj_create(fd, 0); } syncobjs[N_EXEC_QUEUES] = syncobj_create(fd, 0); @@ -782,7 +782,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = sizeof(*data) * n_execs; bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd)); @@ -793,7 +793,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, data = xe_bo_map(fd, bo, bo_size); if (flags & BIND_ARRAY_BIND_EXEC_QUEUE_FLAG) - bind_exec_queue = xe_bind_exec_queue_create(fd, vm, 0, true); + bind_exec_queue = xe_bind_exec_queue_create(fd, vm, 0); exec_queue = xe_exec_queue_create(fd, vm, eci, 0); for (i = 0; i < n_execs; ++i) { @@ -802,7 +802,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, bind_ops[i].range = bo_size; bind_ops[i].addr = addr; bind_ops[i].op = DRM_XE_VM_BIND_OP_MAP; - bind_ops[i].flags = DRM_XE_VM_BIND_FLAG_ASYNC; + bind_ops[i].flags = 0; bind_ops[i].prefetch_mem_region_instance = 0; bind_ops[i].pat_index = intel_get_pat_idx_wb(fd); bind_ops[i].reserved[0] = 0; @@ -848,7 +848,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs, for (i = 0; i < n_execs; ++i) { bind_ops[i].obj = 0; bind_ops[i].op = DRM_XE_VM_BIND_OP_UNMAP; - bind_ops[i].flags = DRM_XE_VM_BIND_FLAG_ASYNC; + bind_ops[i].flags = 0; } syncobj_reset(fd, &sync[0].handle, 1); @@ -977,7 +977,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci, } igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES); - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); if (flags & LARGE_BIND_FLAG_USERPTR) { map = aligned_alloc(xe_get_default_alignment(fd), bo_size); @@ -1272,7 +1272,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci, unbind_n_page_offset *= n_page_per_2mb; } - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = page_size * bo_n_pages; if (flags & MAP_FLAG_USERPTR) { @@ -1572,7 +1572,7 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci, unbind_n_page_offset *= n_page_per_2mb; } - vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + vm = xe_vm_create(fd, 0, 0); bo_size = page_size * bo_n_pages; if (flags & MAP_FLAG_USERPTR) { diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c index 4421e571a..7ba20764c 100644 --- a/tests/intel/xe_waitfence.c +++ b/tests/intel/xe_waitfence.c @@ -92,7 +92,7 @@ waitfence(int fd, enum waittype wt) uint32_t bo_7; int64_t timeout; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); bo_1 = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); do_bind(fd, vm, bo_1, 0, 0x200000, 0x40000, 1); bo_2 = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); @@ -173,7 +173,7 @@ invalid_flag(int fd) .exec_queue_id = 0, }; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); @@ -197,7 +197,7 @@ invalid_ops(int fd) .exec_queue_id = 0, }; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); @@ -221,7 +221,7 @@ invalid_engine(int fd) .exec_queue_id = 0, }; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); bo = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0); @@ -260,7 +260,7 @@ exec_queue_reset_wait(int fd) .syncs = to_user_pointer(sync), }; - uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0); + uint32_t vm = xe_vm_create(fd, 0, 0); uint32_t exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY); struct drm_xe_wait_user_fence wait = { .op = DRM_XE_UFENCE_WAIT_OP_EQ, -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 09/10] drm-uapi/xe: Update header after documentation updates 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (7 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 08/10] drm-uapi/xe: Remove sync binds Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:50 ` [PATCH v1 10/10] tests/intel/xe: Remove xe_uevent for now Francois Dugast ` (4 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi This aligns with a series of documentation updates in the Xe KMD header up to commit ("drm/xe/uapi: Move DRM_XE_ACC_GRANULARITY_* where they are used") Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/xe_drm.h | 754 ++++++++++++++++++++++++++------------ 1 file changed, 517 insertions(+), 237 deletions(-) diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index c39d78a39..991c45bda 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -12,22 +12,114 @@ extern "C" { #endif -/* Please note that modifications to all structs defined here are +/* + * Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. + * Sections in this file are organized as follows: + * 1. IOCTL definition + * 2. Extension definition and helper structs + * 3. IOCTL's Query structs in the order of the Query's entries. + * 4. The rest of IOCTL structs in the order of IOCTL declaration. + * 5. uEvents */ /** - * DOC: uevent generated by xe on it's pci node. + * DOC: Xe Device Block Diagram * - * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt - * fails. The value supplied with the event is always "NEEDS_RESET". - * Additional information supplied is tile id and gt id of the gt unit for - * which reset has failed. + * The diagram below represents a high-level simplification of a discrete + * GPU supported by the Xe driver. It shows some device components which + * are necessary to understand this API, as well as how their relations + * to each other. This diagram does not represent real hardware:: + * + * ┌──────────────────────────────────────────────────────────────────┐ + * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ + * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ + * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ + * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ + * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ + * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ + * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ + * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ + * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ + * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ + * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ + * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ + * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ + * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ + * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ + * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ + * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ + * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ + * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ + * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ + * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ + * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ + * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ + * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ + * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ + * └─────────────────────────────Device0───────┬──────────────────────┘ + * │ + * ───────────────────────┴────────── PCI bus */ -#define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" /** - * struct drm_xe_user_extension - Base class for defining a chain of extensions + * DOC: Xe uAPI Overview + * + * This section aims to describe the Xe's IOCTL entries, its structs, and other + * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related + * entries and usage. + * + * List of supported IOCTLs: + * - &DRM_IOCTL_XE_DEVICE_QUERY + * - &DRM_IOCTL_XE_GEM_CREATE + * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET + * - &DRM_IOCTL_XE_VM_CREATE + * - &DRM_IOCTL_XE_VM_DESTROY + * - &DRM_IOCTL_XE_VM_BIND + * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE + * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY + * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY + * - &DRM_IOCTL_XE_EXEC + * - &DRM_IOCTL_XE_WAIT_USER_FENCE + */ + +/* + * xe specific ioctls. + * + * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie + * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset + * against DRM_COMMAND_BASE and should be between [0x0, 0x60). + */ +#define DRM_XE_DEVICE_QUERY 0x00 +#define DRM_XE_GEM_CREATE 0x01 +#define DRM_XE_GEM_MMAP_OFFSET 0x02 +#define DRM_XE_VM_CREATE 0x03 +#define DRM_XE_VM_DESTROY 0x04 +#define DRM_XE_VM_BIND 0x05 +#define DRM_XE_EXEC_QUEUE_CREATE 0x06 +#define DRM_XE_EXEC_QUEUE_DESTROY 0x07 +#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 +#define DRM_XE_EXEC 0x09 +#define DRM_XE_WAIT_USER_FENCE 0x0a +/* Must be kept compact -- no holes */ + +#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) +#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) +#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) +#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) +#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) +#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) +#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) +#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) + +/** + * DOC: Xe IOCTL Extensions + * + * Before detailing the IOCTLs and its structs, it is important to highlight + * that every IOCTL in Xe is extensible. * * Many interfaces need to grow over time. In most cases we can simply * extend the struct and have userspace pass in more data. Another option, @@ -61,7 +153,10 @@ extern "C" { * Typically the struct drm_xe_user_extension would be embedded in some uAPI * struct, and in this case we would feed it the head of the chain(i.e ext1), * which would then apply all of the above extensions. - * +*/ + +/** + * struct drm_xe_user_extension - Base class for defining a chain of extensions */ struct drm_xe_user_extension { /** @@ -90,37 +185,28 @@ struct drm_xe_user_extension { __u32 pad; }; -/* - * xe specific ioctls. +/** + * struct drm_xe_ext_set_property - Generic set property extension * - * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie - * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset - * against DRM_COMMAND_BASE and should be between [0x0, 0x60). + * A generic struct that allows any of the Xe's IOCTL to be extended + * with a set_property operation. */ -#define DRM_XE_DEVICE_QUERY 0x00 -#define DRM_XE_GEM_CREATE 0x01 -#define DRM_XE_GEM_MMAP_OFFSET 0x02 -#define DRM_XE_VM_CREATE 0x03 -#define DRM_XE_VM_DESTROY 0x04 -#define DRM_XE_VM_BIND 0x05 -#define DRM_XE_EXEC_QUEUE_CREATE 0x06 -#define DRM_XE_EXEC_QUEUE_DESTROY 0x07 -#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 -#define DRM_XE_EXEC 0x09 -#define DRM_XE_WAIT_USER_FENCE 0x0a -/* Must be kept compact -- no holes */ +struct drm_xe_ext_set_property { + /** @base: base user extension */ + struct drm_xe_user_extension base; -#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) -#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) -#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) -#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) -#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) -#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) -#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) -#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) -#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) -#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) -#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) + /** @property: property to set */ + __u32 property; + + /** @pad: MBZ */ + __u32 pad; + + /** @value: property value */ + __u64 value; + + /** @reserved: Reserved */ + __u64 reserved[2]; +}; /** * struct drm_xe_engine_class_instance - instance of an engine class @@ -128,6 +214,16 @@ struct drm_xe_user_extension { * It is returned as part of the @drm_xe_engine, but it also is used as * the input of engine selection for both @drm_xe_exec_queue_create and * @drm_xe_query_engine_cycles + * + * The @engine_class can be: + * - %DRM_XE_ENGINE_CLASS_RENDER + * - %DRM_XE_ENGINE_CLASS_COPY + * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE + * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE + * - %DRM_XE_ENGINE_CLASS_COMPUTE + * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual + * hardware engine class). Used for creating ordered queues of VM + * bind operations. */ struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_RENDER 0 @@ -135,10 +231,6 @@ struct drm_xe_engine_class_instance { #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 - /* - * Kernel only classes (not actual hardware engine class). Used for - * creating ordered queues of VM bind operations. - */ #define DRM_XE_ENGINE_CLASS_VM_BIND 5 /** @engine_class: engine class id */ __u16 engine_class; @@ -203,10 +295,9 @@ struct drm_xe_mem_region { */ __u16 mem_class; /** - * @instance: The instance for this region. - * - * The @mem_class and @instance taken together will always give - * a unique pair. + * @instance: The unique ID for this region, which serves as the + * index in the placement bitmask used as argument for + * &DRM_IOCTL_XE_GEM_CREATE */ __u16 instance; /** @@ -264,61 +355,10 @@ struct drm_xe_mem_region { * here will always be zero). */ __u64 cpu_visible_used; - /** @reserved: MBZ */ + /** @reserved: Reserved */ __u64 reserved[6]; }; -/** - * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps - * - * If a query is made with a struct drm_xe_device_query where .query is equal to - * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles - * in .data. struct drm_xe_query_engine_cycles is allocated by the user and - * .data points to this allocated structure. - * - * The query returns the engine cycles, which along with GT's @reference_clock, - * can be used to calculate the engine timestamp. In addition the - * query returns a set of cpu timestamps that indicate when the command - * streamer cycle count was captured. - */ -struct drm_xe_query_engine_cycles { - /** - * @eci: This is input by the user and is the engine for which command - * streamer cycles is queried. - */ - struct drm_xe_engine_class_instance eci; - - /** - * @clockid: This is input by the user and is the reference clock id for - * CPU timestamp. For definition, see clock_gettime(2) and - * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, - * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. - */ - __s32 clockid; - - /** @width: Width of the engine cycle counter in bits. */ - __u32 width; - - /** - * @engine_cycles: Engine cycles as read from its register - * at 0x358 offset. - */ - __u64 engine_cycles; - - /** - * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before - * reading the engine_cycles register using the reference clockid set by the - * user. - */ - __u64 cpu_timestamp; - - /** - * @cpu_delta: Time delta in ns captured around reading the lower dword - * of the engine_cycles register. - */ - __u64 cpu_delta; -}; - /** * struct drm_xe_query_mem_regions - describe memory regions * @@ -342,6 +382,19 @@ struct drm_xe_query_mem_regions { * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses * struct drm_xe_query_config in .data. * + * The index in @info can be: + * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) + * and the device revision (next 8 bits) + * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device + * configuration, see list below + * + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device + * has usable VRAM + * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment + * required by this device, typically SZ_4K or SZ_64K + * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address + * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest + * available exec queue priority */ struct drm_xe_query_config { /** @num_params: number of parameters returned in info */ @@ -367,6 +420,10 @@ struct drm_xe_query_config { * existing GT individual descriptions. * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for * implementing graphics and/or media operations. + * + * The index in @type can be: + * - %DRM_XE_QUERY_GT_TYPE_MAIN + * - %DRM_XE_QUERY_GT_TYPE_MEDIA */ struct drm_xe_gt { #define DRM_XE_QUERY_GT_TYPE_MAIN 0 @@ -385,6 +442,10 @@ struct drm_xe_gt { * @near_mem_regions: Bit mask of instances from * drm_xe_query_mem_regions that are nearest to the current engines * of this GT. + * Each index in this mask refers directly to the struct + * drm_xe_query_mem_regions' instance, no assumptions should + * be made about order. The type of each region is described + * by struct drm_xe_query_mem_regions' mem_class. */ __u64 near_mem_regions; /** @@ -393,6 +454,10 @@ struct drm_xe_gt { * In general, they have extra indirections when compared to the * @near_mem_regions. For a discrete device this could mean system * memory and memory living in a different tile. + * Each index in this mask refers directly to the struct + * drm_xe_query_mem_regions' instance, no assumptions should + * be made about order. The type of each region is described + * by struct drm_xe_query_mem_regions' mem_class. */ __u64 far_mem_regions; /** @reserved: Reserved */ @@ -424,34 +489,30 @@ struct drm_xe_query_gt_list { * If a query is made with a struct drm_xe_device_query where .query * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses * struct drm_xe_query_topology_mask in .data. + * + * The @type can be: + * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices + * (DSS) available for geometry operations. For example a query response + * containing the following in mask: + * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` + * means 32 DSS are available for geometry. + * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices + * (DSS) available for compute operations. For example a query response + * containing the following in mask: + * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` + * means 32 DSS are available for compute. + * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) + * available per Dual Sub Slices (DSS). For example a query response + * containing the following in mask: + * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` + * means each DSS has 16 EU. */ struct drm_xe_query_topology_mask { /** @gt_id: GT ID the mask is associated with */ __u16 gt_id; - /* - * To query the mask of Dual Sub Slices (DSS) available for geometry - * operations. For example a query response containing the following - * in mask: - * DSS_GEOMETRY ff ff ff ff 00 00 00 00 - * means 32 DSS are available for geometry. - */ #define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0) - /* - * To query the mask of Dual Sub Slices (DSS) available for compute - * operations. For example a query response containing the following - * in mask: - * DSS_COMPUTE ff ff ff ff 00 00 00 00 - * means 32 DSS are available for compute. - */ #define DRM_XE_TOPO_DSS_COMPUTE (1 << 1) - /* - * To query the mask of Execution Units (EU) available per Dual Sub - * Slices (DSS). For example a query response containing the following - * in mask: - * EU_PER_DSS ff ff 00 00 00 00 00 00 - * means each DSS has 16 EU. - */ #define DRM_XE_TOPO_EU_PER_DSS (1 << 2) /** @type: type of mask */ __u16 type; @@ -464,11 +525,81 @@ struct drm_xe_query_topology_mask { }; /** - * struct drm_xe_device_query - main structure to query device information + * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps * - * If size is set to 0, the driver fills it with the required size for the - * requested type of data to query. If size is equal to the required size, - * the queried information is copied into data. + * If a query is made with a struct drm_xe_device_query where .query is equal to + * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles + * in .data. struct drm_xe_query_engine_cycles is allocated by the user and + * .data points to this allocated structure. + * + * The query returns the engine cycles, which along with GT's @reference_clock, + * can be used to calculate the engine timestamp. In addition the + * query returns a set of cpu timestamps that indicate when the command + * streamer cycle count was captured. + */ +struct drm_xe_query_engine_cycles { + /** + * @eci: This is input by the user and is the engine for which command + * streamer cycles is queried. + */ + struct drm_xe_engine_class_instance eci; + + /** + * @clockid: This is input by the user and is the reference clock id for + * CPU timestamp. For definition, see clock_gettime(2) and + * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, + * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. + */ + __s32 clockid; + + /** @width: Width of the engine cycle counter in bits. */ + __u32 width; + + /** + * @engine_cycles: Engine cycles as read from its register + * at 0x358 offset. + */ + __u64 engine_cycles; + + /** + * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before + * reading the engine_cycles register using the reference clockid set by the + * user. + */ + __u64 cpu_timestamp; + + /** + * @cpu_delta: Time delta in ns captured around reading the lower dword + * of the engine_cycles register. + */ + __u64 cpu_delta; +}; + +/** + * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main + * structure to query device information + * + * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* + * and sets the value in the query member. This determines the type of + * the structure provided by the driver in data, among struct drm_xe_query_*. + * + * The @query can be: + * - %DRM_XE_DEVICE_QUERY_ENGINES + * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS + * - %DRM_XE_DEVICE_QUERY_CONFIG + * - %DRM_XE_DEVICE_QUERY_GT_LIST + * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware + * configuration of the device such as information on slices, memory, + * caches, and so on. It is provided as a table of key / value + * attributes. + * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY + * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES + * + * If size is set to 0, the driver fills it with the required size for + * the requested type of data to query. If size is equal to the required + * size, the queried information is copied into data. If size is set to + * a value different from 0 and different from the required size, the + * IOCTL call returns -EINVAL. * * For example the following code snippet allows retrieving and printing * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: @@ -526,6 +657,37 @@ struct drm_xe_device_query { __u64 reserved[2]; }; +/** + * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for + * gem creation + * + * The @flags can be: + * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING + * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT + * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a + * possible placement, ensure that the corresponding VRAM allocation + * will always use the CPU accessible part of VRAM. This is important + * for small-bar systems (on full-bar systems this gets turned into a + * noop). + * Note1: System memory can be used as an extra placement if the kernel + * should spill the allocation to system memory, if space can't be made + * available in the CPU accessible part of VRAM (giving the same + * behaviour as the i915 interface, see + * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). + * Note2: For clear-color CCS surfaces the kernel needs to read the + * clear-color value stored in the buffer, and on discrete platforms we + * need to use VRAM for display surfaces, therefore the kernel requires + * setting this flag for such objects, otherwise an error is thrown on + * small-bar systems. + * + * @cpu_caching supports the following values: + * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back + * caching. On iGPU this can't be used for scanout surfaces. Currently + * not allowed for objects placed in VRAM. + * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This + * is uncached. Scanout surfaces should likely use this. All objects + * that can be placed in VRAM must use this. + */ struct drm_xe_gem_create { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -536,26 +698,17 @@ struct drm_xe_gem_create { */ __u64 size; - /** @placement: A mask of memory instances of where BO can be placed. */ + /** + * @placement: A mask of memory instances of where BO can be placed. + * Each index in this mask refers directly to the struct + * drm_xe_query_mem_regions' instance, no assumptions should + * be made about order. The type of each region is described + * by struct drm_xe_query_mem_regions' mem_class. + */ __u32 placement; #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) -/* - * When using VRAM as a possible placement, ensure that the corresponding VRAM - * allocation will always use the CPU accessible part of VRAM. This is important - * for small-bar systems (on full-bar systems this gets turned into a noop). - * - * Note: System memory can be used as an extra placement if the kernel should - * spill the allocation to system memory, if space can't be made available in - * the CPU accessible part of VRAM (giving the same behaviour as the i915 - * interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). - * - * Note: For clear-color CCS surfaces the kernel needs to read the clear-color - * value stored in the buffer, and on discrete platforms we need to use VRAM for - * display surfaces, therefore the kernel requires setting this flag for such - * objects, otherwise an error is thrown on small-bar systems. - */ #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) /** * @flags: Flags, currently a mask of memory instances of where BO can @@ -580,22 +733,12 @@ struct drm_xe_gem_create { */ __u32 handle; +#define DRM_XE_GEM_CPU_CACHING_WB 1 +#define DRM_XE_GEM_CPU_CACHING_WC 2 /** * @cpu_caching: The CPU caching mode to select for this object. If * mmaping the object the mode selected here will also be used. - * - * Supported values: - * - * DRM_XE_GEM_CPU_CACHING_WB: Allocate the pages with write-back - * caching. On iGPU this can't be used for scanout surfaces. Currently - * not allowed for objects placed in VRAM. - * - * DRM_XE_GEM_CPU_CACHING_WC: Allocate the pages as write-combined. This - * is uncached. Scanout surfaces should likely use this. All objects - * that can be placed in VRAM must use this. */ -#define DRM_XE_GEM_CPU_CACHING_WB 1 -#define DRM_XE_GEM_CPU_CACHING_WC 2 __u16 cpu_caching; /** @pad: MBZ */ __u16 pad[3]; @@ -604,6 +747,9 @@ struct drm_xe_gem_create { __u64 reserved[2]; }; +/** + * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET + */ struct drm_xe_gem_mmap_offset { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -621,51 +767,35 @@ struct drm_xe_gem_mmap_offset { __u64 reserved[2]; }; -/** struct drm_xe_ext_set_property - XE set property extension */ -struct drm_xe_ext_set_property { - /** @base: base user extension */ - struct drm_xe_user_extension base; - - /** @property: property to set */ - __u32 property; - - /** @pad: MBZ */ - __u32 pad; - - /** @value: property value */ - __u64 value; - - /** @reserved: Reserved */ - __u64 reserved[2]; -}; - +/** + * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE + * + * The @flags can be: + * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE + * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts + * exec submissions to its exec_queues that don't have an upper time + * limit on the job execution time. But exec submissions to these + * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, + * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, + * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. + * LR VMs can be created in recoverable page-fault mode using + * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. + * If that flag is omitted, the UMD can not rely on the slightly + * different per-VM overcommit semantics that are enabled by + * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may + * still enable recoverable pagefaults if supported by the device. + * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also + * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on + * demand when accessed, and also allows per-VM overcommit of memory. + * The xe driver internally uses recoverable pagefaults to implement + * this. + */ struct drm_xe_vm_create { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) - /* - * An LR, or Long Running VM accepts exec submissions - * to its exec_queues that don't have an upper time limit on - * the job execution time. But exec submissions to these - * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, - * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, - * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. - * LR VMs can be created in recoverable page-fault mode using - * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. - * If that flag is omitted, the UMD can not rely on the slightly - * different per-VM overcommit semantics that are enabled by - * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may - * still enable recoverable pagefaults if supported by the device. - */ #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) - /* - * DRM_XE_VM_CREATE_FLAG_FAULT_MODE requires also - * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated - * on demand when accessed, and also allows per-VM overcommit of memory. - * The xe driver internally uses recoverable pagefaults to implement - * this. - */ #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) /** @flags: Flags */ __u32 flags; @@ -677,6 +807,9 @@ struct drm_xe_vm_create { __u64 reserved[2]; }; +/** + * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY + */ struct drm_xe_vm_destroy { /** @vm_id: VM ID */ __u32 vm_id; @@ -688,6 +821,29 @@ struct drm_xe_vm_destroy { __u64 reserved[2]; }; +/** + * struct drm_xe_vm_bind_op - run bind operations + * + * The @op can be: + * - %DRM_XE_VM_BIND_OP_MAP + * - %DRM_XE_VM_BIND_OP_UNMAP + * - %DRM_XE_VM_BIND_OP_MAP_USERPTR + * - %DRM_XE_VM_BIND_OP_UNMAP_ALL + * - %DRM_XE_VM_BIND_OP_PREFETCH + * + * and the @flags can be: + * - %DRM_XE_VM_BIND_FLAG_READONLY + * - %DRM_XE_VM_BIND_FLAG_ASYNC + * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - Valid on a faulting VM only, do the + * MAP operation immediately rather than deferring the MAP to the page + * fault handler. + * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page + * tables are setup with a special bit which indicates writes are + * dropped and all reads return zero. In the future, the NULL flags + * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO + * handle MBZ, and the BO offset MBZ. This flag is intended to + * implement VK sparse bindings. + */ struct drm_xe_vm_bind_op { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -774,18 +930,7 @@ struct drm_xe_vm_bind_op { __u32 op; #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) - /* - * Valid on a faulting VM only, do the MAP operation immediately rather - * than deferring the MAP to the page fault handler. - */ #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) - /* - * When the NULL flag is set, the page tables are setup with a special - * bit which indicates writes are dropped and all reads return zero. In - * the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP - * operations, the BO handle MBZ, and the BO offset MBZ. This flag is - * intended to implement VK sparse bindings. - */ #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) /** @flags: Bind flags */ __u32 flags; @@ -797,13 +942,40 @@ struct drm_xe_vm_bind_op { */ __u32 prefetch_mem_region_instance; - /** @pad: MBZ */ + /** @pad2: MBZ */ __u32 pad2; /** @reserved: Reserved */ __u64 reserved[3]; }; +/** + * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND + * + * Below is an example of a minimal use of @drm_xe_vm_bind to + * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to + * illustrate `userptr`. It can be synchronized by using the example + * provided for @drm_xe_sync. + * + * .. code-block:: C + * + * data = aligned_alloc(ALIGNMENT, BO_SIZE); + * struct drm_xe_vm_bind bind = { + * .vm_id = vm, + * .num_binds = 1, + * .bind.obj = 0, + * .bind.obj_offset = to_user_pointer(data), + * .bind.range = BO_SIZE, + * .bind.addr = BIND_ADDRESS, + * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, + * .bind.flags = 0, + * .num_syncs = 1, + * .syncs = &sync, + * .exec_queue_id = 0, + * }; + * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); + * + */ struct drm_xe_vm_bind { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -835,7 +1007,7 @@ struct drm_xe_vm_bind { __u64 vector_of_binds; }; - /** @pad: MBZ */ + /** @pad2: MBZ */ __u32 pad2; /** @num_syncs: amount of syncs to wait on */ @@ -848,20 +1020,28 @@ struct drm_xe_vm_bind { __u64 reserved[2]; }; -/* For use with DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */ - -/* Monitor 128KB contiguous region with 4K sub-granularity */ -#define DRM_XE_ACC_GRANULARITY_128K 0 - -/* Monitor 2MB contiguous region with 64KB sub-granularity */ -#define DRM_XE_ACC_GRANULARITY_2M 1 - -/* Monitor 16MB contiguous region with 512KB sub-granularity */ -#define DRM_XE_ACC_GRANULARITY_16M 2 - -/* Monitor 64MB contiguous region with 2M sub-granularity */ -#define DRM_XE_ACC_GRANULARITY_64M 3 - +/** + * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE + * + * The example below shows how to use @drm_xe_exec_queue_create to create + * a simple exec_queue (no parallel submission) of class + * &DRM_XE_ENGINE_CLASS_RENDER. + * + * .. code-block:: C + * + * struct drm_xe_engine_class_instance instance = { + * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, + * }; + * struct drm_xe_exec_queue_create exec_queue_create = { + * .extensions = 0, + * .vm_id = vm, + * .num_bb_per_exec = 1, + * .num_eng_per_bb = 1, + * .instances = to_user_pointer(&instance), + * }; + * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); + * + */ struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 @@ -872,6 +1052,14 @@ struct drm_xe_exec_queue_create { #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7 +/* Monitor 128KB contiguous region with 4K sub-granularity */ +#define DRM_XE_ACC_GRANULARITY_128K 0 +/* Monitor 2MB contiguous region with 64KB sub-granularity */ +#define DRM_XE_ACC_GRANULARITY_2M 1 +/* Monitor 16MB contiguous region with 512KB sub-granularity */ +#define DRM_XE_ACC_GRANULARITY_16M 2 +/* Monitor 64MB contiguous region with 2M sub-granularity */ +#define DRM_XE_ACC_GRANULARITY_64M 3 /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -904,6 +1092,26 @@ struct drm_xe_exec_queue_create { __u64 reserved[2]; }; +/** + * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY + */ +struct drm_xe_exec_queue_destroy { + /** @exec_queue_id: Exec queue ID */ + __u32 exec_queue_id; + + /** @pad: MBZ */ + __u32 pad; + + /** @reserved: Reserved */ + __u64 reserved[2]; +}; + +/** + * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY + * + * The @property can be: + * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN + */ struct drm_xe_exec_queue_get_property { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -922,17 +1130,41 @@ struct drm_xe_exec_queue_get_property { __u64 reserved[2]; }; -struct drm_xe_exec_queue_destroy { - /** @exec_queue_id: Exec queue ID */ - __u32 exec_queue_id; - - /** @pad: MBZ */ - __u32 pad; - - /** @reserved: Reserved */ - __u64 reserved[2]; -}; - +/** + * struct drm_xe_sync - sync object + * + * The @type can be: + * - %DRM_XE_SYNC_TYPE_SYNCOBJ + * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ + * - %DRM_XE_SYNC_TYPE_USER_FENCE + * + * and the @flags can be: + * - %DRM_XE_SYNC_FLAG_SIGNAL + * + * A minimal use of @drm_xe_sync looks like this: + * + * .. code-block:: C + * + * struct drm_xe_sync sync = { + * .flags = DRM_XE_SYNC_FLAG_SIGNAL, + * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, + * }; + * struct drm_syncobj_create syncobj_create = { 0 }; + * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); + * sync.handle = syncobj_create.handle; + * ... + * use of &sync in drm_xe_exec or drm_xe_vm_bind + * ... + * struct drm_syncobj_wait wait = { + * .handles = &sync.handle, + * .timeout_nsec = INT64_MAX, + * .count_handles = 1, + * .flags = 0, + * .first_signaled = 0, + * .pad = 0, + * }; + * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); + */ struct drm_xe_sync { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -948,11 +1180,12 @@ struct drm_xe_sync { __u32 flags; union { + /** @handle: Handle for the object */ __u32 handle; /** - * @addr: Address of user fence. When sync passed in via exec - * IOCTL this a GPU address in the VM. When sync passed in via + * @addr: Address of user fence. When sync is passed in via exec + * IOCTL this is a GPU address in the VM. When sync passed in via * VM bind IOCTL this is a user pointer. In either case, it is * the users responsibility that this address is present and * mapped when the user fence is signalled. Must be qword @@ -961,12 +1194,36 @@ struct drm_xe_sync { __u64 addr; }; + /** + * @timeline_value: Input for the timeline sync object. Needs to be + * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ. + */ __u64 timeline_value; /** @reserved: Reserved */ __u64 reserved[2]; }; +/** + * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC + * + * This is an example to use @drm_xe_exec for execution of the object + * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue + * (see example in @drm_xe_exec_queue_create). It can be synchronized + * by using the example provided for @drm_xe_sync. + * + * .. code-block:: C + * + * struct drm_xe_exec exec = { + * .exec_queue_id = exec_queue, + * .syncs = &sync, + * .num_syncs = 1, + * .address = BIND_ADDRESS, + * .num_batch_buffer = 1, + * }; + * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); + * + */ struct drm_xe_exec { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; @@ -1000,7 +1257,7 @@ struct drm_xe_exec { }; /** - * struct drm_xe_wait_user_fence - wait user fence + * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE * * Wait on user fence, XE will wake-up on every HW engine interrupt in the * instances list and check if user fence is complete:: @@ -1008,6 +1265,24 @@ struct drm_xe_exec { * (*addr & MASK) OP (VALUE & MASK) * * Returns to user on user fence completion or timeout. + * + * The @op can be: + * - %DRM_XE_UFENCE_WAIT_OP_EQ + * - %DRM_XE_UFENCE_WAIT_OP_NEQ + * - %DRM_XE_UFENCE_WAIT_OP_GT + * - %DRM_XE_UFENCE_WAIT_OP_GTE + * - %DRM_XE_UFENCE_WAIT_OP_LT + * - %DRM_XE_UFENCE_WAIT_OP_LTE + * + * and the @flags can be: + * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME + * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP + * + * The @mask values can be for example: + * - 0xffu for u8 + * - 0xffffu for u16 + * - 0xffffffffu for u32 + * - 0xffffffffffffffffu for u64 */ struct drm_xe_wait_user_fence { /** @extensions: Pointer to the first extension struct, if any */ @@ -1037,13 +1312,7 @@ struct drm_xe_wait_user_fence { /** @value: compare value */ __u64 value; - /** - * @mask: comparison mask, values can be for example: - * - 0xffu for u8 - * - 0xffffu for u16 - * - 0xffffffffu for u32 - * - 0xffffffffffffffffu for u64 - */ + /** @mask: comparison mask */ __u64 mask; /** @@ -1071,6 +1340,17 @@ struct drm_xe_wait_user_fence { /** @reserved: Reserved */ __u64 reserved[2]; }; + +/** + * DOC: uevent generated by xe on it's pci node. + * + * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt + * fails. The value supplied with the event is always "NEEDS_RESET". + * Additional information supplied is tile id and gt id of the gt unit for + * which reset has failed. + */ +#define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" + #if defined(__cplusplus) } #endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v1 10/10] tests/intel/xe: Remove xe_uevent for now 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (8 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 09/10] drm-uapi/xe: Update header after documentation updates Francois Dugast @ 2023-12-15 15:50 ` Francois Dugast 2023-12-15 15:56 ` [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Dixit, Ashutosh ` (3 subsequent siblings) 13 siblings, 0 replies; 16+ messages in thread From: Francois Dugast @ 2023-12-15 15:50 UTC (permalink / raw) To: igt-dev; +Cc: Lucas De Marchi, Rodrigo Vivi From: Rodrigo Vivi <rodrigo.vivi@intel.com> This kernel uevent is getting removed for now. It will come back later with a better future proof name. v2: Align with kernel commit ("drm/xe/uapi: Remove reset uevent \ for now") (Francois Dugast) Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Francois Dugast <francois.dugast@intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> --- include/drm-uapi/xe_drm.h | 11 ---- tests/intel/xe_uevent.c | 129 -------------------------------------- tests/meson.build | 1 - 3 files changed, 141 deletions(-) delete mode 100644 tests/intel/xe_uevent.c diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index 991c45bda..bacdca787 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -20,7 +20,6 @@ extern "C" { * 2. Extension definition and helper structs * 3. IOCTL's Query structs in the order of the Query's entries. * 4. The rest of IOCTL structs in the order of IOCTL declaration. - * 5. uEvents */ /** @@ -1341,16 +1340,6 @@ struct drm_xe_wait_user_fence { __u64 reserved[2]; }; -/** - * DOC: uevent generated by xe on it's pci node. - * - * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt - * fails. The value supplied with the event is always "NEEDS_RESET". - * Additional information supplied is tile id and gt id of the gt unit for - * which reset has failed. - */ -#define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" - #if defined(__cplusplus) } #endif diff --git a/tests/intel/xe_uevent.c b/tests/intel/xe_uevent.c deleted file mode 100644 index d30931714..000000000 --- a/tests/intel/xe_uevent.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * Copyright © 2023 Intel Corporation - */ - -/** - * TEST: cause fake gt reset failure and listen uevent from KMD - * Category: Software building block - * SUBTEST:fake_reset_uevent_listener - * Functionality: uevent - * Sub-category: GT reset failure uevent - * Test category: functionality test - * Description: - * Test creates uevent listener and causes fake reset failure for gt0 - * and returns success if uevent is sent by driver and listened by listener. - */ - -#include <libudev.h> -#include <string.h> -#include <sys/stat.h> - -#include "igt.h" - -#include "xe_drm.h" -#include "xe/xe_ioctl.h" -#include "xe/xe_query.h" - -static void xe_fail_gt_reset(int fd, int gt) -{ - igt_debugfs_write(fd, "fail_gt_reset/probability", "100"); - igt_debugfs_write(fd, "fail_gt_reset/times", "2"); - - xe_force_gt_reset(fd, gt); -} - -static bool listen_reset_fail_uevent(struct udev_device *device, const char *source, int gt_id) -{ - struct udev_list_entry *list_entry; - bool dev_needs_reset = false; - bool tile_id_passed = false; - bool gt_id_matches = false; - const char *name, *val; - - udev_list_entry_foreach(list_entry, udev_device_get_properties_list_entry(device)) - { - name = udev_list_entry_get_name(list_entry); - val = udev_list_entry_get_value(list_entry); - - if (!strcmp(name, "DEVICE_STATUS") && !strcmp(val, "NEEDS_RESET")) { - igt_debug("%s = %s\n", name, val); - dev_needs_reset = true; - continue; - } - - if (!strcmp(name, "TILE_ID")) { - igt_debug("%s = %s\n", name, val); - tile_id_passed = true; - continue; - } - - if (!strcmp(name, "GT_ID") && (atoi(val) == gt_id)) { - igt_debug("%s = %s\n", name, val); - gt_id_matches = true; - continue; - } - } - - return (dev_needs_reset && tile_id_passed && gt_id_matches); -} - -static void fake_reset_uevent_listener(int fd, int gt_id) -{ - struct udev *udev; - struct udev_device *dev; - struct udev_monitor *mon; - bool event_received = false; - bool event_sent = false; - const u32 listener_timeout = 5; - - /* create udev object */ - udev = udev_new(); - if (!udev) - igt_assert_f(false, "New udev object creation failed"); - - mon = udev_monitor_new_from_netlink(udev, "kernel"); - udev_monitor_filter_add_match_subsystem_devtype(mon, "pci", NULL); - udev_monitor_enable_receiving(mon); - igt_until_timeout(listener_timeout) { - if (event_sent) { - dev = udev_monitor_receive_device(mon); - if (dev) { - event_received = listen_reset_fail_uevent(dev, "kernel", gt_id); - udev_device_unref(dev); - } - } else { - event_sent = true; - xe_fail_gt_reset(fd, gt_id); - } - - if (event_received) - break; - } - - udev_unref(udev); - igt_assert_f(event_received, "Event not received"); -} - -igt_main -{ - int fd; - int gt; - const u32 settle_xe_load_uevents = 50000; - - igt_fixture - fd = drm_open_driver(DRIVER_XE); - - /* Ensures uevents triggered in case of driver - * load are settled down. - */ - usleep(settle_xe_load_uevents); - - igt_subtest("fake_reset_uevent_listener") - xe_for_each_gt(fd, gt) { - fake_reset_uevent_listener(fd, gt); - } - - igt_fixture - drm_close_driver(fd); -} diff --git a/tests/meson.build b/tests/meson.build index a5f5c143c..6dbe45e93 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -307,7 +307,6 @@ intel_xe_progs = [ 'xe_pm_residency', 'xe_prime_self_import', 'xe_query', - 'xe_uevent', 'xe_vm', 'xe_waitfence', 'xe_spin_batch', -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (9 preceding siblings ...) 2023-12-15 15:50 ` [PATCH v1 10/10] tests/intel/xe: Remove xe_uevent for now Francois Dugast @ 2023-12-15 15:56 ` Dixit, Ashutosh 2023-12-15 16:48 ` Rodrigo Vivi 2023-12-15 16:35 ` ✓ Fi.CI.BAT: success for uAPI Alignment - More cleanup before upstream (rev3) Patchwork ` (2 subsequent siblings) 13 siblings, 1 reply; 16+ messages in thread From: Dixit, Ashutosh @ 2023-12-15 15:56 UTC (permalink / raw) To: Francois Dugast; +Cc: igt-dev On Fri, 15 Dec 2023 07:50:40 -0800, Francois Dugast wrote: > Hi Francois, > This is a combined submission of series which have been sent and > reviewed separately. It aligns with this kernel series: > https://patchwork.freedesktop.org/series/127878/ > Could you please set your SubjectPrefix and label your IGT patches [PATCH i-g-t], then they will reach my correct email folder ;) .git/config [format] subjectPrefix = PATCH i-g-t Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream 2023-12-15 15:56 ` [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Dixit, Ashutosh @ 2023-12-15 16:48 ` Rodrigo Vivi 0 siblings, 0 replies; 16+ messages in thread From: Rodrigo Vivi @ 2023-12-15 16:48 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev On Fri, Dec 15, 2023 at 07:56:22AM -0800, Dixit, Ashutosh wrote: > On Fri, 15 Dec 2023 07:50:40 -0800, Francois Dugast wrote: > > > > Hi Francois, > > > This is a combined submission of series which have been sent and > > reviewed separately. It aligns with this kernel series: > > https://patchwork.freedesktop.org/series/127878/ > > > > Could you please set your SubjectPrefix and label your IGT patches > [PATCH i-g-t], then they will reach my correct email folder ;) I wonder why do we still need this? I understand that we needed this when igt was still using the same intel-gfx mailing list so we wanted a clear way to differentiate the igt from the kernel patches, but I don't see much sense on this after the mailng list is split. > > .git/config > > [format] > subjectPrefix = PATCH i-g-t I even had forgotten that I had this there :) > > Thanks. > -- > Ashutosh ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for uAPI Alignment - More cleanup before upstream (rev3) 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (10 preceding siblings ...) 2023-12-15 15:56 ` [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Dixit, Ashutosh @ 2023-12-15 16:35 ` Patchwork 2023-12-15 16:59 ` ✗ CI.xeBAT: failure " Patchwork 2023-12-16 0:22 ` ✗ Fi.CI.IGT: " Patchwork 13 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-12-15 16:35 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 18178 bytes --] == Series Details == Series: uAPI Alignment - More cleanup before upstream (rev3) URL : https://patchwork.freedesktop.org/series/127704/ State : success == Summary == CI Bug Log - changes from CI_DRM_14030 -> IGTPW_10429 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html Participating hosts (35 -> 36) ------------------------------ Additional (4): bat-dg2-8 bat-rpls-2 bat-kbl-2 bat-dg2-9 Missing (3): bat-mtlp-8 fi-snb-2520m fi-pnv-d510 Known issues ------------ Here are the changes found in IGTPW_10429 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@debugfs_test@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@debugfs_test@basic-hwmon.html * igt@fbdev@info: - bat-kbl-2: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1849]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-kbl-2/igt@fbdev@info.html * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-8: NOTRUN -> [INCOMPLETE][4] ([i915#9275]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@gem_exec_suspend@basic-s0@lmem0.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-kbl-2: NOTRUN -> [SKIP][6] ([fdo#109271]) +36 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html - bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html * igt@gem_mmap@basic: - bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@gem_mmap@basic.html - bat-dg2-9: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@gem_mmap@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@gem_mmap_gtt@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@gem_render_tiled_blits@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-9: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@gem_tiled_pread_basic.html - bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#3282]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@i915_pm_rps@basic-api.html - bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#6621]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@i915_pm_rps@basic-api.html - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#6621]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@i915_pm_rps@basic-api.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#6645]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html - bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#6645]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#4212] / [i915#9792]) +8 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#4212]) +6 other tests skip [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][23] ([i915#5190]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html - bat-mtlp-6: NOTRUN -> [SKIP][24] ([i915#5190] / [i915#9792]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html - bat-dg2-8: NOTRUN -> [SKIP][25] ([i915#5190]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-8: NOTRUN -> [SKIP][26] ([i915#4215] / [i915#5190]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html - bat-dg2-9: NOTRUN -> [SKIP][27] ([i915#4215] / [i915#5190]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][28] ([i915#4212]) +6 other tests skip [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg2-8: NOTRUN -> [SKIP][29] ([i915#4212] / [i915#5608]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html - bat-dg2-9: NOTRUN -> [SKIP][30] ([i915#4212] / [i915#5608]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-8: NOTRUN -> [SKIP][31] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html - bat-jsl-1: NOTRUN -> [SKIP][32] ([i915#4103]) +1 other test skip [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html - bat-dg2-9: NOTRUN -> [SKIP][33] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html - bat-rpls-2: NOTRUN -> [SKIP][34] ([i915#4103]) +1 other test skip [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][35] ([i915#9792]) +17 other tests skip [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-rpls-2: NOTRUN -> [SKIP][36] ([i915#3555] / [i915#3840] / [i915#9886]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@kms_dsc@dsc-basic.html - bat-jsl-1: NOTRUN -> [SKIP][37] ([i915#3555] / [i915#9886]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@kms_dsc@dsc-basic.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][38] ([i915#3637] / [i915#9792]) +3 other tests skip [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1: - fi-cfl-8109u: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][41] ([fdo#109285]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html - bat-jsl-1: NOTRUN -> [SKIP][42] ([fdo#109285]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html - bat-mtlp-6: NOTRUN -> [SKIP][43] ([fdo#109285] / [i915#9792]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html - bat-dg2-9: NOTRUN -> [SKIP][44] ([fdo#109285]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html - bat-rpls-2: NOTRUN -> [SKIP][45] ([fdo#109285]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9: NOTRUN -> [SKIP][46] ([i915#5274]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html - bat-mtlp-6: NOTRUN -> [SKIP][47] ([i915#5274] / [i915#9792]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html - bat-dg2-8: NOTRUN -> [SKIP][48] ([i915#5274]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][49] ([i915#4342] / [i915#5354] / [i915#9792]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-8: NOTRUN -> [SKIP][50] ([i915#5354]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html - bat-mtlp-6: NOTRUN -> [SKIP][51] ([i915#5354] / [i915#9792]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html - bat-dg2-9: NOTRUN -> [SKIP][52] ([i915#5354]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_pm_backlight@basic-brightness.html - bat-rpls-2: NOTRUN -> [SKIP][53] ([i915#5354]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@kms_pm_backlight@basic-brightness.html * igt@kms_pm_rpm@basic-rte: - bat-rpls-2: NOTRUN -> [ABORT][54] ([i915#8668]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-rpls-2/igt@kms_pm_rpm@basic-rte.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-9: NOTRUN -> [SKIP][55] ([i915#3555]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html - bat-mtlp-6: NOTRUN -> [SKIP][56] ([i915#3555] / [i915#8809] / [i915#9792]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html - bat-dg2-8: NOTRUN -> [SKIP][57] ([i915#3555]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html - bat-jsl-1: NOTRUN -> [SKIP][58] ([i915#3555]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-8: NOTRUN -> [SKIP][59] ([i915#3708]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html - bat-dg2-9: NOTRUN -> [SKIP][60] ([i915#3708]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html - bat-mtlp-6: NOTRUN -> [SKIP][61] ([i915#3708] / [i915#9792]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-mtlp-6: NOTRUN -> [SKIP][62] ([i915#3708] / [i915#4077]) +1 other test skip [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html - bat-dg2-9: NOTRUN -> [SKIP][63] ([i915#3708] / [i915#4077]) +1 other test skip [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-gtt: - bat-dg2-8: NOTRUN -> [SKIP][64] ([i915#3708] / [i915#4077]) +1 other test skip [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-write: - bat-dg2-9: NOTRUN -> [SKIP][65] ([i915#3291] / [i915#3708]) +2 other tests skip [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-9/igt@prime_vgem@basic-write.html - bat-mtlp-6: NOTRUN -> [SKIP][66] ([i915#3708]) +2 other tests skip [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@prime_vgem@basic-write.html - bat-dg2-8: NOTRUN -> [SKIP][67] ([i915#3291] / [i915#3708]) +2 other tests skip [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-dg2-8/igt@prime_vgem@basic-write.html #### Possible fixes #### * igt@i915_hangman@error-state-basic: - bat-mtlp-6: [ABORT][68] ([i915#9414]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/bat-mtlp-6/igt@i915_hangman@error-state-basic.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/bat-mtlp-6/igt@i915_hangman@error-state-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809 [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275 [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414 [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673 [i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792 [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7643 -> IGTPW_10429 CI-20190529: 20190529 CI_DRM_14030: 0896a36d44111936050697e425e1b903e91a1178 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_10429: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html IGT_7643: ced22f8bf4263ff395dc852c86b682e62a7a1c1b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Testlist changes ---------------- +igt@xe_waitfence@exec_queue-reset-wait -igt@xe_uevent@fake_reset_uevent_listener == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html [-- Attachment #2: Type: text/html, Size: 24257 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ CI.xeBAT: failure for uAPI Alignment - More cleanup before upstream (rev3) 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (11 preceding siblings ...) 2023-12-15 16:35 ` ✓ Fi.CI.BAT: success for uAPI Alignment - More cleanup before upstream (rev3) Patchwork @ 2023-12-15 16:59 ` Patchwork 2023-12-16 0:22 ` ✗ Fi.CI.IGT: " Patchwork 13 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-12-15 16:59 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 10383 bytes --] == Series Details == Series: uAPI Alignment - More cleanup before upstream (rev3) URL : https://patchwork.freedesktop.org/series/127704/ State : failure == Summary == CI Bug Log - changes from XEIGT_7643_BAT -> XEIGTPW_10429_BAT ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_10429_BAT absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_10429_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_10429_BAT: ### IGT changes ### #### Possible regressions #### * igt@xe_exec_compute_mode@twice-userptr-invalidate: - bat-atsm-2: [PASS][1] -> [FAIL][2] +120 other tests fail [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-atsm-2/igt@xe_exec_compute_mode@twice-userptr-invalidate.html * igt@xe_intel_bb@create-in-region: - bat-dg2-oem2: [PASS][3] -> [FAIL][4] +176 other tests fail [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-dg2-oem2/igt@xe_intel_bb@create-in-region.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-dg2-oem2/igt@xe_intel_bb@create-in-region.html * igt@xe_intel_bb@intel-bb-blit-y: - bat-pvc-2: [PASS][5] -> [FAIL][6] +138 other tests fail [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-pvc-2/igt@xe_intel_bb@intel-bb-blit-y.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-pvc-2/igt@xe_intel_bb@intel-bb-blit-y.html * igt@xe_intel_bb@offset-control: - bat-adlp-7: [PASS][7] -> [FAIL][8] +139 other tests fail [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@xe_intel_bb@offset-control.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@xe_intel_bb@offset-control.html #### Warnings #### * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - bat-adlp-7: [FAIL][9] ([i915#2346]) -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-wf_vblank: - bat-dg2-oem2: [FAIL][11] ([Intel XE#480]) -> [FAIL][12] +1 other test fail [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-dg2-oem2/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12: - bat-dg2-oem2: [FAIL][13] ([Intel XE#400] / [Intel XE#616]) -> [FAIL][14] +2 other tests fail [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html * igt@xe_evict@evict-beng-small-external: - bat-pvc-2: [FAIL][15] ([Intel XE#1000]) -> [FAIL][16] +3 other tests fail [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-pvc-2/igt@xe_evict@evict-beng-small-external.html [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-pvc-2/igt@xe_evict@evict-beng-small-external.html * igt@xe_evict@evict-small-external-cm: - bat-pvc-2: [DMESG-FAIL][17] ([Intel XE#482]) -> [FAIL][18] +3 other tests fail [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-pvc-2/igt@xe_evict@evict-small-external-cm.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-pvc-2/igt@xe_evict@evict-small-external-cm.html * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd: - bat-pvc-2: [INCOMPLETE][19] ([Intel XE#392]) -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-pvc-2/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-pvc-2/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate: - bat-dg2-oem2: [SKIP][21] ([Intel XE#288]) -> [FAIL][22] +32 other tests fail [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-dg2-oem2/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-dg2-oem2/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate.html * igt@xe_exec_fault_mode@twice-userptr-invalidate-imm: - bat-atsm-2: [SKIP][23] ([Intel XE#288]) -> [FAIL][24] +32 other tests fail [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-atsm-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-imm.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-atsm-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-imm.html * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch: - bat-adlp-7: [SKIP][25] ([Intel XE#288]) -> [FAIL][26] +32 other tests fail [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_psr@psr-cursor-plane-move}: - bat-adlp-7: [PASS][27] -> [FAIL][28] +8 other tests fail [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@kms_psr@psr-cursor-plane-move.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@kms_psr@psr-cursor-plane-move.html * {igt@xe_pat@pat-index-xehpc@blt}: - bat-pvc-2: [PASS][29] -> [FAIL][30] +1 other test fail [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-pvc-2/igt@xe_pat@pat-index-xehpc@blt.html [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-pvc-2/igt@xe_pat@pat-index-xehpc@blt.html * {igt@xe_pat@pat-index-xelp@render}: - bat-dg2-oem2: [PASS][31] -> [FAIL][32] +2 other tests fail [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-dg2-oem2/igt@xe_pat@pat-index-xelp@render.html [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-dg2-oem2/igt@xe_pat@pat-index-xelp@render.html - bat-atsm-2: [PASS][33] -> [FAIL][34] +2 other tests fail [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-atsm-2/igt@xe_pat@pat-index-xelp@render.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-atsm-2/igt@xe_pat@pat-index-xelp@render.html Known issues ------------ Here are the changes found in XEIGTPW_10429_BAT that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1: - bat-adlp-7: [PASS][35] -> [FAIL][36] ([Intel XE#1006]) +4 other tests fail [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html * igt@xe_prime_self_import@basic-with_fd_dup: - bat-atsm-2: [PASS][37] -> [FAIL][38] ([Intel XE#999]) [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-atsm-2/igt@xe_prime_self_import@basic-with_fd_dup.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-atsm-2/igt@xe_prime_self_import@basic-with_fd_dup.html #### Warnings #### * igt@kms_frontbuffer_tracking@basic: - bat-adlp-7: [DMESG-FAIL][39] ([Intel XE#1033]) -> [FAIL][40] ([Intel XE#1007]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7643/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000 [Intel XE#1006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1006 [Intel XE#1007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1007 [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/392 [Intel XE#400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/400 [Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480 [Intel XE#482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/482 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/999 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 Build changes ------------- * IGT: IGT_7643 -> IGTPW_10429 * Linux: xe-577-5cd1893366708380854f4694ae57417192458a6b -> xe-580-d25c0edf65307f50c5fb98e6790b548962ae75ed IGTPW_10429: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html IGT_7643: ced22f8bf4263ff395dc852c86b682e62a7a1c1b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-577-5cd1893366708380854f4694ae57417192458a6b: 5cd1893366708380854f4694ae57417192458a6b xe-580-d25c0edf65307f50c5fb98e6790b548962ae75ed: d25c0edf65307f50c5fb98e6790b548962ae75ed == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10429/index.html [-- Attachment #2: Type: text/html, Size: 11625 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.IGT: failure for uAPI Alignment - More cleanup before upstream (rev3) 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast ` (12 preceding siblings ...) 2023-12-15 16:59 ` ✗ CI.xeBAT: failure " Patchwork @ 2023-12-16 0:22 ` Patchwork 13 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-12-16 0:22 UTC (permalink / raw) To: Bommu, Krishnaiah; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 86297 bytes --] == Series Details == Series: uAPI Alignment - More cleanup before upstream (rev3) URL : https://patchwork.freedesktop.org/series/127704/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14030_full -> IGTPW_10429_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_10429_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_10429_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html Participating hosts (8 -> 8) ------------------------------ Additional (1): shard-glk-0 Missing (1): shard-snb-0 Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_10429_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_balancer@bonded-true-hang: - shard-mtlp: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_exec_balancer@bonded-true-hang.html * igt@i915_power@sanity: - shard-snb: NOTRUN -> [INCOMPLETE][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb2/igt@i915_power@sanity.html * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-snb: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-snb6/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb4/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html #### Warnings #### * igt@i915_pm_rps@engine-order: - shard-snb: [INCOMPLETE][5] ([i915#9847]) -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-snb5/igt@i915_pm_rps@engine-order.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb4/igt@i915_pm_rps@engine-order.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_vrr@seamless-rr-switch-vrr}: - shard-dg2: NOTRUN -> [SKIP][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@kms_vrr@seamless-rr-switch-vrr.html - shard-rkl: NOTRUN -> [SKIP][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-vrr.html - shard-tglu: NOTRUN -> [SKIP][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_vrr@seamless-rr-switch-vrr.html - shard-mtlp: NOTRUN -> [SKIP][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_vrr@seamless-rr-switch-vrr.html Known issues ------------ Here are the changes found in IGTPW_10429_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#8411]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@api_intel_bb@blit-reloc-purge-cache.html - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#8411]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@api_intel_bb@blit-reloc-purge-cache.html - shard-dg2: NOTRUN -> [SKIP][13] ([i915#8411]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@api_intel_bb@blit-reloc-purge-cache.html - shard-rkl: NOTRUN -> [SKIP][14] ([i915#8411]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-2/igt@api_intel_bb@blit-reloc-purge-cache.html * igt@debugfs_test@basic-hwmon: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#9318]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@debugfs_test@basic-hwmon.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [INCOMPLETE][16] ([i915#9618]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@device_reset@unbind-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#8414]) +12 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@drm_fdinfo@busy-hang@bcs0.html - shard-dg1: NOTRUN -> [SKIP][18] ([i915#8414]) +7 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@drm_fdinfo@busy-hang@bcs0.html * igt@drm_fdinfo@busy-hang@rcs0: - shard-mtlp: NOTRUN -> [SKIP][19] ([i915#8414]) +8 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@drm_fdinfo@busy-hang@rcs0.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][20] ([i915#7742]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@drm_fdinfo@virtual-idle.html * igt@gem_create@create-ext-cpu-access-big: - shard-tglu: NOTRUN -> [SKIP][21] ([i915#6335]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-8/igt@gem_create@create-ext-cpu-access-big.html - shard-mtlp: NOTRUN -> [SKIP][22] ([i915#6335]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_create@create-ext-cpu-access-big.html - shard-dg2: NOTRUN -> [INCOMPLETE][23] ([i915#9364]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html - shard-rkl: NOTRUN -> [SKIP][24] ([i915#6335]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][25] ([i915#8562]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_create@create-ext-set-pat.html - shard-rkl: NOTRUN -> [SKIP][26] ([i915#8562]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_create@create-ext-set-pat.html - shard-dg1: NOTRUN -> [SKIP][27] ([i915#8562]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@gem_create@create-ext-set-pat.html - shard-tglu: NOTRUN -> [SKIP][28] ([i915#8562]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@gem_create@create-ext-set-pat.html * igt@gem_ctx_persistence@engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#1099]) +5 other tests skip [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb4/igt@gem_ctx_persistence@engines-mixed-process.html * igt@gem_ctx_persistence@hang: - shard-mtlp: NOTRUN -> [SKIP][30] ([i915#8555]) +2 other tests skip [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@gem_ctx_persistence@hang.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-dg2: NOTRUN -> [SKIP][31] ([i915#8555]) +2 other tests skip [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hang.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][32] ([i915#8555]) +1 other test skip [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0: - shard-mtlp: NOTRUN -> [SKIP][33] ([i915#5882]) +5 other tests skip [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0.html * igt@gem_ctx_sseu@mmap-args: - shard-dg2: NOTRUN -> [SKIP][34] ([i915#280]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@gem_ctx_sseu@mmap-args.html - shard-rkl: NOTRUN -> [SKIP][35] ([i915#280]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@gem_ctx_sseu@mmap-args.html - shard-dg1: NOTRUN -> [SKIP][36] ([i915#280]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@gem_ctx_sseu@mmap-args.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][37] ([i915#8898]) +1 other test fail [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb1/igt@gem_eio@unwedge-stress.html - shard-dg1: NOTRUN -> [FAIL][38] ([i915#5784]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@bonded-chain: - shard-rkl: NOTRUN -> [ABORT][39] ([i915#9856]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_exec_balancer@bonded-chain.html * igt@gem_exec_balancer@bonded-pair: - shard-dg2: NOTRUN -> [SKIP][40] ([i915#4771]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@gem_exec_balancer@bonded-pair.html - shard-dg1: NOTRUN -> [SKIP][41] ([i915#4771]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@gem_exec_balancer@bonded-pair.html * igt@gem_exec_balancer@bonded-semaphore: - shard-dg1: NOTRUN -> [ABORT][42] ([i915#9855]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@gem_exec_balancer@bonded-semaphore.html * igt@gem_exec_balancer@fairslice: - shard-rkl: NOTRUN -> [ABORT][43] ([i915#9855] / [i915#9856]) +1 other test abort [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@gem_exec_balancer@fairslice.html - shard-dg1: NOTRUN -> [INCOMPLETE][44] ([i915#9856]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@gem_exec_balancer@fairslice.html * igt@gem_exec_balancer@full: - shard-dg2: NOTRUN -> [INCOMPLETE][45] ([i915#9856]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_exec_balancer@full.html - shard-mtlp: NOTRUN -> [ABORT][46] ([i915#9855] / [i915#9856]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_exec_balancer@full.html * igt@gem_exec_balancer@individual: - shard-rkl: NOTRUN -> [ABORT][47] ([i915#9855]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_exec_balancer@individual.html * igt@gem_exec_balancer@parallel-contexts: - shard-mtlp: NOTRUN -> [ABORT][48] ([i915#9855]) +2 other tests abort [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-dg2: NOTRUN -> [ABORT][49] ([i915#9855]) +1 other test abort [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@gem_exec_balancer@parallel-keep-in-fence.html - shard-glk: NOTRUN -> [ABORT][50] ([i915#9855]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk1/igt@gem_exec_balancer@parallel-keep-in-fence.html * igt@gem_exec_balancer@parallel-out-fence: - shard-dg2: NOTRUN -> [ABORT][51] ([i915#9856]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@gem_exec_balancer@parallel-out-fence.html - shard-dg1: NOTRUN -> [ABORT][52] ([i915#9856]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@gem_exec_balancer@parallel-out-fence.html - shard-mtlp: NOTRUN -> [ABORT][53] ([i915#9856]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_capture@capture-recoverable: - shard-rkl: NOTRUN -> [SKIP][54] ([i915#6344]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html - shard-tglu: NOTRUN -> [SKIP][55] ([i915#6344]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@gem_exec_capture@capture-recoverable.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-rkl: NOTRUN -> [FAIL][56] ([i915#2842]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-pace-share: - shard-dg2: NOTRUN -> [SKIP][57] ([i915#3539] / [i915#4852]) +1 other test skip [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@gem_exec_fair@basic-pace-share.html - shard-dg1: NOTRUN -> [SKIP][58] ([i915#3539] / [i915#4852]) +1 other test skip [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@gem_exec_fair@basic-pace-share.html - shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4473] / [i915#4771]) +1 other test skip [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@gem_exec_fair@basic-pace-share.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][60] ([i915#2842]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_flush@basic-uc-set-default: - shard-dg2: NOTRUN -> [SKIP][61] ([i915#3539]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@gem_exec_flush@basic-uc-set-default.html - shard-dg1: NOTRUN -> [SKIP][62] ([i915#3539]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@gem_exec_flush@basic-uc-set-default.html * igt@gem_exec_params@rsvd2-dirt: - shard-mtlp: NOTRUN -> [SKIP][63] ([i915#5107]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_exec_params@rsvd2-dirt.html - shard-dg2: NOTRUN -> [SKIP][64] ([fdo#109283] / [i915#5107]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_exec_params@rsvd2-dirt.html - shard-rkl: NOTRUN -> [SKIP][65] ([fdo#109283]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_exec_params@rsvd2-dirt.html - shard-tglu: NOTRUN -> [SKIP][66] ([fdo#109283]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@gem_exec_params@rsvd2-dirt.html * igt@gem_exec_reloc@basic-active: - shard-dg2: NOTRUN -> [SKIP][67] ([i915#3281]) +8 other tests skip [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_exec_reloc@basic-active.html * igt@gem_exec_reloc@basic-wc-noreloc: - shard-mtlp: NOTRUN -> [SKIP][68] ([i915#3281]) +7 other tests skip [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@gem_exec_reloc@basic-wc-noreloc.html * igt@gem_exec_reloc@basic-wc-read-active: - shard-dg1: NOTRUN -> [SKIP][69] ([i915#3281]) +5 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@gem_exec_reloc@basic-wc-read-active.html * igt@gem_exec_reloc@basic-wc-read-noreloc: - shard-rkl: NOTRUN -> [SKIP][70] ([i915#3281]) +7 other tests skip [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@gem_exec_reloc@basic-wc-read-noreloc.html * igt@gem_exec_whisper@basic-contexts-forked: - shard-mtlp: NOTRUN -> [ABORT][71] ([i915#9855] / [i915#9857]) +1 other test abort [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-forked.html - shard-tglu: NOTRUN -> [INCOMPLETE][72] ([i915#9857]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@gem_exec_whisper@basic-contexts-forked.html * igt@gem_exec_whisper@basic-forked: - shard-tglu: NOTRUN -> [INCOMPLETE][73] ([i915#7392] / [i915#9857]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-6/igt@gem_exec_whisper@basic-forked.html - shard-glk: NOTRUN -> [INCOMPLETE][74] ([i915#9857]) +1 other test incomplete [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk2/igt@gem_exec_whisper@basic-forked.html * igt@gem_exec_whisper@basic-queues: - shard-snb: NOTRUN -> [INCOMPLETE][75] ([i915#9857]) +7 other tests incomplete [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb1/igt@gem_exec_whisper@basic-queues.html * igt@gem_fence_thrash@bo-copy: - shard-dg2: NOTRUN -> [SKIP][76] ([i915#4860]) +2 other tests skip [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@gem_fence_thrash@bo-copy.html * igt@gem_fenced_exec_thrash@no-spare-fences: - shard-dg1: NOTRUN -> [SKIP][77] ([i915#4860]) +2 other tests skip [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@gem_fenced_exec_thrash@no-spare-fences.html - shard-mtlp: NOTRUN -> [SKIP][78] ([i915#4860]) +2 other tests skip [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_fenced_exec_thrash@no-spare-fences.html * igt@gem_huc_copy@huc-copy: - shard-rkl: NOTRUN -> [SKIP][79] ([i915#2190]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gem_huc_copy@huc-copy.html - shard-tglu: NOTRUN -> [SKIP][80] ([i915#2190]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4613]) +4 other tests skip [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@gem_lmem_swapping@heavy-verify-multi.html * igt@gem_lmem_swapping@random: - shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#4613]) +4 other tests skip [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk2/igt@gem_lmem_swapping@random.html * igt@gem_lmem_swapping@verify-random: - shard-rkl: NOTRUN -> [SKIP][83] ([i915#4613]) +4 other tests skip [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@gem_lmem_swapping@verify-random.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-tglu: NOTRUN -> [SKIP][84] ([i915#4613]) +4 other tests skip [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-10/igt@gem_lmem_swapping@verify-random-ccs.html * igt@gem_lmem_swapping@verify-random-ccs@lmem0: - shard-dg1: NOTRUN -> [SKIP][85] ([i915#4565]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html * igt@gem_media_fill@media-fill: - shard-mtlp: NOTRUN -> [SKIP][86] ([i915#8289]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_media_fill@media-fill.html - shard-dg2: NOTRUN -> [SKIP][87] ([i915#8289]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_media_fill@media-fill.html * igt@gem_mmap@short-mmap: - shard-mtlp: NOTRUN -> [SKIP][88] ([i915#4083]) +1 other test skip [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@gem_mmap@short-mmap.html * igt@gem_mmap_gtt@big-copy-odd: - shard-dg2: NOTRUN -> [SKIP][89] ([i915#4077]) +11 other tests skip [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-10/igt@gem_mmap_gtt@big-copy-odd.html * igt@gem_mmap_gtt@coherency: - shard-tglu: NOTRUN -> [SKIP][90] ([fdo#111656]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@gem_mmap_gtt@coherency.html - shard-rkl: NOTRUN -> [SKIP][91] ([fdo#111656]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@gem_mmap_gtt@coherency.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-dg1: NOTRUN -> [SKIP][92] ([i915#4077]) +9 other tests skip [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html * igt@gem_mmap_gtt@hang-busy: - shard-mtlp: NOTRUN -> [SKIP][93] ([i915#4077]) +8 other tests skip [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_mmap_gtt@hang-busy.html * igt@gem_mmap_wc@bad-offset: - shard-dg2: NOTRUN -> [SKIP][94] ([i915#4083]) +1 other test skip [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gem_mmap_wc@bad-offset.html * igt@gem_partial_pwrite_pread@write: - shard-dg2: NOTRUN -> [SKIP][95] ([i915#3282]) +3 other tests skip [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@gem_partial_pwrite_pread@write.html - shard-rkl: NOTRUN -> [SKIP][96] ([i915#3282]) +4 other tests skip [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@gem_partial_pwrite_pread@write.html - shard-dg1: NOTRUN -> [SKIP][97] ([i915#3282]) +4 other tests skip [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@gem_partial_pwrite_pread@write.html * igt@gem_pxp@reject-modify-context-protection-on: - shard-rkl: NOTRUN -> [SKIP][98] ([i915#4270]) +5 other tests skip [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@gem_pxp@reject-modify-context-protection-on.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-dg2: NOTRUN -> [SKIP][99] ([i915#4270]) +4 other tests skip [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html * igt@gem_pxp@verify-pxp-stale-ctx-execution: - shard-dg1: NOTRUN -> [SKIP][100] ([i915#4270]) +5 other tests skip [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@gem_pxp@verify-pxp-stale-ctx-execution.html - shard-tglu: NOTRUN -> [SKIP][101] ([i915#4270]) +4 other tests skip [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@gem_pxp@verify-pxp-stale-ctx-execution.html - shard-mtlp: NOTRUN -> [SKIP][102] ([i915#4270]) +2 other tests skip [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-3/igt@gem_pxp@verify-pxp-stale-ctx-execution.html * igt@gem_readwrite@new-obj: - shard-mtlp: NOTRUN -> [SKIP][103] ([i915#3282]) +2 other tests skip [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@gem_readwrite@new-obj.html * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled: - shard-mtlp: NOTRUN -> [SKIP][104] ([i915#8428]) +1 other test skip [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html * igt@gem_render_tiled_blits@basic: - shard-dg1: NOTRUN -> [SKIP][105] ([i915#4079]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@gem_render_tiled_blits@basic.html - shard-mtlp: NOTRUN -> [SKIP][106] ([i915#4079]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@gem_render_tiled_blits@basic.html - shard-dg2: NOTRUN -> [SKIP][107] ([i915#4079]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-10/igt@gem_render_tiled_blits@basic.html * igt@gem_unfence_active_buffers: - shard-dg1: NOTRUN -> [SKIP][108] ([i915#4879]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@gem_unfence_active_buffers.html - shard-mtlp: NOTRUN -> [SKIP][109] ([i915#4879]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@gem_unfence_active_buffers.html - shard-dg2: NOTRUN -> [SKIP][110] ([i915#4879]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@gem_unfence_active_buffers.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap: - shard-dg1: NOTRUN -> [SKIP][111] ([i915#3297] / [i915#4880]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html - shard-mtlp: NOTRUN -> [SKIP][112] ([i915#3297]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html - shard-dg2: NOTRUN -> [SKIP][113] ([i915#3297] / [i915#4880]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html * igt@gem_userptr_blits@unsync-overlap: - shard-dg2: NOTRUN -> [SKIP][114] ([i915#3297]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@gem_userptr_blits@unsync-overlap.html - shard-rkl: NOTRUN -> [SKIP][115] ([i915#3297]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@gem_userptr_blits@unsync-overlap.html - shard-dg1: NOTRUN -> [SKIP][116] ([i915#3297]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@gem_userptr_blits@unsync-overlap.html - shard-tglu: NOTRUN -> [SKIP][117] ([i915#3297]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-7/igt@gem_userptr_blits@unsync-overlap.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][118] ([i915#2724]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb7/igt@gem_userptr_blits@vma-merge.html * igt@gem_vm_create@invalid-create: - shard-snb: NOTRUN -> [SKIP][119] ([fdo#109271]) +429 other tests skip [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb5/igt@gem_vm_create@invalid-create.html * igt@gen3_render_mixed_blits: - shard-dg1: NOTRUN -> [SKIP][120] ([fdo#109289]) +1 other test skip [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@gen3_render_mixed_blits.html * igt@gen7_exec_parse@bitmasks: - shard-dg2: NOTRUN -> [SKIP][121] ([fdo#109289]) +3 other tests skip [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@gen7_exec_parse@bitmasks.html - shard-rkl: NOTRUN -> [SKIP][122] ([fdo#109289]) +2 other tests skip [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@gen7_exec_parse@bitmasks.html * igt@gen9_exec_parse@batch-invalid-length: - shard-rkl: NOTRUN -> [SKIP][123] ([i915#2527]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html - shard-dg1: NOTRUN -> [SKIP][124] ([i915#2527]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@gen9_exec_parse@batch-invalid-length.html - shard-tglu: NOTRUN -> [SKIP][125] ([i915#2527] / [i915#2856]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@gen9_exec_parse@batch-invalid-length.html - shard-mtlp: NOTRUN -> [SKIP][126] ([i915#2856]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@gen9_exec_parse@batch-invalid-length.html - shard-dg2: NOTRUN -> [SKIP][127] ([i915#2856]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@gen9_exec_parse@batch-invalid-length.html * igt@i915_module_load@load: - shard-snb: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#6227]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb6/igt@i915_module_load@load.html - shard-dg1: NOTRUN -> [SKIP][129] ([i915#6227]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@i915_module_load@load.html - shard-tglu: NOTRUN -> [SKIP][130] ([i915#6227]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@i915_module_load@load.html - shard-glk: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#6227]) [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk8/igt@i915_module_load@load.html - shard-mtlp: NOTRUN -> [SKIP][132] ([i915#6227]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@i915_module_load@load.html - shard-dg2: NOTRUN -> [SKIP][133] ([i915#6227]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@i915_module_load@load.html - shard-rkl: NOTRUN -> [SKIP][134] ([i915#6227]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@i915_module_load@load.html * igt@i915_module_load@reload-with-fault-injection: - shard-tglu: NOTRUN -> [INCOMPLETE][135] ([i915#9200]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pipe_stress@stress-xrgb8888-ytiled: - shard-dg2: NOTRUN -> [SKIP][136] ([i915#7091]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html - shard-mtlp: NOTRUN -> [SKIP][137] ([i915#8436]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html * igt@i915_pm_rps@thresholds-idle-park@gt0: - shard-dg2: NOTRUN -> [SKIP][138] ([i915#8925]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@i915_pm_rps@thresholds-idle-park@gt0.html - shard-dg1: NOTRUN -> [SKIP][139] ([i915#8925]) [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@i915_pm_rps@thresholds-idle-park@gt0.html * igt@i915_query@hwconfig_table: - shard-tglu: NOTRUN -> [SKIP][140] ([i915#6245]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@i915_query@hwconfig_table.html - shard-rkl: NOTRUN -> [SKIP][141] ([i915#6245]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@i915_query@hwconfig_table.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - shard-dg2: NOTRUN -> [SKIP][142] ([i915#4212]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html * igt@kms_addfb_basic@tile-pitch-mismatch: - shard-dg1: NOTRUN -> [SKIP][143] ([i915#4212]) +1 other test skip [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@kms_addfb_basic@tile-pitch-mismatch.html - shard-mtlp: NOTRUN -> [SKIP][144] ([i915#4212]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@kms_addfb_basic@tile-pitch-mismatch.html - shard-dg2: NOTRUN -> [SKIP][145] ([i915#4212] / [i915#5608]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_atomic@plane-primary-overlay-mutable-zpos: - shard-mtlp: NOTRUN -> [SKIP][146] ([i915#3555]) [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html - shard-dg2: NOTRUN -> [SKIP][147] ([i915#9531]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html - shard-rkl: NOTRUN -> [SKIP][148] ([i915#9531]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html - shard-tglu: NOTRUN -> [SKIP][149] ([i915#9531]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-mtlp: NOTRUN -> [SKIP][150] ([i915#1769] / [i915#3555]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html * igt@kms_big_fb@4-tiled-16bpp-rotate-0: - shard-rkl: NOTRUN -> [SKIP][151] ([i915#5286]) +6 other tests skip [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html * igt@kms_big_fb@4-tiled-addfb-size-overflow: - shard-dg1: NOTRUN -> [SKIP][152] ([i915#5286]) [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@kms_big_fb@4-tiled-addfb-size-overflow.html - shard-tglu: NOTRUN -> [SKIP][153] ([i915#5286]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@kms_big_fb@4-tiled-addfb-size-overflow.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180: - shard-tglu: NOTRUN -> [SKIP][154] ([fdo#111615] / [i915#5286]) +5 other tests skip [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-dg1: NOTRUN -> [SKIP][155] ([i915#4538] / [i915#5286]) +5 other tests skip [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-mtlp: NOTRUN -> [FAIL][156] ([i915#5138]) +1 other test fail [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][157] ([fdo#111614] / [i915#3638]) +1 other test skip [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-2/igt@kms_big_fb@linear-64bpp-rotate-90.html - shard-mtlp: NOTRUN -> [SKIP][158] ([fdo#111614]) [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_big_fb@linear-64bpp-rotate-90.html - shard-dg2: NOTRUN -> [SKIP][159] ([fdo#111614]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_big_fb@linear-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-64bpp-rotate-90: - shard-dg1: NOTRUN -> [SKIP][160] ([i915#3638]) +1 other test skip [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html - shard-tglu: NOTRUN -> [SKIP][161] ([fdo#111614]) +1 other test skip [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow: - shard-dg2: NOTRUN -> [SKIP][162] ([i915#5190]) +6 other tests skip [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-0: - shard-tglu: NOTRUN -> [SKIP][163] ([fdo#111615]) +5 other tests skip [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html - shard-mtlp: NOTRUN -> [SKIP][164] ([fdo#111615]) +11 other tests skip [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-90: - shard-dg2: NOTRUN -> [SKIP][165] ([i915#4538] / [i915#5190]) +5 other tests skip [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-rkl: NOTRUN -> [SKIP][166] ([fdo#111615]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-rkl: NOTRUN -> [SKIP][167] ([fdo#110723]) +5 other tests skip [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html - shard-dg1: NOTRUN -> [SKIP][168] ([i915#4538]) +5 other tests skip [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_ccs@pipe-a-crc-primary-basic-y-tiled-ccs: - shard-rkl: NOTRUN -> [SKIP][169] ([i915#5354] / [i915#6095]) +16 other tests skip [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@kms_ccs@pipe-a-crc-primary-basic-y-tiled-ccs.html * igt@kms_ccs@pipe-a-random-ccs-data-y-tiled-gen12-rc-ccs: - shard-mtlp: NOTRUN -> [SKIP][170] ([i915#5354] / [i915#6095]) +32 other tests skip [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_ccs@pipe-a-random-ccs-data-y-tiled-gen12-rc-ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-4-tiled-dg2-rc-ccs: - shard-tglu: NOTRUN -> [SKIP][171] ([i915#5354] / [i915#6095]) +25 other tests skip [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-8/igt@kms_ccs@pipe-b-bad-rotation-90-4-tiled-dg2-rc-ccs.html * igt@kms_ccs@pipe-b-bad-rotation-90-y-tiled-gen12-rc-ccs: - shard-dg2: NOTRUN -> [SKIP][172] ([i915#5354]) +55 other tests skip [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@kms_ccs@pipe-b-bad-rotation-90-y-tiled-gen12-rc-ccs.html * igt@kms_ccs@pipe-d-ccs-on-another-bo-4-tiled-mtl-mc-ccs: - shard-rkl: NOTRUN -> [SKIP][173] ([i915#5354]) +23 other tests skip [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_ccs@pipe-d-ccs-on-another-bo-4-tiled-mtl-mc-ccs.html - shard-dg1: NOTRUN -> [SKIP][174] ([i915#5354] / [i915#6095]) +27 other tests skip [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@kms_ccs@pipe-d-ccs-on-another-bo-4-tiled-mtl-mc-ccs.html * igt@kms_chamelium_audio@hdmi-audio: - shard-dg2: NOTRUN -> [SKIP][175] ([i915#7828]) +6 other tests skip [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_chamelium_audio@hdmi-audio.html - shard-rkl: NOTRUN -> [SKIP][176] ([i915#7828]) +7 other tests skip [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_chamelium_audio@hdmi-audio.html - shard-dg1: NOTRUN -> [SKIP][177] ([i915#7828]) +5 other tests skip [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@kms_chamelium_audio@hdmi-audio.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-mtlp: NOTRUN -> [SKIP][178] ([fdo#111827]) +1 other test skip [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_color@ctm-red-to-blue: - shard-rkl: NOTRUN -> [SKIP][179] ([fdo#111827]) +4 other tests skip [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_chamelium_color@ctm-red-to-blue.html - shard-dg1: NOTRUN -> [SKIP][180] ([fdo#111827]) +3 other tests skip [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_chamelium_color@ctm-red-to-blue.html * igt@kms_chamelium_color@degamma: - shard-dg2: NOTRUN -> [SKIP][181] ([fdo#111827]) +3 other tests skip [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_chamelium_color@degamma.html - shard-tglu: NOTRUN -> [SKIP][182] ([fdo#111827]) +2 other tests skip [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_chamelium_color@degamma.html * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe: - shard-tglu: NOTRUN -> [SKIP][183] ([i915#7828]) +6 other tests skip [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode: - shard-mtlp: NOTRUN -> [SKIP][184] ([i915#7828]) +6 other tests skip [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html * igt@kms_content_protection@legacy: - shard-tglu: NOTRUN -> [SKIP][185] ([i915#6944] / [i915#7116] / [i915#7118]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_content_protection@legacy.html - shard-mtlp: NOTRUN -> [SKIP][186] ([i915#6944]) [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@kms_content_protection@legacy.html - shard-rkl: NOTRUN -> [SKIP][187] ([i915#7118]) [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_content_protection@legacy.html - shard-dg1: NOTRUN -> [SKIP][188] ([i915#7116]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_content_protection@legacy.html * igt@kms_content_protection@legacy@pipe-a-dp-4: - shard-dg2: NOTRUN -> [TIMEOUT][189] ([i915#7173]) [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html * igt@kms_cursor_crc@cursor-offscreen-64x21: - shard-mtlp: NOTRUN -> [SKIP][190] ([i915#8814]) +1 other test skip [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@kms_cursor_crc@cursor-offscreen-64x21.html * igt@kms_cursor_crc@cursor-rapid-movement-32x10: - shard-rkl: NOTRUN -> [SKIP][191] ([i915#3555]) +4 other tests skip [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html - shard-mtlp: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8814]) +1 other test skip [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html * igt@kms_cursor_crc@cursor-rapid-movement-512x512: - shard-dg2: NOTRUN -> [SKIP][193] ([i915#3359]) [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html - shard-rkl: NOTRUN -> [SKIP][194] ([i915#3359]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html - shard-dg1: NOTRUN -> [SKIP][195] ([i915#3359]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-tglu: NOTRUN -> [SKIP][196] ([fdo#109274]) +3 other tests skip [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html - shard-mtlp: NOTRUN -> [SKIP][197] ([i915#9809]) +2 other tests skip [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-rkl: NOTRUN -> [SKIP][198] ([fdo#111825]) +11 other tests skip [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions: - shard-dg2: NOTRUN -> [SKIP][199] ([fdo#109274] / [i915#5354]) +3 other tests skip [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html * igt@kms_cursor_legacy@cursora-vs-flipb-legacy: - shard-snb: [PASS][200] -> [SKIP][201] ([fdo#109271]) [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-snb7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-rkl: NOTRUN -> [SKIP][202] ([fdo#111767] / [fdo#111825]) +1 other test skip [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-snb: NOTRUN -> [SKIP][203] ([fdo#109271] / [fdo#111767]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-tglu: NOTRUN -> [SKIP][204] ([fdo#109274] / [fdo#111767]) [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-mtlp: NOTRUN -> [SKIP][205] ([fdo#111767]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-dg2: NOTRUN -> [SKIP][206] ([fdo#109274] / [fdo#111767] / [i915#5354]) [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_dirtyfb@drrs-dirtyfb-ioctl: - shard-dg2: NOTRUN -> [SKIP][207] ([i915#9833]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html - shard-rkl: NOTRUN -> [SKIP][208] ([i915#9723]) [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html - shard-dg1: NOTRUN -> [SKIP][209] ([i915#9723]) [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html - shard-tglu: NOTRUN -> [SKIP][210] ([i915#9723]) [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html - shard-mtlp: NOTRUN -> [SKIP][211] ([i915#9833]) [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][212] ([i915#3804]) [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html - shard-tglu: NOTRUN -> [SKIP][213] ([i915#3804]) [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html * igt@kms_dither@fb-8bpc-vs-panel-8bpc: - shard-dg2: NOTRUN -> [SKIP][214] ([i915#3555]) +6 other tests skip [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html * igt@kms_dp_aux_dev: - shard-rkl: NOTRUN -> [SKIP][215] ([i915#1257]) [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_dp_aux_dev.html - shard-dg1: NOTRUN -> [SKIP][216] ([i915#1257]) [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@kms_dp_aux_dev.html * igt@kms_feature_discovery@psr1: - shard-tglu: NOTRUN -> [SKIP][217] ([i915#658]) +1 other test skip [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-7/igt@kms_feature_discovery@psr1.html - shard-dg2: NOTRUN -> [SKIP][218] ([i915#658]) +1 other test skip [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_feature_discovery@psr1.html - shard-rkl: NOTRUN -> [SKIP][219] ([i915#658]) +1 other test skip [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_feature_discovery@psr1.html * igt@kms_feature_discovery@psr2: - shard-dg1: NOTRUN -> [SKIP][220] ([i915#658]) +1 other test skip [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_feature_discovery@psr2.html * igt@kms_flip@2x-blocking-absolute-wf_vblank: - shard-tglu: NOTRUN -> [SKIP][221] ([fdo#109274] / [i915#3637]) +7 other tests skip [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@kms_flip@2x-blocking-absolute-wf_vblank.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-mtlp: NOTRUN -> [SKIP][222] ([i915#3637]) +7 other tests skip [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@kms_flip@2x-flip-vs-expired-vblank.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-mtlp: NOTRUN -> [SKIP][223] ([fdo#111767] / [i915#3637]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html - shard-dg2: NOTRUN -> [SKIP][224] ([fdo#109274] / [fdo#111767]) [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html - shard-dg1: NOTRUN -> [SKIP][225] ([fdo#111767] / [fdo#111825]) [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html - shard-tglu: NOTRUN -> [SKIP][226] ([fdo#109274] / [fdo#111767] / [i915#3637]) [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-dg2: NOTRUN -> [SKIP][227] ([fdo#109274]) +7 other tests skip [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@kms_flip@2x-modeset-vs-vblank-race.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][228] ([i915#2672]) +3 other tests skip [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][229] ([i915#3555] / [i915#8810]) [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][230] ([i915#2672]) +3 other tests skip [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode: - shard-tglu: NOTRUN -> [SKIP][231] ([i915#2587] / [i915#2672]) +3 other tests skip [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode: - shard-dg1: NOTRUN -> [SKIP][232] ([i915#2587] / [i915#2672]) +3 other tests skip [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][233] ([i915#2672] / [i915#3555]) +1 other test skip [233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][234] ([i915#2672]) +4 other tests skip [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu: - shard-mtlp: NOTRUN -> [SKIP][235] ([i915#1825]) +20 other tests skip [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt: - shard-rkl: NOTRUN -> [SKIP][236] ([fdo#111825] / [i915#1825]) +30 other tests skip [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-dg2: NOTRUN -> [SKIP][237] ([i915#3458]) +18 other tests skip [237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - shard-tglu: NOTRUN -> [SKIP][238] ([fdo#110189]) +22 other tests skip [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu: - shard-dg1: NOTRUN -> [SKIP][239] ([fdo#111825]) +26 other tests skip [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][240] ([i915#8708]) +10 other tests skip [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-dg1: NOTRUN -> [SKIP][241] ([i915#3458]) +17 other tests skip [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-rkl: NOTRUN -> [SKIP][242] ([i915#3023]) +24 other tests skip [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt: - shard-tglu: NOTRUN -> [SKIP][243] ([fdo#109280]) +27 other tests skip [243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][244] ([i915#8708]) +14 other tests skip [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc: - shard-dg1: NOTRUN -> [SKIP][245] ([i915#8708]) +13 other tests skip [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html * igt@kms_getfb@getfb-reject-ccs: - shard-dg2: NOTRUN -> [SKIP][246] ([i915#6118]) [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-5/igt@kms_getfb@getfb-reject-ccs.html * igt@kms_hdr@static-toggle-dpms: - shard-mtlp: NOTRUN -> [SKIP][247] ([i915#3555] / [i915#8228]) +1 other test skip [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@kms_hdr@static-toggle-dpms.html * igt@kms_hdr@static-toggle-suspend: - shard-dg2: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8228]) +1 other test skip [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@kms_hdr@static-toggle-suspend.html - shard-rkl: NOTRUN -> [SKIP][249] ([i915#3555] / [i915#8228]) +1 other test skip [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@kms_hdr@static-toggle-suspend.html - shard-dg1: NOTRUN -> [SKIP][250] ([i915#3555] / [i915#8228]) +1 other test skip [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@kms_hdr@static-toggle-suspend.html - shard-tglu: NOTRUN -> [SKIP][251] ([i915#3555] / [i915#8228]) +1 other test skip [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@kms_hdr@static-toggle-suspend.html * igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1: - shard-mtlp: NOTRUN -> [SKIP][252] ([i915#9457]) +3 other tests skip [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1.html * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: - shard-tglu: NOTRUN -> [SKIP][253] ([fdo#109289]) +2 other tests skip [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html - shard-mtlp: NOTRUN -> [SKIP][254] ([fdo#109289]) +2 other tests skip [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1: - shard-glk: NOTRUN -> [FAIL][255] ([i915#4573]) +1 other test fail [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk3/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html * igt@kms_plane_lowres@tiling-none@pipe-b-edp-1: - shard-mtlp: NOTRUN -> [SKIP][256] ([i915#3582]) +3 other tests skip [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html * igt@kms_plane_lowres@tiling-y: - shard-mtlp: NOTRUN -> [SKIP][257] ([i915#3555] / [i915#8821]) [257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@kms_plane_lowres@tiling-y.html - shard-dg2: NOTRUN -> [SKIP][258] ([i915#8821]) [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@kms_plane_lowres@tiling-y.html * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][259] ([i915#9423]) +3 other tests skip [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-14/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a-hdmi-a-4.html * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][260] ([i915#9423]) +7 other tests skip [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-7/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1.html * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][261] ([i915#9423]) +3 other tests skip [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][262] ([fdo#109271]) +150 other tests skip [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html - shard-rkl: NOTRUN -> [SKIP][263] ([i915#5235]) +3 other tests skip [263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][264] ([i915#5235]) +3 other tests skip [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][265] ([i915#5235]) +3 other tests skip [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4: - shard-dg1: NOTRUN -> [SKIP][266] ([i915#5235]) +7 other tests skip [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html * igt@kms_pm_dc@dc3co-vpb-simulation: - shard-dg2: NOTRUN -> [SKIP][267] ([i915#9685]) [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@kms_pm_dc@dc3co-vpb-simulation.html - shard-rkl: NOTRUN -> [SKIP][268] ([i915#9685]) [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_pm_dc@dc3co-vpb-simulation.html - shard-dg1: NOTRUN -> [SKIP][269] ([i915#9685]) [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-18/igt@kms_pm_dc@dc3co-vpb-simulation.html - shard-tglu: NOTRUN -> [SKIP][270] ([i915#9685]) [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@kms_pm_dc@dc3co-vpb-simulation.html - shard-mtlp: NOTRUN -> [SKIP][271] ([i915#9292]) [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-5/igt@kms_pm_dc@dc3co-vpb-simulation.html * igt@kms_pm_rpm@dpms-non-lpsp: - shard-rkl: [PASS][272] -> [SKIP][273] ([i915#9519]) [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-rkl-1/igt@kms_pm_rpm@dpms-non-lpsp.html [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-tglu: NOTRUN -> [SKIP][274] ([i915#9683]) +2 other tests skip [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html - shard-rkl: NOTRUN -> [SKIP][275] ([i915#9683]) +2 other tests skip [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: - shard-dg1: NOTRUN -> [SKIP][276] ([i915#9683]) +2 other tests skip [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-tglu: NOTRUN -> [SKIP][277] ([fdo#111068] / [i915#9683]) [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_su@page_flip-p010: - shard-dg2: NOTRUN -> [SKIP][278] ([i915#9683]) +2 other tests skip [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-3/igt@kms_psr2_su@page_flip-p010.html - shard-rkl: NOTRUN -> [SKIP][279] ([fdo#111068] / [i915#9683]) +1 other test skip [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_psr2_su@page_flip-p010.html - shard-dg1: NOTRUN -> [SKIP][280] ([fdo#111068] / [i915#9683]) [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@kms_psr2_su@page_flip-p010.html - shard-tglu: NOTRUN -> [SKIP][281] ([fdo#109642] / [fdo#111068] / [i915#9683]) [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_psr2_su@page_flip-p010.html * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0: - shard-mtlp: NOTRUN -> [SKIP][282] ([i915#4235]) [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html * igt@kms_scaling_modes@scaling-mode-center: - shard-dg1: NOTRUN -> [SKIP][283] ([i915#3555]) +6 other tests skip [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@kms_scaling_modes@scaling-mode-center.html - shard-tglu: NOTRUN -> [SKIP][284] ([i915#3555]) +3 other tests skip [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@kms_scaling_modes@scaling-mode-center.html * igt@kms_tv_load_detect@load-detect: - shard-tglu: NOTRUN -> [SKIP][285] ([fdo#109309]) [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_tv_load_detect@load-detect.html - shard-mtlp: NOTRUN -> [SKIP][286] ([fdo#109309]) [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-3/igt@kms_tv_load_detect@load-detect.html - shard-dg2: NOTRUN -> [SKIP][287] ([fdo#109309]) [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@kms_tv_load_detect@load-detect.html - shard-rkl: NOTRUN -> [SKIP][288] ([fdo#109309]) [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@kms_tv_load_detect@load-detect.html - shard-dg1: NOTRUN -> [SKIP][289] ([fdo#109309]) [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-15/igt@kms_tv_load_detect@load-detect.html * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [FAIL][290] ([i915#9196]) +2 other tests fail [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html * igt@kms_vrr@flip-suspend: - shard-mtlp: NOTRUN -> [SKIP][291] ([i915#3555] / [i915#8808]) [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-6/igt@kms_vrr@flip-suspend.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-dg2: NOTRUN -> [SKIP][292] ([i915#2437] / [i915#9412]) [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-10/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-rkl: NOTRUN -> [SKIP][293] ([i915#2437] / [i915#9412]) [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-dg1: NOTRUN -> [SKIP][294] ([i915#2437] / [i915#9412]) [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-12/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-tglu: NOTRUN -> [SKIP][295] ([i915#2437] / [i915#9412]) [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-10/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-glk: NOTRUN -> [SKIP][296] ([fdo#109271] / [i915#2437]) [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk7/igt@kms_writeback@writeback-check-output-xrgb2101010.html - shard-mtlp: NOTRUN -> [SKIP][297] ([i915#2437] / [i915#9412]) [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@perf@create-destroy-userspace-config: - shard-dg2: NOTRUN -> [ABORT][298] ([i915#9847]) [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@perf@create-destroy-userspace-config.html * igt@perf@gen12-oa-tlb-invalidate@0-rcs0: - shard-mtlp: NOTRUN -> [ABORT][299] ([i915#9847]) +3 other tests abort [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@perf@gen12-oa-tlb-invalidate@0-rcs0.html * igt@perf@stress-open-close@0-rcs0: - shard-glk: NOTRUN -> [ABORT][300] ([i915#9847]) +1 other test abort [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk1/igt@perf@stress-open-close@0-rcs0.html - shard-rkl: NOTRUN -> [ABORT][301] ([i915#9847]) [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@perf@stress-open-close@0-rcs0.html * igt@perf_pmu@all-busy-check-all: - shard-dg2: NOTRUN -> [ABORT][302] ([i915#9847] / [i915#9853]) +2 other tests abort [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@perf_pmu@all-busy-check-all.html - shard-rkl: NOTRUN -> [ABORT][303] ([i915#9847] / [i915#9853]) [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-6/igt@perf_pmu@all-busy-check-all.html * igt@perf_pmu@busy-accuracy-2@rcs0: - shard-dg2: NOTRUN -> [INCOMPLETE][304] ([i915#9853]) +1 other test incomplete [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@perf_pmu@busy-accuracy-2@rcs0.html - shard-rkl: NOTRUN -> [INCOMPLETE][305] ([i915#9853]) +3 other tests incomplete [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@perf_pmu@busy-accuracy-2@rcs0.html - shard-dg1: NOTRUN -> [INCOMPLETE][306] ([i915#9853]) +3 other tests incomplete [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-16/igt@perf_pmu@busy-accuracy-2@rcs0.html * igt@perf_pmu@idle-no-semaphores@rcs0: - shard-tglu: NOTRUN -> [INCOMPLETE][307] ([i915#9853]) +3 other tests incomplete [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-7/igt@perf_pmu@idle-no-semaphores@rcs0.html - shard-glk: NOTRUN -> [INCOMPLETE][308] ([i915#9853]) +3 other tests incomplete [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk3/igt@perf_pmu@idle-no-semaphores@rcs0.html - shard-mtlp: NOTRUN -> [ABORT][309] ([i915#9847] / [i915#9853]) +4 other tests abort [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-4/igt@perf_pmu@idle-no-semaphores@rcs0.html * igt@perf_pmu@interrupts-sync: - shard-snb: NOTRUN -> [INCOMPLETE][310] ([i915#9853]) +7 other tests incomplete [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb4/igt@perf_pmu@interrupts-sync.html * igt@perf_pmu@module-unload: - shard-dg2: NOTRUN -> [FAIL][311] ([i915#5793]) [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-7/igt@perf_pmu@module-unload.html * igt@perf_pmu@semaphore-wait@rcs0: - shard-glk: NOTRUN -> [ABORT][312] ([i915#9847] / [i915#9853]) [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk1/igt@perf_pmu@semaphore-wait@rcs0.html * igt@prime_udl: - shard-tglu: NOTRUN -> [SKIP][313] ([fdo#109291]) [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-3/igt@prime_udl.html - shard-mtlp: NOTRUN -> [SKIP][314] ([fdo#109291]) [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-1/igt@prime_udl.html - shard-dg2: NOTRUN -> [SKIP][315] ([fdo#109291]) [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@prime_udl.html - shard-rkl: NOTRUN -> [SKIP][316] ([fdo#109291]) [316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@prime_udl.html * igt@syncobj_wait@invalid-wait-zero-handles: - shard-mtlp: NOTRUN -> [FAIL][317] ([i915#9779]) [317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-8/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-dg2: NOTRUN -> [FAIL][318] ([i915#9779]) [318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-1/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-rkl: NOTRUN -> [FAIL][319] ([i915#9779]) [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-1/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-dg1: NOTRUN -> [FAIL][320] ([i915#9779]) [320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-19/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-snb: NOTRUN -> [FAIL][321] ([i915#9779]) [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb5/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-tglu: NOTRUN -> [FAIL][322] ([i915#9779]) [322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-4/igt@syncobj_wait@invalid-wait-zero-handles.html - shard-glk: NOTRUN -> [FAIL][323] ([i915#9779]) [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-glk7/igt@syncobj_wait@invalid-wait-zero-handles.html * igt@v3d/v3d_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][324] ([i915#2575]) +11 other tests skip [324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-2/igt@v3d/v3d_perfmon@create-perfmon-exceed.html * igt@v3d/v3d_perfmon@get-values-valid-perfmon: - shard-rkl: NOTRUN -> [SKIP][325] ([fdo#109315]) +13 other tests skip [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-5/igt@v3d/v3d_perfmon@get-values-valid-perfmon.html * igt@v3d/v3d_submit_cl@bad-extension: - shard-dg1: NOTRUN -> [SKIP][326] ([i915#2575]) +11 other tests skip [326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@v3d/v3d_submit_cl@bad-extension.html * igt@v3d/v3d_submit_cl@simple-flush-cache: - shard-dg2: NOTRUN -> [SKIP][327] ([i915#2575]) +12 other tests skip [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-6/igt@v3d/v3d_submit_cl@simple-flush-cache.html * igt@v3d/v3d_submit_csd@multiple-job-submission: - shard-tglu: NOTRUN -> [SKIP][328] ([fdo#109315] / [i915#2575]) +12 other tests skip [328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@v3d/v3d_submit_csd@multiple-job-submission.html * igt@vc4/vc4_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][329] ([i915#7711]) +8 other tests skip [329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-mtlp-7/igt@vc4/vc4_perfmon@create-perfmon-exceed.html * igt@vc4/vc4_purgeable_bo@mark-purgeable-twice: - shard-dg2: NOTRUN -> [SKIP][330] ([i915#7711]) +8 other tests skip [330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg2-11/igt@vc4/vc4_purgeable_bo@mark-purgeable-twice.html * igt@vc4/vc4_tiling@set-bad-handle: - shard-rkl: NOTRUN -> [SKIP][331] ([i915#7711]) +9 other tests skip [331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-rkl-7/igt@vc4/vc4_tiling@set-bad-handle.html * igt@vc4/vc4_wait_bo@unused-bo-0ns: - shard-dg1: NOTRUN -> [SKIP][332] ([i915#7711]) +8 other tests skip [332]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-17/igt@vc4/vc4_wait_bo@unused-bo-0ns.html * igt@vc4/vc4_wait_seqno@bad-seqno-0ns: - shard-tglu: NOTRUN -> [SKIP][333] ([i915#2575]) +8 other tests skip [333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-tglu-5/igt@vc4/vc4_wait_seqno@bad-seqno-0ns.html #### Possible fixes #### * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size: - shard-snb: [SKIP][334] ([fdo#109271]) -> [PASS][335] [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-snb6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html [335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-snb7/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html #### Warnings #### * igt@perf_pmu@module-unload: - shard-dg1: [INCOMPLETE][336] ([i915#9853]) -> [ABORT][337] ([i915#9847] / [i915#9853]) [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14030/shard-dg1-16/igt@perf_pmu@module-unload.html [337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/shard-dg1-13/igt@perf_pmu@module-unload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107 [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793 [i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#7091]: https://gitlab.freedesktop.org/drm/intel/issues/7091 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173 [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289 [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8436]: https://gitlab.freedesktop.org/drm/intel/issues/8436 [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808 [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810 [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814 [i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821 [i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898 [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925 [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196 [i915#9200]: https://gitlab.freedesktop.org/drm/intel/issues/9200 [i915#9292]: https://gitlab.freedesktop.org/drm/intel/issues/9292 [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318 [i915#9364]: https://gitlab.freedesktop.org/drm/intel/issues/9364 [i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412 [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423 [i915#9457]: https://gitlab.freedesktop.org/drm/intel/issues/9457 [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519 [i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531 [i915#9618]: https://gitlab.freedesktop.org/drm/intel/issues/9618 [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673 [i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683 [i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685 [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688 [i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723 [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732 [i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779 [i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808 [i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809 [i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833 [i915#9847]: https://gitlab.freedesktop.org/drm/intel/issues/9847 [i915#9853]: https://gitlab.freedesktop.org/drm/intel/issues/9853 [i915#9855]: https://gitlab.freedesktop.org/drm/intel/issues/9855 [i915#9856]: https://gitlab.freedesktop.org/drm/intel/issues/9856 [i915#9857]: https://gitlab.freedesktop.org/drm/intel/issues/9857 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7643 -> IGTPW_10429 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_14030: 0896a36d44111936050697e425e1b903e91a1178 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_10429: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html IGT_7643: ced22f8bf4263ff395dc852c86b682e62a7a1c1b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10429/index.html [-- Attachment #2: Type: text/html, Size: 111505 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-12-16 0:22 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-15 15:50 [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Francois Dugast 2023-12-15 15:50 ` [PATCH v1 01/10] drm-uapi/xe: Align header with current kernel uAPI Francois Dugast 2023-12-15 15:50 ` [PATCH v1 02/10] drm-uapi/xe: add exec_queue_id member to drm_xe_wait_user_fence structure Francois Dugast 2023-12-15 15:50 ` [PATCH v1 03/10] drm-uapi/xe: Don't wait on user_fence during exec queue reset Francois Dugast 2023-12-15 15:50 ` [PATCH v1 04/10] drm-uapi/xe: Remove DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY Francois Dugast 2023-12-15 15:50 ` [PATCH v1 05/10] drm-uapi/xe: Remove DRM_XE_UFENCE_WAIT_MASK_* Francois Dugast 2023-12-15 15:50 ` [PATCH v1 06/10] drm-uapi/xe: Remove PMU from Xe till uapi is finalized Francois Dugast 2023-12-15 15:50 ` [PATCH v1 07/10] drm-uapi/xe: Ensure every uapi struct has drm_xe prefix Francois Dugast 2023-12-15 15:50 ` [PATCH v1 08/10] drm-uapi/xe: Remove sync binds Francois Dugast 2023-12-15 15:50 ` [PATCH v1 09/10] drm-uapi/xe: Update header after documentation updates Francois Dugast 2023-12-15 15:50 ` [PATCH v1 10/10] tests/intel/xe: Remove xe_uevent for now Francois Dugast 2023-12-15 15:56 ` [PATCH v1 00/10] uAPI Alignment - More cleanup before upstream Dixit, Ashutosh 2023-12-15 16:48 ` Rodrigo Vivi 2023-12-15 16:35 ` ✓ Fi.CI.BAT: success for uAPI Alignment - More cleanup before upstream (rev3) Patchwork 2023-12-15 16:59 ` ✗ CI.xeBAT: failure " Patchwork 2023-12-16 0:22 ` ✗ Fi.CI.IGT: " Patchwork
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