Igt-dev Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: ✗ CI.xeFULL: failure for Intel Xe OA IGT's (rev7)
Date: Mon, 01 Jul 2024 16:08:52 -0700	[thread overview]
Message-ID: <87v81oaewr.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <ZoMJ7KGCzPeR+M06@orsosgc001>

On Mon, 01 Jul 2024 12:56:28 -0700, Umesh Nerlige Ramappa wrote:
>
> >  IGT changes
> >
> >    Possible regressions
> >
> >     * igt@kms_pm_rpm@i2c:
> >
> >          * shard-dg2-set2: [3]PASS -> [4]FAIL
> >
> >     * {igt@xe_oa@non-zero-reason@rcs-0} (NEW):
> >
> >          * shard-dg2-set2: NOTRUN -> [5]FAIL +1 other test fail
>
> This is something that is an open bug even in i915 and will fail with Xe as
> well. Should we even merge this test as it will create a bunch of JIRAs
> every now and then.

I am also thinking what to do about these failures. There are more in
"CI.xeBAT" (since the HAX patch added the tests to
xe-fast-feedback.testlist, though this will not happen in real CI):

	Possible regressions

	* {igt@xe_oa@mi-rpc} (NEW):

	 * bat-atsm-2: NOTRUN -> INCOMPLETE +1 other test incomplete

	* {igt@xe_oa@mi-rpc@ccs-0} (NEW):

	 * bat-pvc-2: NOTRUN -> INCOMPLETE +1 other test incomplete
	 * bat-dg2-oem2: NOTRUN -> INCOMPLETE +1 other test incomplete

	* {igt@xe_oa@mmio-triggered-reports} (NEW):

	 * bat-adlp-7: NOTRUN -> SKIP

	* {igt@xe_oa@non-zero-reason} (NEW):

	 * bat-pvc-2: NOTRUN -> FAIL +6 other tests fail
	 * bat-dg2-oem2: NOTRUN -> FAIL +1 other test fail

	* {igt@xe_oa@oa-formats} (NEW):

	 * bat-pvc-2: NOTRUN -> TIMEOUT +1 other test timeout

	* {igt@xe_oa@oa-tlb-invalidate} (NEW):

	 * {bat-lnl-1}: NOTRUN -> SKIP +1 other test skip
	 * bat-pvc-2: NOTRUN -> SKIP +1 other test skip

	* {igt@xe_oa@polling-small-buf} (NEW):

	 * bat-atsm-2: NOTRUN -> FAIL

	* {igt@xe_oa@rc6-disable} (NEW):

	 * bat-atsm-2: NOTRUN -> SKIP

Mostly similar to those we see in i915 for Xe1.

One idea is to run these xe_oa IGT's only for Xe2 where things seem to be
more stable, that is only for xe KMD supported platforms. Things seem to be
more stable for Xe2, maybe because we don't know how to check Xe2 PEC
counters, like we do for Xe1 in sanity_check_reports. Or simplify the
checks for Xe1, e.g. get rid of sanity_check_reports? And simplify some of
the other asserts.

Or merge these first and as part of fixing the bugs see what to do for the
tests, so that we'll have a record in git of what we did and why?

Thanks.
--
Ashutosh

  reply	other threads:[~2024-07-01 23:13 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-01  2:52 [PATCH i-g-t v7 00/14] Intel Xe OA IGT's Ashutosh Dixit
2024-07-01  2:52 ` [PATCH i-g-t 01/14] lib/xe/oa: Add PVC support Ashutosh Dixit
2024-07-01 19:52   ` Umesh Nerlige Ramappa
2024-07-01  2:52 ` [PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests Ashutosh Dixit
2024-07-01 16:53   ` Dixit, Ashutosh
2024-07-01 19:47   ` Umesh Nerlige Ramappa
2024-07-01 22:31     ` Dixit, Ashutosh
2024-07-01  2:52 ` [PATCH i-g-t 03/14] tests/intel/xe_oa: Add some negative tests Ashutosh Dixit
2024-07-01  2:52 ` [PATCH i-g-t 04/14] tests/intel/xe_oa: Add "oa-formats" subtest Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 05/14] tests/intel/xe_oa: Add oa exponent tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 06/14] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 07/14] tests/intel/xe_oa: blocking and polling tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 08/14] tests/intel/xe_oa: OAR/OAC tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 09/14] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 10/14] tests/intel/xe_oa: add remove OA config tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 11/14] tests/intel/xe_oa: OA buffer mmap tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 12/14] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests Ashutosh Dixit
2024-07-01  2:53 ` [PATCH i-g-t 13/14] tests/intel/xe_oa: Drop "xe-ref-count" subtest Ashutosh Dixit
2024-07-01 19:53   ` Umesh Nerlige Ramappa
2024-07-01  2:53 ` [PATCH i-g-t 14/14] HAX: Add Xe OA tests to xe-fast-feedback.testlist Ashutosh Dixit
2024-07-01  3:23 ` ✓ CI.xeBAT: success for Intel Xe OA IGT's (rev7) Patchwork
2024-07-01  3:31 ` ✓ Fi.CI.BAT: " Patchwork
2024-07-01  5:00 ` ✗ CI.xeFULL: failure " Patchwork
2024-07-01 19:56   ` Umesh Nerlige Ramappa
2024-07-01 23:08     ` Dixit, Ashutosh [this message]
2024-07-01  5:36 ` ✗ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87v81oaewr.wl-ashutosh.dixit@intel.com \
    --to=ashutosh.dixit@intel.com \
    --cc=igt-dev@lists.freedesktop.org \
    --cc=umesh.nerlige.ramappa@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox