[igt-dev] [PATCH i-g-t 0/4] Use intel_cmds_info in i915_pm_rpm

[igt-dev] [PATCH i-g-t 0/4] Use intel_cmds_info in i915_pm_rpm

[Karolina Stolarek]

i915_pm_rpm test uses XY_COLOR_BLT blitter command which is not
supported in newer generations. This series modifies gem-execbuf
test to switch to fast copy if it can't do a color blit. It also
introduces an updated version of intel_cmds_info library that has
information on XY_COLOR_BLT support. 

Karolina Stolarek (2):
  lib/intel_cmds_info: Drop BLT_CMD_LONG flag
  tests/i915/i915_pm_rpm: Check command property instead of gen

Vikas Srivastava (2):
  lib/i915: Add library support for XY_COLOR_BLT
  tests/i915/i915_pm_rpm: Modify gem-execbuf test for gen12+

 lib/i915/i915_blt.c        |  16 +++
 lib/i915/i915_blt.h        |   1 +
 lib/i915/intel_cmds_info.c |  23 ++++-
 lib/i915/intel_cmds_info.h |   1 +
 tests/i915/i915_pm_rpm.c   | 195 +++++++++++++++++++++++++++++--------
 5 files changed, 191 insertions(+), 45 deletions(-)

-- 
2.25.1

[igt-dev] [PATCH i-g-t 1/4] lib/i915: Add library support for XY_COLOR_BLT

[Karolina Stolarek]

From: Vikas Srivastava <vikas.srivastava@intel.com>

Add API to check support for XY_COLOR_BLT command
in existing library for gen12 and older platforms.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 lib/i915/i915_blt.c        | 16 ++++++++++++++++
 lib/i915/i915_blt.h        |  1 +
 lib/i915/intel_cmds_info.c | 23 ++++++++++++++++++++---
 lib/i915/intel_cmds_info.h |  2 ++
 4 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
index ef67fe26f..b9a5f8e19 100644
--- a/lib/i915/i915_blt.c
+++ b/lib/i915/i915_blt.c
@@ -317,6 +317,22 @@ bool blt_has_xy_src_copy(int i915)
 	return blt_supports_command(cmds_info, XY_SRC_COPY);
 }
 
+/**
+ * blt_has_xy_color
+ * @i915: drm fd
+ *
+ * Check if XY_COLOR_BLT is supported by @i915 device
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_has_xy_color(int i915)
+{
+	const struct intel_cmds_info *cmds_info = GET_CMDS_INFO(i915);
+
+	return blt_supports_command(cmds_info, XY_COLOR_BLT);
+}
+
 /**
  * blt_fast_copy_supports_tiling
  * @i915: drm fd
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
index a5f0edd15..1e18d15c3 100644
--- a/lib/i915/i915_blt.h
+++ b/lib/i915/i915_blt.h
@@ -169,6 +169,7 @@ bool blt_cmd_has_property(const struct intel_cmds_info *cmds_info,
 bool blt_has_block_copy(int i915);
 bool blt_has_fast_copy(int i915);
 bool blt_has_xy_src_copy(int i915);
+bool blt_has_xy_color(int i915);
 
 bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
 bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
diff --git a/lib/i915/intel_cmds_info.c b/lib/i915/intel_cmds_info.c
index 166fb4740..3ce2fd74b 100644
--- a/lib/i915/intel_cmds_info.c
+++ b/lib/i915/intel_cmds_info.c
@@ -82,24 +82,38 @@ static const struct blt_cmd_info
 						 BIT(T_TILE64),
 						 BLT_CMD_EXTENDED);
 
+static const struct blt_cmd_info
+		gen6_xy_color_blt = BLT_INFO_EXT(XY_COLOR_BLT,
+						 BIT(T_LINEAR) |
+						 BIT(T_YMAJOR) |
+						 BIT(T_XMAJOR),
+						 BLT_CMD_LONG);
+
+static const struct blt_cmd_info
+		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
+						 BIT(T_LINEAR) |
+						 BIT(T_XMAJOR));
+
 const struct intel_cmds_info pre_gen6_cmds_info = {
 	.blt_cmds = {
 		[SRC_COPY] = &src_copy,
-		[XY_SRC_COPY] = &pre_gen6_xy_src_copy
+		[XY_SRC_COPY] = &pre_gen6_xy_src_copy,
+		[XY_COLOR_BLT] = &pre_gen6_xy_color_blt,
 	}
 };
 
 const struct intel_cmds_info gen6_cmds_info =  {
 	.blt_cmds = {
 		[SRC_COPY] = &src_copy,
-		[XY_SRC_COPY] = &gen6_xy_src_copy
+		[XY_SRC_COPY] = &gen6_xy_src_copy,
+		[XY_COLOR_BLT] = &gen6_xy_color_blt,
 	}
-
 };
 
 const struct intel_cmds_info gen8_cmds_info = {
 	.blt_cmds = {
 		[XY_SRC_COPY] = &gen6_xy_src_copy,
+		[XY_COLOR_BLT] = &gen6_xy_color_blt,
 	}
 };
 
@@ -107,6 +121,7 @@ const struct intel_cmds_info gen11_cmds_info = {
 	.blt_cmds = {
 		[XY_SRC_COPY] = &gen6_xy_src_copy,
 		[XY_FAST_COPY] = &gen11_xy_fast_copy,
+		[XY_COLOR_BLT] = &gen6_xy_color_blt,
 	}
 };
 
@@ -115,6 +130,7 @@ const struct intel_cmds_info gen12_cmds_info = {
 		[XY_SRC_COPY] = &gen6_xy_src_copy,
 		[XY_FAST_COPY] = &gen12_xy_fast_copy,
 		[XY_BLOCK_COPY] = &gen12_xy_block_copy,
+		[XY_COLOR_BLT] = &gen6_xy_color_blt,
 	}
 };
 
@@ -123,6 +139,7 @@ const struct intel_cmds_info gen12_dg2_cmds_info = {
 		[XY_SRC_COPY] = &gen6_xy_src_copy,
 		[XY_FAST_COPY] = &dg2_xy_fast_copy,
 		[XY_BLOCK_COPY] = &dg2_xy_block_copy,
+		[XY_COLOR_BLT] = &gen6_xy_color_blt,
 	}
 };
 
diff --git a/lib/i915/intel_cmds_info.h b/lib/i915/intel_cmds_info.h
index 1db8709f8..5998a35ca 100644
--- a/lib/i915/intel_cmds_info.h
+++ b/lib/i915/intel_cmds_info.h
@@ -23,6 +23,7 @@ enum blt_cmd_type {
 	XY_SRC_COPY,
 	XY_FAST_COPY,
 	XY_BLOCK_COPY,
+	XY_COLOR_BLT,
 	__BLT_MAX_CMD
 };
 
@@ -33,6 +34,7 @@ struct blt_cmd_info {
 	uint32_t flags;
 #define BLT_CMD_EXTENDED               (1 << 0)
 #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
+#define BLT_CMD_LONG                   (1 << 2)
 };
 
 struct intel_cmds_info {
-- 
2.25.1

[igt-dev] [PATCH i-g-t 2/4] tests/i915/i915_pm_rpm: Modify gem-execbuf test for gen12+

[Karolina Stolarek]

From: Vikas Srivastava <vikas.srivastava@intel.com>

xy_color_blt is not supported on MTL and other gen12+ target
hence an IGT test update needs to be done. Modify the test
to add a lib API to check for xy_color_blt support.

Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 tests/i915/i915_pm_rpm.c | 185 ++++++++++++++++++++++++++++++---------
 1 file changed, 146 insertions(+), 39 deletions(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index d9b4cbbfe..b23eba544 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -243,6 +243,7 @@
 #include "igt_debugfs.h"
 #include "igt_device.h"
 #include "igt_edid.h"
+#include "i915/i915_blt.h"
 
 #define MSR_PC8_RES	0x630
 #define MSR_PC9_RES	0x631
@@ -252,6 +253,11 @@
 #define MAX_ENCODERS	32
 #define MAX_CRTCS	16
 
+#define WIDTH 64
+#define HEIGHT 64
+#define STRIDE (WIDTH)
+#define SIZE (HEIGHT * STRIDE)
+
 enum pc8_status {
 	PC8_ENABLED,
 	PC8_DISABLED
@@ -308,10 +314,57 @@ struct modeset_params {
 	drmModeModeInfoPtr mode;
 };
 
+struct data_t {
+	int width;
+	int height;
+	uint32_t region;
+};
+
 struct modeset_params lpsp_mode_params;
 struct modeset_params non_lpsp_mode_params;
 struct modeset_params *default_mode_params;
 
+/* API to create mmap buffer */
+static struct intel_buf *
+create_buf(struct data_t *data, uint32_t color)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	uint32_t handle;
+	struct buf_ops *bops;
+	int i;
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+	bops = buf_ops_create(drm_fd);
+
+	handle = gem_create_in_memory_regions(drm_fd, SIZE, data->region);
+	intel_buf_init_using_handle(bops, handle, buf,
+				    data->width / 4, data->height, 32, 0,
+				    I915_TILING_NONE, 0);
+
+	ptr = gem_mmap__cpu_coherent(drm_fd, buf->handle, 0,
+				     buf->surface[0].size, PROT_WRITE);
+
+	for (i = 0; i < buf->surface[0].size; i++)
+		ptr[i] = color;
+
+	munmap(ptr, buf->surface[0].size);
+
+	return buf;
+}
+
+/* checking the buffer content is correct or not */
+static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
+{
+	uint8_t val;
+
+	val = ptr[y * WIDTH + x];
+	igt_assert_f(val == color,
+		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+		     color, val, x, y);
+}
+
 static int modprobe(const char *driver)
 {
 	return igt_kmod_load(driver, NULL);
@@ -1522,7 +1575,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
 /* Make sure we can submit a batch buffer and verify its result. */
 static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_regions)
 {
-	int x, y;
+	int x, y, i, j;
 	uint32_t handle;
 	int bpp = 4;
 	int pitch = 128 * bpp;
@@ -1531,10 +1584,31 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
 	uint32_t presumed_offset = 0;
 	int sq_x = 5, sq_y = 10, sq_w = 15, sq_h = 20;
 	uint32_t color;
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	struct data_t data = {0, };
+	struct igt_collection *region;
+	struct drm_i915_query_memory_regions *region_info;
+	struct igt_collection *region_set;
+	uint32_t id;
 
 	igt_require_gem(drm_fd);
 	gem_require_blitter(drm_fd);
 
+	region_info = gem_get_query_memory_regions(drm_fd);
+	igt_assert(region_info);
+	region_set = get_memory_region_set(region_info,
+					   I915_SYSTEM_MEMORY,
+					   I915_DEVICE_MEMORY);
+	for_each_combination(region, 1, region_set) {
+		id = igt_collection_get_value(region, 0);
+		break;
+	}
+
+	data.width = WIDTH;
+	data.height = HEIGHT;
+	data.region = id;
+
 	/* Create and set data while the device is active. */
 	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
 
@@ -1549,62 +1623,95 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
 	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
 
 	color = 0x12345678;
-	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
-		       &presumed_offset);
-	igt_assert(wait_for_suspended());
+	if (blt_has_xy_color(drm_fd)) {
+		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
+			       &presumed_offset);
+		igt_assert(wait_for_suspended());
 
-	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
-	igt_assert(wait_for_suspended());
-	for (y = 0; y < 128; y++) {
-		for (x = 0; x < 128; x++) {
-			uint32_t px = cpu_buf[y * 128 + x];
+		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
+		for (y = 0; y < 128; y++) {
+			for (x = 0; x < 128; x++) {
+				uint32_t px = cpu_buf[y * 128 + x];
 
-			if (y >= sq_y && y < (sq_y + sq_h) &&
-			    x >= sq_x && x < (sq_x + sq_w))
-				igt_assert_eq_u32(px, color);
-			else
-				igt_assert(px == 0);
+				if (y >= sq_y && y < (sq_y + sq_h) &&
+				    x >= sq_x && x < (sq_x + sq_w))
+					igt_assert_eq_u32(px, color);
+				else
+					igt_assert(px == 0);
+			}
 		}
+	} else {
+		buf = create_buf(&data, color);
+		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
+						buf->surface[0].size, PROT_READ);
+		igt_assert(wait_for_suspended());
+
+		for (i = 0; i < WIDTH; i++)
+			for (j = 0; j < HEIGHT; j++)
+				buf_check(ptr, i, j, color);
+		munmap(ptr, buf->surface[0].size);
 	}
 
 	/* Now resume and check for it again. */
 	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
 
-	memset(cpu_buf, 0, dst_size);
-	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
-	for (y = 0; y < 128; y++) {
-		for (x = 0; x < 128; x++) {
-			uint32_t px = cpu_buf[y * 128 + x];
-
-			if (y >= sq_y && y < (sq_y + sq_h) &&
-			    x >= sq_x && x < (sq_x + sq_w))
-				igt_assert_eq_u32(px, color);
-			else
-				igt_assert(px == 0);
+	if (blt_has_xy_color(drm_fd)) {
+		memset(cpu_buf, 0, dst_size);
+		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
+
+		for (y = 0; y < 128; y++) {
+			for (x = 0; x < 128; x++) {
+				uint32_t px = cpu_buf[y * 128 + x];
+
+				if (y >= sq_y && y < (sq_y + sq_h) &&
+				    x >= sq_x && x < (sq_x + sq_w))
+					igt_assert_eq_u32(px, color);
+				else
+					igt_assert(px == 0);
+			}
 		}
+	} else {
+		buf = create_buf(&data, color);
+		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
+						buf->surface[0].size, PROT_READ);
+		for (i = 0; i < WIDTH; i++)
+			for (j = 0; j < HEIGHT; j++)
+				buf_check(ptr, i, j, color);
+		munmap(ptr, buf->surface[0].size);
 	}
 
 	/* Now we'll do the opposite: do the blt while active, then read while
 	 * suspended. We use the same spot, but a different color. As a bonus,
 	 * we're testing the presumed_offset from the previous command. */
 	color = 0x87654321;
-	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
-		       &presumed_offset);
+	if (blt_has_xy_color(drm_fd)) {
 
-	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
+		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
+			       &presumed_offset);
 
-	memset(cpu_buf, 0, dst_size);
-	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
-	for (y = 0; y < 128; y++) {
-		for (x = 0; x < 128; x++) {
-			uint32_t px = cpu_buf[y * 128 + x];
-
-			if (y >= sq_y && y < (sq_y + sq_h) &&
-			    x >= sq_x && x < (sq_x + sq_w))
-				igt_assert_eq_u32(px, color);
-			else
-				igt_assert(px == 0);
+		disable_all_screens_or_forcewake_put_and_wait(&ms_data);
+
+		memset(cpu_buf, 0, dst_size);
+		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
+		for (y = 0; y < 128; y++) {
+			for (x = 0; x < 128; x++) {
+				uint32_t px = cpu_buf[y * 128 + x];
+
+				if (y >= sq_y && y < (sq_y + sq_h) &&
+				    x >= sq_x && x < (sq_x + sq_w))
+					igt_assert_eq_u32(px, color);
+				else
+					igt_assert(px == 0);
+			}
 		}
+	} else {
+		buf = create_buf(&data, color);
+		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
+						buf->surface[0].size, PROT_READ);
+		for (i = 0; i < WIDTH; i++)
+			for (j = 0; j < HEIGHT; j++)
+				buf_check(ptr, i, j, color);
+		munmap(ptr, buf->surface[0].size);
 	}
 
 	gem_close(drm_fd, handle);
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 2/4] tests/i915/i915_pm_rpm: Modify gem-execbuf test for gen12+

[Zbigniew Kempczyński]

On Mon, May 22, 2023 at 11:57:12AM +0200, Karolina Stolarek wrote:
> From: Vikas Srivastava <vikas.srivastava@intel.com>
> 
> xy_color_blt is not supported on MTL and other gen12+ target
> hence an IGT test update needs to be done. Modify the test
> to add a lib API to check for xy_color_blt support.
> 
> Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
>  tests/i915/i915_pm_rpm.c | 185 ++++++++++++++++++++++++++++++---------
>  1 file changed, 146 insertions(+), 39 deletions(-)
> 
> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
> index d9b4cbbfe..b23eba544 100644
> --- a/tests/i915/i915_pm_rpm.c
> +++ b/tests/i915/i915_pm_rpm.c
> @@ -243,6 +243,7 @@
>  #include "igt_debugfs.h"
>  #include "igt_device.h"
>  #include "igt_edid.h"
> +#include "i915/i915_blt.h"
>  
>  #define MSR_PC8_RES	0x630
>  #define MSR_PC9_RES	0x631
> @@ -252,6 +253,11 @@
>  #define MAX_ENCODERS	32
>  #define MAX_CRTCS	16
>  
> +#define WIDTH 64
> +#define HEIGHT 64
> +#define STRIDE (WIDTH)
> +#define SIZE (HEIGHT * STRIDE)
> +
>  enum pc8_status {
>  	PC8_ENABLED,
>  	PC8_DISABLED
> @@ -308,10 +314,57 @@ struct modeset_params {
>  	drmModeModeInfoPtr mode;
>  };
>  
> +struct data_t {
> +	int width;
> +	int height;
> +	uint32_t region;
> +};
> +
>  struct modeset_params lpsp_mode_params;
>  struct modeset_params non_lpsp_mode_params;
>  struct modeset_params *default_mode_params;
>  
> +/* API to create mmap buffer */
> +static struct intel_buf *
> +create_buf(struct data_t *data, uint32_t color)
> +{
> +	struct intel_buf *buf;
> +	uint8_t *ptr;
> +	uint32_t handle;
> +	struct buf_ops *bops;
> +	int i;
> +
> +	buf = calloc(1, sizeof(*buf));
> +	igt_assert(buf);
> +	bops = buf_ops_create(drm_fd);
> +
> +	handle = gem_create_in_memory_regions(drm_fd, SIZE, data->region);
> +	intel_buf_init_using_handle(bops, handle, buf,
> +				    data->width / 4, data->height, 32, 0,
> +				    I915_TILING_NONE, 0);
> +
> +	ptr = gem_mmap__cpu_coherent(drm_fd, buf->handle, 0,
> +				     buf->surface[0].size, PROT_WRITE);
> +
> +	for (i = 0; i < buf->surface[0].size; i++)
> +		ptr[i] = color;
> +
> +	munmap(ptr, buf->surface[0].size);
> +
> +	return buf;
> +}
> +
> +/* checking the buffer content is correct or not */
> +static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
> +{
> +	uint8_t val;
> +
> +	val = ptr[y * WIDTH + x];
> +	igt_assert_f(val == color,
> +		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
> +		     color, val, x, y);
> +}
> +
>  static int modprobe(const char *driver)
>  {
>  	return igt_kmod_load(driver, NULL);
> @@ -1522,7 +1575,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
>  /* Make sure we can submit a batch buffer and verify its result. */
>  static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_regions)
>  {
> -	int x, y;
> +	int x, y, i, j;
>  	uint32_t handle;
>  	int bpp = 4;
>  	int pitch = 128 * bpp;
> @@ -1531,10 +1584,31 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
>  	uint32_t presumed_offset = 0;
>  	int sq_x = 5, sq_y = 10, sq_w = 15, sq_h = 20;
>  	uint32_t color;
> +	struct intel_buf *buf;
> +	uint8_t *ptr;
> +	struct data_t data = {0, };
> +	struct igt_collection *region;
> +	struct drm_i915_query_memory_regions *region_info;
> +	struct igt_collection *region_set;
> +	uint32_t id;
>  
>  	igt_require_gem(drm_fd);
>  	gem_require_blitter(drm_fd);
>  
> +	region_info = gem_get_query_memory_regions(drm_fd);
> +	igt_assert(region_info);
> +	region_set = get_memory_region_set(region_info,
> +					   I915_SYSTEM_MEMORY,
> +					   I915_DEVICE_MEMORY);
> +	for_each_combination(region, 1, region_set) {
> +		id = igt_collection_get_value(region, 0);
> +		break;
> +	}

All above region work finally lead to simple gem_create() in
system memory (break). I think order of SYSTEM and DEVICE
regions has meaning here (I guess you want to prefer DEVICE
on discrete instead of SYSTEM).

--
Zbigniew

> +
> +	data.width = WIDTH;
> +	data.height = HEIGHT;
> +	data.region = id;
> +
>  	/* Create and set data while the device is active. */
>  	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
>  
> @@ -1549,62 +1623,95 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
>  	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
>  
>  	color = 0x12345678;
> -	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
> -		       &presumed_offset);
> -	igt_assert(wait_for_suspended());
> +	if (blt_has_xy_color(drm_fd)) {
> +		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
> +			       &presumed_offset);
> +		igt_assert(wait_for_suspended());
>  
> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> -	igt_assert(wait_for_suspended());
> -	for (y = 0; y < 128; y++) {
> -		for (x = 0; x < 128; x++) {
> -			uint32_t px = cpu_buf[y * 128 + x];
> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> +		for (y = 0; y < 128; y++) {
> +			for (x = 0; x < 128; x++) {
> +				uint32_t px = cpu_buf[y * 128 + x];
>  
> -			if (y >= sq_y && y < (sq_y + sq_h) &&
> -			    x >= sq_x && x < (sq_x + sq_w))
> -				igt_assert_eq_u32(px, color);
> -			else
> -				igt_assert(px == 0);
> +				if (y >= sq_y && y < (sq_y + sq_h) &&
> +				    x >= sq_x && x < (sq_x + sq_w))
> +					igt_assert_eq_u32(px, color);
> +				else
> +					igt_assert(px == 0);
> +			}
>  		}
> +	} else {
> +		buf = create_buf(&data, color);
> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
> +						buf->surface[0].size, PROT_READ);
> +		igt_assert(wait_for_suspended());
> +
> +		for (i = 0; i < WIDTH; i++)
> +			for (j = 0; j < HEIGHT; j++)
> +				buf_check(ptr, i, j, color);
> +		munmap(ptr, buf->surface[0].size);
>  	}
>  
>  	/* Now resume and check for it again. */
>  	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
>  
> -	memset(cpu_buf, 0, dst_size);
> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> -	for (y = 0; y < 128; y++) {
> -		for (x = 0; x < 128; x++) {
> -			uint32_t px = cpu_buf[y * 128 + x];
> -
> -			if (y >= sq_y && y < (sq_y + sq_h) &&
> -			    x >= sq_x && x < (sq_x + sq_w))
> -				igt_assert_eq_u32(px, color);
> -			else
> -				igt_assert(px == 0);
> +	if (blt_has_xy_color(drm_fd)) {
> +		memset(cpu_buf, 0, dst_size);
> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> +
> +		for (y = 0; y < 128; y++) {
> +			for (x = 0; x < 128; x++) {
> +				uint32_t px = cpu_buf[y * 128 + x];
> +
> +				if (y >= sq_y && y < (sq_y + sq_h) &&
> +				    x >= sq_x && x < (sq_x + sq_w))
> +					igt_assert_eq_u32(px, color);
> +				else
> +					igt_assert(px == 0);
> +			}
>  		}
> +	} else {
> +		buf = create_buf(&data, color);
> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
> +						buf->surface[0].size, PROT_READ);
> +		for (i = 0; i < WIDTH; i++)
> +			for (j = 0; j < HEIGHT; j++)
> +				buf_check(ptr, i, j, color);
> +		munmap(ptr, buf->surface[0].size);
>  	}
>  
>  	/* Now we'll do the opposite: do the blt while active, then read while
>  	 * suspended. We use the same spot, but a different color. As a bonus,
>  	 * we're testing the presumed_offset from the previous command. */
>  	color = 0x87654321;
> -	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
> -		       &presumed_offset);
> +	if (blt_has_xy_color(drm_fd)) {
>  
> -	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
> +		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
> +			       &presumed_offset);
>  
> -	memset(cpu_buf, 0, dst_size);
> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> -	for (y = 0; y < 128; y++) {
> -		for (x = 0; x < 128; x++) {
> -			uint32_t px = cpu_buf[y * 128 + x];
> -
> -			if (y >= sq_y && y < (sq_y + sq_h) &&
> -			    x >= sq_x && x < (sq_x + sq_w))
> -				igt_assert_eq_u32(px, color);
> -			else
> -				igt_assert(px == 0);
> +		disable_all_screens_or_forcewake_put_and_wait(&ms_data);
> +
> +		memset(cpu_buf, 0, dst_size);
> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
> +		for (y = 0; y < 128; y++) {
> +			for (x = 0; x < 128; x++) {
> +				uint32_t px = cpu_buf[y * 128 + x];
> +
> +				if (y >= sq_y && y < (sq_y + sq_h) &&
> +				    x >= sq_x && x < (sq_x + sq_w))
> +					igt_assert_eq_u32(px, color);
> +				else
> +					igt_assert(px == 0);
> +			}
>  		}
> +	} else {
> +		buf = create_buf(&data, color);
> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
> +						buf->surface[0].size, PROT_READ);
> +		for (i = 0; i < WIDTH; i++)
> +			for (j = 0; j < HEIGHT; j++)
> +				buf_check(ptr, i, j, color);
> +		munmap(ptr, buf->surface[0].size);
>  	}
>  
>  	gem_close(drm_fd, handle);
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 2/4] tests/i915/i915_pm_rpm: Modify gem-execbuf test for gen12+

[Karolina Stolarek]

On 22.05.2023 13:29, Zbigniew Kempczyński wrote:
> On Mon, May 22, 2023 at 11:57:12AM +0200, Karolina Stolarek wrote:
>> From: Vikas Srivastava <vikas.srivastava@intel.com>
>>
>> xy_color_blt is not supported on MTL and other gen12+ target
>> hence an IGT test update needs to be done. Modify the test
>> to add a lib API to check for xy_color_blt support.
>>
>> Signed-off-by: Vikas Srivastava <vikas.srivastava@intel.com>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>> ---
>>   tests/i915/i915_pm_rpm.c | 185 ++++++++++++++++++++++++++++++---------
>>   1 file changed, 146 insertions(+), 39 deletions(-)
>>
>> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
>> index d9b4cbbfe..b23eba544 100644
>> --- a/tests/i915/i915_pm_rpm.c
>> +++ b/tests/i915/i915_pm_rpm.c
>> @@ -243,6 +243,7 @@
>>   #include "igt_debugfs.h"
>>   #include "igt_device.h"
>>   #include "igt_edid.h"
>> +#include "i915/i915_blt.h"
>>   
>>   #define MSR_PC8_RES	0x630
>>   #define MSR_PC9_RES	0x631
>> @@ -252,6 +253,11 @@
>>   #define MAX_ENCODERS	32
>>   #define MAX_CRTCS	16
>>   
>> +#define WIDTH 64
>> +#define HEIGHT 64
>> +#define STRIDE (WIDTH)
>> +#define SIZE (HEIGHT * STRIDE)
>> +
>>   enum pc8_status {
>>   	PC8_ENABLED,
>>   	PC8_DISABLED
>> @@ -308,10 +314,57 @@ struct modeset_params {
>>   	drmModeModeInfoPtr mode;
>>   };
>>   
>> +struct data_t {
>> +	int width;
>> +	int height;
>> +	uint32_t region;
>> +};
>> +
>>   struct modeset_params lpsp_mode_params;
>>   struct modeset_params non_lpsp_mode_params;
>>   struct modeset_params *default_mode_params;
>>   
>> +/* API to create mmap buffer */
>> +static struct intel_buf *
>> +create_buf(struct data_t *data, uint32_t color)
>> +{
>> +	struct intel_buf *buf;
>> +	uint8_t *ptr;
>> +	uint32_t handle;
>> +	struct buf_ops *bops;
>> +	int i;
>> +
>> +	buf = calloc(1, sizeof(*buf));
>> +	igt_assert(buf);
>> +	bops = buf_ops_create(drm_fd);
>> +
>> +	handle = gem_create_in_memory_regions(drm_fd, SIZE, data->region);
>> +	intel_buf_init_using_handle(bops, handle, buf,
>> +				    data->width / 4, data->height, 32, 0,
>> +				    I915_TILING_NONE, 0);
>> +
>> +	ptr = gem_mmap__cpu_coherent(drm_fd, buf->handle, 0,
>> +				     buf->surface[0].size, PROT_WRITE);
>> +
>> +	for (i = 0; i < buf->surface[0].size; i++)
>> +		ptr[i] = color;
>> +
>> +	munmap(ptr, buf->surface[0].size);
>> +
>> +	return buf;
>> +}
>> +
>> +/* checking the buffer content is correct or not */
>> +static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
>> +{
>> +	uint8_t val;
>> +
>> +	val = ptr[y * WIDTH + x];
>> +	igt_assert_f(val == color,
>> +		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
>> +		     color, val, x, y);
>> +}
>> +
>>   static int modprobe(const char *driver)
>>   {
>>   	return igt_kmod_load(driver, NULL);
>> @@ -1522,7 +1575,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
>>   /* Make sure we can submit a batch buffer and verify its result. */
>>   static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_regions)
>>   {
>> -	int x, y;
>> +	int x, y, i, j;
>>   	uint32_t handle;
>>   	int bpp = 4;
>>   	int pitch = 128 * bpp;
>> @@ -1531,10 +1584,31 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
>>   	uint32_t presumed_offset = 0;
>>   	int sq_x = 5, sq_y = 10, sq_w = 15, sq_h = 20;
>>   	uint32_t color;
>> +	struct intel_buf *buf;
>> +	uint8_t *ptr;
>> +	struct data_t data = {0, };
>> +	struct igt_collection *region;
>> +	struct drm_i915_query_memory_regions *region_info;
>> +	struct igt_collection *region_set;
>> +	uint32_t id;
>>   
>>   	igt_require_gem(drm_fd);
>>   	gem_require_blitter(drm_fd);
>>   
>> +	region_info = gem_get_query_memory_regions(drm_fd);
>> +	igt_assert(region_info);
>> +	region_set = get_memory_region_set(region_info,
>> +					   I915_SYSTEM_MEMORY,
>> +					   I915_DEVICE_MEMORY);
>> +	for_each_combination(region, 1, region_set) {
>> +		id = igt_collection_get_value(region, 0);
>> +		break;
>> +	}
> 
> All above region work finally lead to simple gem_create() in
> system memory (break). I think order of SYSTEM and DEVICE
> regions has meaning here (I guess you want to prefer DEVICE
> on discrete instead of SYSTEM).
> 

Hmm, interesting. I believe this definition was inspired by what was 
already in the code, but I can try and move things around.

Many thanks,
Karolina

> --
> Zbigniew
> 
>> +
>> +	data.width = WIDTH;
>> +	data.height = HEIGHT;
>> +	data.region = id;
>> +
>>   	/* Create and set data while the device is active. */
>>   	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
>>   
>> @@ -1549,62 +1623,95 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
>>   	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
>>   
>>   	color = 0x12345678;
>> -	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
>> -		       &presumed_offset);
>> -	igt_assert(wait_for_suspended());
>> +	if (blt_has_xy_color(drm_fd)) {
>> +		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
>> +			       &presumed_offset);
>> +		igt_assert(wait_for_suspended());
>>   
>> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> -	igt_assert(wait_for_suspended());
>> -	for (y = 0; y < 128; y++) {
>> -		for (x = 0; x < 128; x++) {
>> -			uint32_t px = cpu_buf[y * 128 + x];
>> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> +		for (y = 0; y < 128; y++) {
>> +			for (x = 0; x < 128; x++) {
>> +				uint32_t px = cpu_buf[y * 128 + x];
>>   
>> -			if (y >= sq_y && y < (sq_y + sq_h) &&
>> -			    x >= sq_x && x < (sq_x + sq_w))
>> -				igt_assert_eq_u32(px, color);
>> -			else
>> -				igt_assert(px == 0);
>> +				if (y >= sq_y && y < (sq_y + sq_h) &&
>> +				    x >= sq_x && x < (sq_x + sq_w))
>> +					igt_assert_eq_u32(px, color);
>> +				else
>> +					igt_assert(px == 0);
>> +			}
>>   		}
>> +	} else {
>> +		buf = create_buf(&data, color);
>> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
>> +						buf->surface[0].size, PROT_READ);
>> +		igt_assert(wait_for_suspended());
>> +
>> +		for (i = 0; i < WIDTH; i++)
>> +			for (j = 0; j < HEIGHT; j++)
>> +				buf_check(ptr, i, j, color);
>> +		munmap(ptr, buf->surface[0].size);
>>   	}
>>   
>>   	/* Now resume and check for it again. */
>>   	enable_one_screen_or_forcewake_get_and_wait(&ms_data);
>>   
>> -	memset(cpu_buf, 0, dst_size);
>> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> -	for (y = 0; y < 128; y++) {
>> -		for (x = 0; x < 128; x++) {
>> -			uint32_t px = cpu_buf[y * 128 + x];
>> -
>> -			if (y >= sq_y && y < (sq_y + sq_h) &&
>> -			    x >= sq_x && x < (sq_x + sq_w))
>> -				igt_assert_eq_u32(px, color);
>> -			else
>> -				igt_assert(px == 0);
>> +	if (blt_has_xy_color(drm_fd)) {
>> +		memset(cpu_buf, 0, dst_size);
>> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> +
>> +		for (y = 0; y < 128; y++) {
>> +			for (x = 0; x < 128; x++) {
>> +				uint32_t px = cpu_buf[y * 128 + x];
>> +
>> +				if (y >= sq_y && y < (sq_y + sq_h) &&
>> +				    x >= sq_x && x < (sq_x + sq_w))
>> +					igt_assert_eq_u32(px, color);
>> +				else
>> +					igt_assert(px == 0);
>> +			}
>>   		}
>> +	} else {
>> +		buf = create_buf(&data, color);
>> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
>> +						buf->surface[0].size, PROT_READ);
>> +		for (i = 0; i < WIDTH; i++)
>> +			for (j = 0; j < HEIGHT; j++)
>> +				buf_check(ptr, i, j, color);
>> +		munmap(ptr, buf->surface[0].size);
>>   	}
>>   
>>   	/* Now we'll do the opposite: do the blt while active, then read while
>>   	 * suspended. We use the same spot, but a different color. As a bonus,
>>   	 * we're testing the presumed_offset from the previous command. */
>>   	color = 0x87654321;
>> -	submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
>> -		       &presumed_offset);
>> +	if (blt_has_xy_color(drm_fd)) {
>>   
>> -	disable_all_screens_or_forcewake_put_and_wait(&ms_data);
>> +		submit_blt_cmd(handle, dst_size, sq_x, sq_y, sq_w, sq_h, pitch, color,
>> +			       &presumed_offset);
>>   
>> -	memset(cpu_buf, 0, dst_size);
>> -	gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> -	for (y = 0; y < 128; y++) {
>> -		for (x = 0; x < 128; x++) {
>> -			uint32_t px = cpu_buf[y * 128 + x];
>> -
>> -			if (y >= sq_y && y < (sq_y + sq_h) &&
>> -			    x >= sq_x && x < (sq_x + sq_w))
>> -				igt_assert_eq_u32(px, color);
>> -			else
>> -				igt_assert(px == 0);
>> +		disable_all_screens_or_forcewake_put_and_wait(&ms_data);
>> +
>> +		memset(cpu_buf, 0, dst_size);
>> +		gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
>> +		for (y = 0; y < 128; y++) {
>> +			for (x = 0; x < 128; x++) {
>> +				uint32_t px = cpu_buf[y * 128 + x];
>> +
>> +				if (y >= sq_y && y < (sq_y + sq_h) &&
>> +				    x >= sq_x && x < (sq_x + sq_w))
>> +					igt_assert_eq_u32(px, color);
>> +				else
>> +					igt_assert(px == 0);
>> +			}
>>   		}
>> +	} else {
>> +		buf = create_buf(&data, color);
>> +		ptr = gem_mmap__device_coherent(drm_fd, buf->handle, 0,
>> +						buf->surface[0].size, PROT_READ);
>> +		for (i = 0; i < WIDTH; i++)
>> +			for (j = 0; j < HEIGHT; j++)
>> +				buf_check(ptr, i, j, color);
>> +		munmap(ptr, buf->surface[0].size);
>>   	}
>>   
>>   	gem_close(drm_fd, handle);
>> -- 
>> 2.25.1
>>

[igt-dev] [PATCH i-g-t 3/4] lib/intel_cmds_info: Drop BLT_CMD_LONG flag

[Karolina Stolarek]

It looks like a separate flag for longer commands isn't needed
and we can use BLT_CMD_EXTENDED instead.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 lib/i915/intel_cmds_info.c | 2 +-
 lib/i915/intel_cmds_info.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/lib/i915/intel_cmds_info.c b/lib/i915/intel_cmds_info.c
index 3ce2fd74b..09b612279 100644
--- a/lib/i915/intel_cmds_info.c
+++ b/lib/i915/intel_cmds_info.c
@@ -87,7 +87,7 @@ static const struct blt_cmd_info
 						 BIT(T_LINEAR) |
 						 BIT(T_YMAJOR) |
 						 BIT(T_XMAJOR),
-						 BLT_CMD_LONG);
+						 BLT_CMD_EXTENDED);
 
 static const struct blt_cmd_info
 		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
diff --git a/lib/i915/intel_cmds_info.h b/lib/i915/intel_cmds_info.h
index 5998a35ca..91d0f15ec 100644
--- a/lib/i915/intel_cmds_info.h
+++ b/lib/i915/intel_cmds_info.h
@@ -34,7 +34,6 @@ struct blt_cmd_info {
 	uint32_t flags;
 #define BLT_CMD_EXTENDED               (1 << 0)
 #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
-#define BLT_CMD_LONG                   (1 << 2)
 };
 
 struct intel_cmds_info {
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t 3/4] lib/intel_cmds_info: Drop BLT_CMD_LONG flag

[Zbigniew Kempczyński]

On Mon, May 22, 2023 at 11:57:13AM +0200, Karolina Stolarek wrote:
> It looks like a separate flag for longer commands isn't needed
> and we can use BLT_CMD_EXTENDED instead.

If so what for you're introducing this flag in patch 1/4?

--
Zbigniew

> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
>  lib/i915/intel_cmds_info.c | 2 +-
>  lib/i915/intel_cmds_info.h | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/lib/i915/intel_cmds_info.c b/lib/i915/intel_cmds_info.c
> index 3ce2fd74b..09b612279 100644
> --- a/lib/i915/intel_cmds_info.c
> +++ b/lib/i915/intel_cmds_info.c
> @@ -87,7 +87,7 @@ static const struct blt_cmd_info
>  						 BIT(T_LINEAR) |
>  						 BIT(T_YMAJOR) |
>  						 BIT(T_XMAJOR),
> -						 BLT_CMD_LONG);
> +						 BLT_CMD_EXTENDED);
>  
>  static const struct blt_cmd_info
>  		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
> diff --git a/lib/i915/intel_cmds_info.h b/lib/i915/intel_cmds_info.h
> index 5998a35ca..91d0f15ec 100644
> --- a/lib/i915/intel_cmds_info.h
> +++ b/lib/i915/intel_cmds_info.h
> @@ -34,7 +34,6 @@ struct blt_cmd_info {
>  	uint32_t flags;
>  #define BLT_CMD_EXTENDED               (1 << 0)
>  #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
> -#define BLT_CMD_LONG                   (1 << 2)
>  };
>  
>  struct intel_cmds_info {
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 3/4] lib/intel_cmds_info: Drop BLT_CMD_LONG flag

[Karolina Stolarek]

On 22.05.2023 13:32, Zbigniew Kempczyński wrote:
> On Mon, May 22, 2023 at 11:57:13AM +0200, Karolina Stolarek wrote:
>> It looks like a separate flag for longer commands isn't needed
>> and we can use BLT_CMD_EXTENDED instead.
> 
> If so what for you're introducing this flag in patch 1/4?
> 

The idea was to keep the original patch and work on the top of it. But I 
can modify it and drop this commit, no problem.

Thanks,
Karolina

> --
> Zbigniew
> 
>>
>> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>> ---
>>   lib/i915/intel_cmds_info.c | 2 +-
>>   lib/i915/intel_cmds_info.h | 1 -
>>   2 files changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/lib/i915/intel_cmds_info.c b/lib/i915/intel_cmds_info.c
>> index 3ce2fd74b..09b612279 100644
>> --- a/lib/i915/intel_cmds_info.c
>> +++ b/lib/i915/intel_cmds_info.c
>> @@ -87,7 +87,7 @@ static const struct blt_cmd_info
>>   						 BIT(T_LINEAR) |
>>   						 BIT(T_YMAJOR) |
>>   						 BIT(T_XMAJOR),
>> -						 BLT_CMD_LONG);
>> +						 BLT_CMD_EXTENDED);
>>   
>>   static const struct blt_cmd_info
>>   		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT,
>> diff --git a/lib/i915/intel_cmds_info.h b/lib/i915/intel_cmds_info.h
>> index 5998a35ca..91d0f15ec 100644
>> --- a/lib/i915/intel_cmds_info.h
>> +++ b/lib/i915/intel_cmds_info.h
>> @@ -34,7 +34,6 @@ struct blt_cmd_info {
>>   	uint32_t flags;
>>   #define BLT_CMD_EXTENDED               (1 << 0)
>>   #define BLT_CMD_SUPPORTS_COMPRESSION   (1 << 1)
>> -#define BLT_CMD_LONG                   (1 << 2)
>>   };
>>   
>>   struct intel_cmds_info {
>> -- 
>> 2.25.1
>>

[igt-dev] [PATCH i-g-t 4/4] tests/i915/i915_pm_rpm: Check command property instead of gen

[Karolina Stolarek]

Update submit_blt_cmd() function to check if a platform uses a long
version of XY_COLOR_BLT when building the command. Remove checks
related to the gen alone.

Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
 tests/i915/i915_pm_rpm.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index b23eba544..8656f5531 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1489,20 +1489,24 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
 	uint32_t batch_handle;
 	int batch_size = 8 * sizeof(uint32_t);
 	uint32_t batch_buf[batch_size];
+	bool cmd_extended;
 	struct drm_i915_gem_execbuffer2 execbuf = {};
 	struct drm_i915_gem_exec_object2 objs[2] = {{}, {}};
 	struct drm_i915_gem_relocation_entry relocs[1] = {{}};
 	struct drm_i915_gem_wait gem_wait;
 	uint64_t ahnd = get_reloc_ahnd(drm_fd, 0), dst_offset;
+	const struct intel_cmds_info *cmds_info = intel_get_cmds_info(ms_data.devid);
 
 	if (ahnd)
 		dst_offset = get_offset(ahnd, dst_handle, dst_size, 0);
 	else
 		dst_offset = *presumed_dst_offset;
 
+	cmd_extended = blt_cmd_has_property(cmds_info, XY_COLOR_BLT,
+					    BLT_CMD_EXTENDED);
 	i = 0;
 
-	if (intel_gen(ms_data.devid) >= 8)
+	if (cmd_extended)
 		batch_buf[i++] = XY_COLOR_BLT_CMD_NOLEN |
 				 XY_COLOR_BLT_WRITE_ALPHA |
 				 XY_COLOR_BLT_WRITE_RGB | 0x5;
@@ -1515,12 +1519,12 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
 	batch_buf[i++] = ((y + height) << 16) | (x + width);
 	reloc_pos = i;
 	batch_buf[i++] = dst_offset;
-	if (intel_gen(ms_data.devid) >= 8)
+	if (cmd_extended)
 		batch_buf[i++] = dst_offset >> 32;
 	batch_buf[i++] = color;
 
 	batch_buf[i++] = MI_BATCH_BUFFER_END;
-	if (intel_gen(ms_data.devid) < 8)
+	if (!cmd_extended)
 		batch_buf[i++] = MI_NOOP;
 
 	igt_assert(i * sizeof(uint32_t) == batch_size);
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Use intel_cmds_info in i915_pm_rpm

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4583 bytes --]

== Series Details ==

Series: Use intel_cmds_info in i915_pm_rpm
URL   : https://patchwork.freedesktop.org/series/118102/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13171 -> IGTPW_9016
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html

Participating hosts (39 -> 37)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_9016 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [PASS][1] -> [DMESG-WARN][2] ([i915#7699])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-1:         [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7911] / [i915#7920])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/bat-rpls-1/igt@i915_selftest@live@requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-2:         NOTRUN -> [DMESG-WARN][5] ([i915#6367])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-rpls-2/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-rpls-2:         NOTRUN -> [ABORT][6] ([i915#6687])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-adlp-9:         NOTRUN -> [SKIP][7] ([i915#3546]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][8] ([i915#5334]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [ABORT][10] ([i915#7913]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/bat-rpls-2/igt@i915_selftest@live@requests.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-rpls-2/igt@i915_selftest@live@requests.html
    - {bat-mtlp-8}:       [DMESG-FAIL][12] ([i915#8497]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-mtlp-8/igt@i915_selftest@live@requests.html
    - {bat-mtlp-6}:       [DMESG-FAIL][14] ([i915#8497]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/bat-mtlp-6/igt@i915_selftest@live@requests.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/bat-mtlp-6/igt@i915_selftest@live@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7299 -> IGTPW_9016

  CI-20190529: 20190529
  CI_DRM_13171: 9ee3008b1f9517cd236dedf72f28c228fede7559 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9016: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html
  IGT_7299: 3effd4be7f6c867d942532b3fe18d6c54fffbd7a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html

[-- Attachment #2: Type: text/html, Size: 5452 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Use intel_cmds_info in i915_pm_rpm

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 16299 bytes --]

== Series Details ==

Series: Use intel_cmds_info in i915_pm_rpm
URL   : https://patchwork.freedesktop.org/series/118102/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13171_full -> IGTPW_9016_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html

Participating hosts (7 -> 8)
------------------------------

  Additional (1): shard-rkl0 

Known issues
------------

  Here are the changes found in IGTPW_9016_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([i915#2842])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-glk:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk8/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][6] ([i915#2658])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk9/igt@gem_pread@exhaustion.html

  * igt@i915_query@query-topology-unsupported:
    - shard-apl:          NOTRUN -> [SKIP][7] ([fdo#109271])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-apl3/igt@i915_query@query-topology-unsupported.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-apl2/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-glk:          NOTRUN -> [SKIP][9] ([fdo#109271]) +16 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk2/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-hdmi-a1:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2122])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-hdmi-a1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-apl:          [PASS][12] -> [ABORT][13] ([i915#180])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-apl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][14] ([i915#4573]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk1/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][15] ([fdo#109271]) +14 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-snb2/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4579]) +10 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-snb4/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-vga-1.html

  * igt@kms_setmode@basic@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [FAIL][17] ([i915#5465]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][18] ([i915#6268]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@kms:
    - {shard-dg1}:        [FAIL][20] ([i915#5784]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-dg1-17/igt@gem_eio@kms.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-dg1-17/igt@gem_eio@kms.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - {shard-rkl}:        [FAIL][22] ([i915#2842]) -> [PASS][23] +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-rkl-6/igt@gem_exec_fair@basic-none@vcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-rkl-1/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - {shard-rkl}:        [SKIP][24] ([i915#1937] / [i915#4579]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-rkl-4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-dg1}:        [FAIL][26] ([i915#3591]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - {shard-rkl}:        [SKIP][28] ([i915#1397]) -> [PASS][29] +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-rkl-4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-apl:          [DMESG-FAIL][30] ([i915#5334]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - {shard-rkl}:        [FAIL][32] ([i915#3743]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-rkl-7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][34] ([i915#2346]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
    - shard-glk:          [FAIL][36] ([i915#79]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html

  * igt@kms_sysfs_edid_timing:
    - {shard-dg1}:        [FAIL][38] ([IGT#2] / [i915#6493]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-dg1-15/igt@kms_sysfs_edid_timing.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-dg1-12/igt@kms_sysfs_edid_timing.html

  * igt@perf@stress-open-close@0-rcs0:
    - shard-glk:          [ABORT][40] ([i915#5213] / [i915#7941]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13171/shard-glk8/igt@perf@stress-open-close@0-rcs0.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/shard-glk9/igt@perf@stress-open-close@0-rcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8304]: https://gitlab.freedesktop.org/drm/intel/issues/8304
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7299 -> IGTPW_9016
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_13171: 9ee3008b1f9517cd236dedf72f28c228fede7559 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9016: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html
  IGT_7299: 3effd4be7f6c867d942532b3fe18d6c54fffbd7a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9016/index.html

[-- Attachment #2: Type: text/html, Size: 12776 bytes --]