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* [PATCH i-g-t 1/4] lib/amdgpu: add gpu reset check
@ 2024-11-07  2:05 Jesse.zhang@amd.com
  2024-11-07  2:05 ` [PATCH i-g-t 2/4] tests/amd_queue_reset: modify the asic filter Jesse.zhang@amd.com
                   ` (6 more replies)
  0 siblings, 7 replies; 9+ messages in thread
From: Jesse.zhang@amd.com @ 2024-11-07  2:05 UTC (permalink / raw)
  To: igt-dev
  Cc: Vitaly Prosyak, Alex Deucher, Christian Koenig, Kamil Konieczny,
	Jesse.zhang@amd.com, Jesse Zhang

GPU reset types include full adapter reset, soft reset,
queue reset and pipeline reset. It is possible to check
whether a specific reset is supported via the sysfs interface
and run special cases for testing.

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
---
 lib/amdgpu/amd_ip_blocks.c | 57 ++++++++++++++++++++++++++++++++++++++
 lib/amdgpu/amd_ip_blocks.h |  8 ++++++
 2 files changed, 65 insertions(+)

diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index df603618b..40db28d8d 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c
@@ -995,3 +995,60 @@ asic_rings_readness(amdgpu_device_handle device_handle, uint32_t mask,
 		arr[i++] = is_rings_available(device_handle, mask, ip);
 }
 
+/**
+ * is_reset_enable:
+ * @ip_type: such as gfx, compute and dma.
+ * @reset_type: includes full adapter reset, soft reset, queue reset, and pipeline reset
+ *
+ * Check if reset supports certain reset types.
+ */
+
+bool
+is_reset_enable(enum amd_ip_block_type ip_type, uint32_t reset_type)
+{
+        char cmd[256];
+        FILE *fp, *fp2;
+        char buffer[100];
+        bool enable = false;
+        char reset_mask[100];
+
+        if(ip_type == AMD_IP_GFX)
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "gfx_reset_mask");
+        else if (ip_type == AMD_IP_COMPUTE)
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "compute_reset_mask");
+        else if (ip_type == AMD_IP_DMA)
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "sdma_reset_mask");
+        else if (ip_type == AMD_IP_VCN_JPEG)
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "jpeg_reset_mask");
+        else if (ip_type == AMD_IP_VPE)
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "vpe_reset_mask");
+        else
+                snprintf(reset_mask, sizeof(reset_mask) - 1, "vcn_reset_mask");
+
+        snprintf(cmd, sizeof(cmd) - 1, "sudo cat /sys/kernel/debug/dri/0/name |grep -oP '(?<=dev=)[0-9:.]+'");
+        fp = popen(cmd, "r");
+        if (fp == NULL)
+                return false;
+
+        if (fgets(buffer, 13, fp) != NULL) {
+                snprintf(cmd,sizeof(cmd) - 1,"sudo cat /sys/bus/pci/devices/%s/%s | grep -oP '%s'",
+                        buffer,reset_mask,
+			reset_type & AMDGPU_RESET_TYPE_FULL ? "full":
+			reset_type & AMDGPU_RESET_TYPE_SOFT_RESET ? "soft":
+			reset_type & AMDGPU_RESET_TYPE_PER_QUEUE ? "queue": "pipe");
+
+                fp2 = popen(cmd, "r");
+                if (fp2 == NULL) {
+                        pclose(fp);
+                        return false;
+                }
+
+                if (fgets(buffer, 13, fp2) != NULL) {
+                        enable = true;
+                }
+                pclose(fp2);
+        }
+        pclose(fp);
+
+        return enable;
+}
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 109d36602..337ef3c25 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -14,6 +14,12 @@
 
 #define MAX_CARDS_SUPPORTED 4
 
+/* reset mask */
+#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */
+#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */
+#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
+#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
+
 enum amd_ip_block_type {
 	AMD_IP_GFX = 0,
 	AMD_IP_COMPUTE,
@@ -212,4 +218,6 @@ amdgpu_open_devices(bool open_render_node, int max_cards_supported, int drm_amdg
 void
 asic_rings_readness(amdgpu_device_handle device_handle, uint32_t mask, bool arr[AMD_IP_MAX]);
 
+bool
+is_reset_enable(enum amd_ip_block_type ip_type, uint32_t reset_type);
 #endif
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-11-11  0:44 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-07  2:05 [PATCH i-g-t 1/4] lib/amdgpu: add gpu reset check Jesse.zhang@amd.com
2024-11-07  2:05 ` [PATCH i-g-t 2/4] tests/amd_queue_reset: modify the asic filter Jesse.zhang@amd.com
2024-11-07  2:05 ` [PATCH i-g-t 3/4] tests/amd_deadlock: add the filter for amd deadlock Jesse.zhang@amd.com
2024-11-07  2:05 ` [PATCH i-g-t 4/4] tests/amd_dispatch: add the filter for amd dispatch Jesse.zhang@amd.com
2024-11-11  0:44   ` vitaly prosyak
2024-11-07  2:54 ` ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/amdgpu: add gpu reset check Patchwork
2024-11-07  3:02 ` ✓ CI.xeBAT: " Patchwork
2024-11-07  3:56 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-11-08  9:08 ` ✗ CI.xeFULL: " Patchwork

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