* [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties
@ 2026-08-14 6:32 Joseph Guo
2026-08-14 6:45 ` sashiko-bot
2026-08-14 7:25 ` Daniel Baluta
0 siblings, 2 replies; 4+ messages in thread
From: Joseph Guo @ 2026-08-14 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, qijian.guo,
Joseph Guo
Add boot phase properties to essential resources during boot phase.
FRDM-IMX95 need UART, SD-Card, eMMC access during boot process.
Signed-off-by: Joseph Guo <qijian.guo@nxp.com>
---
arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
index 0f43e3be70589532763f65f1699f31dd361cc841..ba17d87f197a3d3498a815fb82547bd810b3e57d 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
@@ -140,6 +140,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-name = "VDD_SD2_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
+ bootph-pre-ram;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
@@ -445,6 +446,7 @@ led_backlight1: led@1 {
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
+ bootph-pre-ram;
status = "okay";
};
@@ -721,6 +723,7 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
+ bootph-pre-ram;
};
pinctrl_uart1: uart1grp {
@@ -728,6 +731,7 @@ pinctrl_uart1: uart1grp {
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
+ bootph-pre-ram;
};
pinctrl_uart5: uart5grp {
@@ -753,6 +757,7 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
@@ -769,6 +774,7 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
@@ -785,12 +791,14 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2: usdhc2grp {
@@ -803,6 +811,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -815,6 +824,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -827,6 +837,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc3: usdhc3grp {
@@ -1001,6 +1012,7 @@ &usdhc1 {
pinctrl-3 = <&pinctrl_usdhc1>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
fsl,tuning-step = <1>;
+ bootph-pre-ram;
status = "okay";
};
@@ -1014,6 +1026,7 @@ &usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <®_usdhc2_vmmc>;
fsl,tuning-step = <1>;
+ bootph-pre-ram;
status = "okay";
};
---
base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
change-id: 20260814-bootph-frdm-imx95-a4124d7bede4
Best regards,
--
Joseph Guo <qijian.guo@nxp.com>
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties
2026-08-14 6:32 [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties Joseph Guo
@ 2026-08-14 6:45 ` sashiko-bot
2026-08-14 6:49 ` [EXT] " Joseph Guo
2026-08-14 7:25 ` Daniel Baluta
1 sibling, 1 reply; 4+ messages in thread
From: sashiko-bot @ 2026-08-14 6:45 UTC (permalink / raw)
To: Joseph Guo; +Cc: imx, Frank.Li, devicetree, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing device tree boot phase properties on provider dependencies (`&gpio3`, `&scmi_clk`) causes early boot (SPL) failure for UART and SD/eMMC.
--
--- Patch [1]: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties ---
commit 9b9056eb20751b354934dfae8becee905da7d7b0
Author: Joseph Guo <qijian.guo@nxp.com>
arm64: dts: imx95-15x15-frdm: add boot phase properties
Add boot phase properties to essential resources during boot phase.
FRDM-IMX95 need UART, SD-Card, eMMC access during boot process.
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> index 0f43e3be70589..ba17d87f197a3 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> @@ -140,6 +140,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> regulator-name = "VDD_SD2_3V3";
> gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> + bootph-pre-ram;
> };
[Severity: High]
Will this regulator fail to probe during early boot (SPL)?
It appears that while this regulator is marked for SPL, its provider &gpio3
lacks boot phase tags. U-Boot's SPL device tree minification tool (fdtgrep)
drops any node lacking bootph-* tags unless it is an ancestor of a tagged node,
and phandle dependencies are not automatically kept.
If &gpio3 is excluded from the SPL DTB, could this fail to acquire the
enable GPIO and break MMC power?
[ ... ]
> @@ -445,6 +446,7 @@ led_backlight1: led@1 {
> &lpuart1 {
> pinctrl-0 = <&pinctrl_uart1>;
> pinctrl-names = "default";
> + bootph-pre-ram;
> status = "okay";
> };
[Severity: High]
Is a boot phase tag also needed on the clock provider &scmi_clk for this UART?
Since phandle dependencies are stripped if not explicitly tagged, this could
cause clock acquisition to fail during SPL when &scmi_clk is missing from
the minified device tree.
[ ... ]
> @@ -1014,6 +1026,7 @@ &usdhc2 {
> pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> vmmc-supply = <®_usdhc2_vmmc>;
> fsl,tuning-step = <1>;
> + bootph-pre-ram;
> status = "okay";
> };
[Severity: High]
Could the missing provider tag on &gpio3 also cause a regression here for
the card detect GPIO?
Since this node is marked for early boot but relies on &gpio3 via cd-gpios,
SPL might fail to acquire the GPIO if &gpio3 is excluded from the SPL DTB.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260814-bootph-frdm-imx95-v1-1-c0e3f1b9d2ed@nxp.com?part=1
^ permalink raw reply [flat|nested] 4+ messages in thread* RE: [EXT] Re: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties
2026-08-14 6:45 ` sashiko-bot
@ 2026-08-14 6:49 ` Joseph Guo
0 siblings, 0 replies; 4+ messages in thread
From: Joseph Guo @ 2026-08-14 6:49 UTC (permalink / raw)
To: sashiko-reviews@lists.linux.dev
Cc: imx@lists.linux.dev, Frank.Li@kernel.org,
devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
NXP Confidential
> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: Friday, August 14, 2026 2:45 PM
> To: Joseph Guo <qijian.guo@nxp.com>
> Cc: imx@lists.linux.dev; Frank.Li@kernel.org; devicetree@vger.kernel.org;
> conor+dt@kernel.org; robh@kernel.org
> Subject: [EXT] Re: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase
> properties
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s)
> to consider:
> - [High] Missing device tree boot phase properties on provider dependencies
> (`&gpio3`, `&scmi_clk`) causes early boot (SPL) failure for UART and SD/eMMC.
> --
>
> --- Patch [1]: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase
> properties --- commit 9b9056eb20751b354934dfae8becee905da7d7b0
> Author: Joseph Guo <qijian.guo@nxp.com>
>
> arm64: dts: imx95-15x15-frdm: add boot phase properties
>
> Add boot phase properties to essential resources during boot phase.
> FRDM-IMX95 need UART, SD-Card, eMMC access during boot process.
>
> > diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> > b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> > index 0f43e3be70589..ba17d87f197a3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> > @@ -140,6 +140,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> > regulator-name = "VDD_SD2_3V3";
> > gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> > enable-active-high;
> > + bootph-pre-ram;
> > };
>
> [Severity: High]
> Will this regulator fail to probe during early boot (SPL)?
>
> It appears that while this regulator is marked for SPL, its provider &gpio3 lacks
> boot phase tags. U-Boot's SPL device tree minification tool (fdtgrep) drops any
> node lacking bootph-* tags unless it is an ancestor of a tagged node, and
> phandle dependencies are not automatically kept.
>
> If &gpio3 is excluded from the SPL DTB, could this fail to acquire the enable
> GPIO and break MMC power?
>
> [ ... ]
>
> > @@ -445,6 +446,7 @@ led_backlight1: led@1 {
> > &lpuart1 {
> > pinctrl-0 = <&pinctrl_uart1>;
> > pinctrl-names = "default";
> > + bootph-pre-ram;
> > status = "okay";
> > };
>
> [Severity: High]
> Is a boot phase tag also needed on the clock provider &scmi_clk for this UART?
>
> Since phandle dependencies are stripped if not explicitly tagged, this could
> cause clock acquisition to fail during SPL when &scmi_clk is missing from the
> minified device tree.
>
> [ ... ]
>
> > @@ -1014,6 +1026,7 @@ &usdhc2 {
> > pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > vmmc-supply = <®_usdhc2_vmmc>;
> > fsl,tuning-step = <1>;
> > + bootph-pre-ram;
> > status = "okay";
> > };
>
> [Severity: High]
> Could the missing provider tag on &gpio3 also cause a regression here for the
> card detect GPIO?
>
> Since this node is marked for early boot but relies on &gpio3 via cd-gpios, SPL
> might fail to acquire the GPIO if &gpio3 is excluded from the SPL DTB.
>
&scmi_clk, &gpio3 both have the booth-all property in SoC u-boot dtsi already.
This won't be an issue if not adding the booth- property in board dts.
> --
> Sashiko AI
> review · https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%
> 2Fsashiko.dev%2F%23%2Fpatchset%2F20260814-bootph-frdm-imx95-v1-
> 1-
> c0e3f1b9d2ed%40nxp.com%3Fpart%3D1&data=05%7C02%7Cqijian.guo%4
> 0nxp.com%7C0de91c85afe547e4e75408def9cf9c95%7C686ea1d3bc2b4c6f
> a92cd99c5c301635%7C0%7C0%7C639222867257619988%7CUnknown%7
> CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOi
> JXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> elhbsnr6HqPz8KlXMZXnKx90oqd5iLF8CUBVDz6XfOo%3D&reserved=0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties
2026-08-14 6:32 [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties Joseph Guo
2026-08-14 6:45 ` sashiko-bot
@ 2026-08-14 7:25 ` Daniel Baluta
1 sibling, 0 replies; 4+ messages in thread
From: Daniel Baluta @ 2026-08-14 7:25 UTC (permalink / raw)
To: Joseph Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, qijian.guo,
daniel.baluta
On 8/14/26 09:32, Joseph Guo wrote:
> Add boot phase properties to essential resources during boot phase.
>
> FRDM-IMX95 need UART, SD-Card, eMMC access during boot process.
>
> Signed-off-by: Joseph Guo <qijian.guo@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-08-14 6:32 [PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties Joseph Guo
2026-08-14 6:45 ` sashiko-bot
2026-08-14 6:49 ` [EXT] " Joseph Guo
2026-08-14 7:25 ` Daniel Baluta
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