* [PATCH 1/1] irqchip: irq-imx-mu-msi: fixed wrong register offset for 8ulp
@ 2022-10-04 20:24 Frank Li
2022-10-04 21:27 ` Fabio Estevam
0 siblings, 1 reply; 3+ messages in thread
From: Frank Li @ 2022-10-04 20:24 UTC (permalink / raw)
To: imx, Thomas Gleixner, Marc Zyngier, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:IRQCHIP DRIVERS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Offset 0x124 should be IMX_MU_TSR, not IMX_MU_GSR
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/irqchip/irq-imx-mu-msi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c
index b62139dc36e82..229039eda1b1f 100644
--- a/drivers/irqchip/irq-imx-mu-msi.c
+++ b/drivers/irqchip/irq-imx-mu-msi.c
@@ -292,7 +292,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
.xSR = {
[IMX_MU_SR] = 0xC,
[IMX_MU_GSR] = 0x118,
- [IMX_MU_GSR] = 0x124,
+ [IMX_MU_TSR] = 0x124,
[IMX_MU_RSR] = 0x12C,
},
.xCR = {
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] irqchip: irq-imx-mu-msi: fixed wrong register offset for 8ulp
2022-10-04 20:24 [PATCH 1/1] irqchip: irq-imx-mu-msi: fixed wrong register offset for 8ulp Frank Li
@ 2022-10-04 21:27 ` Fabio Estevam
2022-10-04 22:41 ` Marc Zyngier
0 siblings, 1 reply; 3+ messages in thread
From: Fabio Estevam @ 2022-10-04 21:27 UTC (permalink / raw)
To: Frank Li
Cc: imx, Thomas Gleixner, Marc Zyngier, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team,
open list:IRQCHIP DRIVERS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
colin.i.king
Hi Frank,
On Tue, Oct 4, 2022 at 5:24 PM Frank Li <Frank.Li@nxp.com> wrote:
>
> Offset 0x124 should be IMX_MU_TSR, not IMX_MU_GSR
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
You missed passing Reported-by and Fixes tag.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] irqchip: irq-imx-mu-msi: fixed wrong register offset for 8ulp
2022-10-04 21:27 ` Fabio Estevam
@ 2022-10-04 22:41 ` Marc Zyngier
0 siblings, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2022-10-04 22:41 UTC (permalink / raw)
To: Fabio Estevam
Cc: Frank Li, imx, Thomas Gleixner, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team,
open list:IRQCHIP DRIVERS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
colin.i.king
On Tue, 04 Oct 2022 22:27:32 +0100,
Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Frank,
>
> On Tue, Oct 4, 2022 at 5:24 PM Frank Li <Frank.Li@nxp.com> wrote:
> >
> > Offset 0x124 should be IMX_MU_TSR, not IMX_MU_GSR
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
>
> You missed passing Reported-by and Fixes tag.
I fixed that locally. Thanks for CC'ing Colin though.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-10-04 20:24 [PATCH 1/1] irqchip: irq-imx-mu-msi: fixed wrong register offset for 8ulp Frank Li
2022-10-04 21:27 ` Fabio Estevam
2022-10-04 22:41 ` Marc Zyngier
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