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From: "Arnd Bergmann" <arnd@arndb.de>
To: "James Clark" <james.clark@linaro.org>,
	"Vladimir Oltean" <vladimir.oltean@nxp.com>
Cc: "Frank Li" <Frank.li@nxp.com>,
	"Vladimir Oltean" <olteanv@gmail.com>,
	"Mark Brown" <broonie@kernel.org>,
	linux-spi@vger.kernel.org, imx@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA
Date: Thu, 12 Jun 2025 17:40:33 +0200	[thread overview]
Message-ID: <b9ae3ee9-1296-4a0d-b6e2-97aaf551482c@app.fastmail.com> (raw)
In-Reply-To: <ad7e9aa7-74a3-449d-8ed9-cb270fd5c718@linaro.org>

On Thu, Jun 12, 2025, at 16:14, James Clark wrote:
> On 12/06/2025 12:15 pm, Vladimir Oltean wrote:
> This leads me to realise a mistake in my original figures. My head was 
> stuck in target mode where we use DMA so I forgot to force DMA in host 
> mode to run the performance tests. The previous figures were all XSPI 
> mode and the small difference in performance could have been just down 
> to the layout of the code changing?
>
> Changing it to DMA mode gives figures that make much more sense:
>
> Coherent (4096 byte transfers): 6534 kbps
> Non-coherent:                   7347 kbps
>
> Coherent (16 byte transfers):    447 kbps
> Non-coherent:                    448 kbps

Ok, good. The improvement from the patch is less than I had hoped
for, but it does sound like at least it doesn't get worse for
small transfers.

     Arnd

  parent reply	other threads:[~2025-06-12 15:40 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-09 15:32 [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements James Clark
2025-06-09 15:32 ` [PATCH 1/4] spi: spi-fsl-dspi: Clear completion counter before initiating transfer James Clark
2025-06-10 11:34   ` Vladimir Oltean
2025-06-10 15:41     ` James Clark
2025-06-10 21:01       ` Vladimir Oltean
2025-06-10 21:31         ` Vladimir Oltean
2025-06-11  9:12           ` James Clark
2025-06-09 15:32 ` [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA James Clark
2025-06-10  8:26   ` Arnd Bergmann
2025-06-10  9:03     ` James Clark
2025-06-10 15:15   ` Frank Li
2025-06-10 15:46     ` James Clark
2025-06-13 15:56       ` David Laight
2025-06-10 15:48     ` Arnd Bergmann
2025-06-10 15:56       ` Frank Li
2025-06-11  9:01         ` Vladimir Oltean
2025-06-12 11:05           ` James Clark
2025-06-12 11:15             ` Vladimir Oltean
2025-06-12 14:14               ` James Clark
2025-06-12 14:23                 ` Vladimir Oltean
2025-06-12 14:28                   ` James Clark
2025-06-12 14:31                     ` Vladimir Oltean
2025-06-12 14:35                       ` James Clark
2025-06-12 14:36                 ` Vladimir Oltean
2025-06-12 15:36                   ` James Clark
2025-06-12 15:37                     ` James Clark
2025-06-12 14:43                 ` Mark Brown
2025-06-12 15:47                   ` James Clark
2025-06-12 15:51                     ` Vladimir Oltean
2025-06-12 15:40                 ` Arnd Bergmann [this message]
2025-06-12 11:15             ` Arnd Bergmann
2025-06-09 15:32 ` [PATCH 3/4] spi: spi-fsl-dspi: Increase DMA buffer size James Clark
2025-06-09 15:32 ` [PATCH 4/4] spi: spi-fsl-dspi: Report FIFO overflows as errors James Clark
2025-06-10 21:52   ` Vladimir Oltean
2025-06-11 14:40     ` James Clark
2025-06-11 14:56       ` Vladimir Oltean
2025-06-11 15:00         ` James Clark
2025-06-30 11:40 ` [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements Mark Brown
2025-06-30 12:23   ` James Clark
2025-06-30 12:25     ` Mark Brown
2025-06-30 12:36       ` James Clark
2025-06-30 12:40         ` Mark Brown
2025-06-30 12:54           ` James Clark

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