From: James Clark <james.clark@linaro.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>,
linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Vladimir Oltean <olteanv@gmail.com>,
Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA
Date: Tue, 10 Jun 2025 10:03:18 +0100 [thread overview]
Message-ID: <e78107ae-e2d9-4ffb-9a2a-bc04426e2a75@linaro.org> (raw)
In-Reply-To: <1c579729-4461-4666-ab1a-77f17a320ee9@app.fastmail.com>
On 10/06/2025 9:26 am, Arnd Bergmann wrote:
> On Mon, Jun 9, 2025, at 17:32, James Clark wrote:
>> Using coherent memory here isn't functionally necessary. Because the
>> change to use non-coherent memory isn't overly complex and only a few
>> synchronization points are required, we might as well do it while fixing
>> up some other DMA issues.
>>
>> Suggested-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>
> This version looks good to me,
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> I had reviewed an internal version originally and had some comment
> on that, all of which are addressed now. You did not Cc me on the
> other patches, so I looked them up in the archive, Patch 3 also
Yes sorry about that. I've just started using "b4 send" and I was under
the impression that it would automatically CC all patches the same way,
but apparently not. Maybe I'm holding it wrong.
> looks good to me and complements this one (i.e. you really want
> the combination). I did not understand the logic in patch 4,
> and it would be good if someone else can take a closer look
> at that in order to Ack that.
>
> Arnd
next prev parent reply other threads:[~2025-06-10 9:03 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-09 15:32 [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements James Clark
2025-06-09 15:32 ` [PATCH 1/4] spi: spi-fsl-dspi: Clear completion counter before initiating transfer James Clark
2025-06-10 11:34 ` Vladimir Oltean
2025-06-10 15:41 ` James Clark
2025-06-10 21:01 ` Vladimir Oltean
2025-06-10 21:31 ` Vladimir Oltean
2025-06-11 9:12 ` James Clark
2025-06-09 15:32 ` [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA James Clark
2025-06-10 8:26 ` Arnd Bergmann
2025-06-10 9:03 ` James Clark [this message]
2025-06-10 15:15 ` Frank Li
2025-06-10 15:46 ` James Clark
2025-06-13 15:56 ` David Laight
2025-06-10 15:48 ` Arnd Bergmann
2025-06-10 15:56 ` Frank Li
2025-06-11 9:01 ` Vladimir Oltean
2025-06-12 11:05 ` James Clark
2025-06-12 11:15 ` Vladimir Oltean
2025-06-12 14:14 ` James Clark
2025-06-12 14:23 ` Vladimir Oltean
2025-06-12 14:28 ` James Clark
2025-06-12 14:31 ` Vladimir Oltean
2025-06-12 14:35 ` James Clark
2025-06-12 14:36 ` Vladimir Oltean
2025-06-12 15:36 ` James Clark
2025-06-12 15:37 ` James Clark
2025-06-12 14:43 ` Mark Brown
2025-06-12 15:47 ` James Clark
2025-06-12 15:51 ` Vladimir Oltean
2025-06-12 15:40 ` Arnd Bergmann
2025-06-12 11:15 ` Arnd Bergmann
2025-06-09 15:32 ` [PATCH 3/4] spi: spi-fsl-dspi: Increase DMA buffer size James Clark
2025-06-09 15:32 ` [PATCH 4/4] spi: spi-fsl-dspi: Report FIFO overflows as errors James Clark
2025-06-10 21:52 ` Vladimir Oltean
2025-06-11 14:40 ` James Clark
2025-06-11 14:56 ` Vladimir Oltean
2025-06-11 15:00 ` James Clark
2025-06-30 11:40 ` [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements Mark Brown
2025-06-30 12:23 ` James Clark
2025-06-30 12:25 ` Mark Brown
2025-06-30 12:36 ` James Clark
2025-06-30 12:40 ` Mark Brown
2025-06-30 12:54 ` James Clark
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