Re: [Intel-gfx] [PATCH 1/4] drm/i915/gt: Disable arbitration around Braswell's pdp updates

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 11/01/2021 10:57, Chris Wilson wrote:
> Braswell's pdp workaround is full of dragons, that may be being angered
> when they are interrupted. Let's not take that risk and disable
> arbitrartion during the update.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 52c1fe62bdfe..10e9940cf3f5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2539,6 +2539,14 @@ static int emit_pdps(struct i915_request *rq)
>   	 * GPU hangs to forcewake errors and machine lockups!
>   	 */
>   
> +	cs = intel_ring_begin(rq, 2);
> +	if (IS_ERR(cs))
> +		return PTR_ERR(cs);
> +
> +	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> +	*cs++ = MI_NOOP;
> +	intel_ring_advance(rq, cs);
> +
>   	/* Flush any residual operations from the context load */
>   	err = engine->emit_flush(rq, EMIT_FLUSH);
>   	if (err)
> @@ -2564,7 +2572,8 @@ static int emit_pdps(struct i915_request *rq)
>   		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
>   		*cs++ = lower_32_bits(pd_daddr);
>   	}
> -	*cs++ = MI_NOOP;
> +	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> +	intel_ring_advance(rq, cs);
>   
>   	intel_ring_advance(rq, cs);
>   
> 

I had to remind myself that Gen8LP is indeed the only platform with 
32-bit ppgtt.

I presume you are fixing some sporadic CI failures here, anyway:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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