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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: Perform an arbitration check before busywaiting
Date: Mon, 11 Jan 2021 17:12:57 +0000	[thread overview]
Message-ID: <c8a89bfa-f5df-5f41-f5d9-a5042226e5ba@linux.intel.com> (raw)
In-Reply-To: <161038246850.28181.16757116420949491976@build.alporthouse.com>


On 11/01/2021 16:27, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2021-01-11 16:19:40)
>>
>> On 11/01/2021 10:57, Chris Wilson wrote:
>>> During igt_reset_nop_engine, it was observed that an unexpected failed
>>> engine reset lead to us busywaiting on the stop-ring semaphore (set
>>> during the reset preparations) on the first request afterwards. There was
>>> no explicit MI_ARB_CHECK in this sequence as the presumption was that
>>> the failed MI_SEMAPHORE_WAIT would itself act as an arbitration point.
>>> It did not in this circumstance, so force it.
>>
>> In other words MI_SEMAPHORE_POLL is not a preemption point? Can't
>> remember if I knew that or not..
> 
> MI_SEMAPHORE_WAIT | POLL is most definitely a preemption point on a
> miss.
> 
>> 1)
>> Why not the same handling in !gen12 version?
> 
> Because I think it's a bug in tgl [a0 at least]. I think I've seen the
> same symptoms on tgl before, but not earlier. This is the first time the
> sequence clicked as to why it was busy spinning. Random engine reset
> failures are rare enough -- I was meant to also write a test case to
> inject failure.

Random engine reset failure you think is a TGL issue?

>   
>> 2)
>> Failed reset leads to busy-hang in following request _tail_? But there
>> is an arb check at the start of following request as well. Or in cases
>> where we context switch into the middle of a previously executing request?
> 
> It was the first request submitted after the failed reset. We expect to
> clear the ring-stop flag on the CS IDLE->ACTIVE event.
> 
>> But why would that busy hang? Hasn't the failed request unpaused the ring?
> 
> The engine was idle at the time of the failed reset. We left the
> ring-stop set, and submitted the next batch of requests. We hit the
> MI_SEMAPHORE_WAIT(ring-stop) at the end of the first request, but
> without hitting an arbitration point (first request, no init-breadcrumb
> in this case), the semaphore was stuck.

So a kernel context request? Why hasn't IDLE->ACTIVE cleared ring stop? 
Presumably this CSB must come after the first request has been submitted 
so apparently I am still not getting how it hangs.

Just because igt_reset_nop_engine does things "quickly"? It prevents the 
CSB from arriving? So ARB_CHECK pickups up on the fact ELSP has been 
rewritten before the IDLE->ACTIVE even received and/or engine reset 
prevented it from arriving?

Regards,

Tvrtko
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  reply	other threads:[~2021-01-11 17:13 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-11 10:57 [Intel-gfx] [PATCH 1/4] drm/i915/gt: Disable arbitration around Braswell's pdp updates Chris Wilson
2021-01-11 10:57 ` [Intel-gfx] [PATCH 2/4] drm/i915/gt: Check for arbitration after writing start seqno Chris Wilson
2021-01-11 16:03   ` Tvrtko Ursulin
2021-01-11 16:10     ` Chris Wilson
2021-01-12  9:14       ` Tvrtko Ursulin
2021-01-11 10:57 ` [Intel-gfx] [PATCH 3/4] drm/i915/gt: Perform an arbitration check before busywaiting Chris Wilson
2021-01-11 16:19   ` Tvrtko Ursulin
2021-01-11 16:27     ` Chris Wilson
2021-01-11 17:12       ` Tvrtko Ursulin [this message]
2021-01-11 21:54         ` Chris Wilson
2021-01-12  9:21           ` Tvrtko Ursulin
2021-01-11 10:57 ` [Intel-gfx] [PATCH 4/4] drm/i915/selftests: Include engine name after reset failure Chris Wilson
2021-01-11 16:20   ` Tvrtko Ursulin
2021-01-11 12:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/gt: Disable arbitration around Braswell's pdp updates Patchwork
2021-01-11 14:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-11 15:53 ` [Intel-gfx] [PATCH 1/4] " Tvrtko Ursulin
2021-01-11 16:00   ` Chris Wilson

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