From: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Souza, Jose" <jose.souza@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 sel fetch in TGL pre-production
Date: Thu, 6 May 2021 10:06:49 +0000 [thread overview]
Message-ID: <03d1e7eba6260afcb03a38a80cf8be2e6849e6ca.camel@intel.com> (raw)
In-Reply-To: <20210505213801.80772-1-jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Wed, 2021-05-05 at 14:38 -0700, José Roberto de Souza wrote:
> The implementation of two workarounds are missing causing failures
> in CI with pre-production HW.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e3c30dcadcd1..406ba9a712a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -720,6 +720,13 @@ static bool
> intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> }
> }
>
> + /* Wa_14010254185 Wa_14010103792 */
> + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR2 sel fetch not enabled, missing the
> implementation of WAs\n");
> + return false;
> + }
> +
> return crtc_state->enable_psr2_sel_fetch = true;
> }
>
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prev parent reply other threads:[~2021-05-06 10:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 21:38 [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 sel fetch in TGL pre-production José Roberto de Souza
2021-05-05 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-05-06 1:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-06 17:44 ` Souza, Jose
2021-05-06 10:06 ` Mun, Gwan-gyeong [this message]
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