From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 sel fetch in TGL pre-production
Date: Wed, 5 May 2021 14:38:01 -0700 [thread overview]
Message-ID: <20210505213801.80772-1-jose.souza@intel.com> (raw)
The implementation of two workarounds are missing causing failures
in CI with pre-production HW.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e3c30dcadcd1..406ba9a712a8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -720,6 +720,13 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
}
}
+ /* Wa_14010254185 Wa_14010103792 */
+ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
+ return false;
+ }
+
return crtc_state->enable_psr2_sel_fetch = true;
}
--
2.31.1
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next reply other threads:[~2021-05-05 21:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 21:38 José Roberto de Souza [this message]
2021-05-05 23:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable PSR2 sel fetch in TGL pre-production Patchwork
2021-05-06 1:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-06 17:44 ` Souza, Jose
2021-05-06 10:06 ` [Intel-gfx] [PATCH] " Mun, Gwan-gyeong
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