From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/rpl-s: Add PCI IDS
Date: Mon, 15 Nov 2021 12:20:07 +0000 [thread overview]
Message-ID: <044a62c0-a02c-ff37-e53c-8e3db551cddd@linux.intel.com> (raw)
In-Reply-To: <20211112210825.1489596-2-anusha.srivatsa@intel.com>
On 12/11/2021 21:08, Anusha Srivatsa wrote:
> Adding PCI ids for RPL-S. Introducing RPL-S as a
> subplatform of ADL-S. From graphics POV,RPL-S is
> the same as ADL-S.
>
> BSpec: 53655
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
> drivers/gpu/drm/i915/intel_device_info.h | 3 +++
> include/drm/i915_pciids.h | 11 +++++++++++
> 6 files changed, 25 insertions(+)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 391a4e2b8604..fd2d3ab38ebb 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -554,6 +554,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
> INTEL_RKL_IDS(&gen11_early_ops),
> INTEL_ADLS_IDS(&gen11_early_ops),
> INTEL_ADLP_IDS(&gen11_early_ops),
> + INTEL_RPLS_IDS(&gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 21ff781b8149..406b9204d34b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1470,6 +1470,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define IS_DG2_G11(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> +#define IS_RAPTORLAKE_S(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 5e6795853dc3..9c33ae887f2e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1117,6 +1117,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_ADLS_IDS(&adl_s_info),
> INTEL_ADLP_IDS(&adl_p_info),
> INTEL_DG1_IDS(&dg1_info),
> + INTEL_RPLS_IDS(&adl_s_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 6e6b317bc33c..565b50c3f34f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -182,6 +182,10 @@ static const u16 subplatform_portf_ids[] = {
> INTEL_ICL_PORT_F_IDS(0),
> };
>
> +static const u16 subplatform_rpl_ids[] = {
> + INTEL_RPLS_IDS(0),
> +};
> +
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> {
> for (; num; num--, p++) {
> @@ -218,6 +222,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_portf_ids,
> ARRAY_SIZE(subplatform_portf_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_PORTF);
> + } else if (find_devid(devid, subplatform_rpl_ids,
> + ARRAY_SIZE(subplatform_rpl_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_RPL);
> }
>
> if (IS_TIGERLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..186e773fd0da 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -110,6 +110,9 @@ enum intel_platform {
> #define INTEL_SUBPLATFORM_G10 0
> #define INTEL_SUBPLATFORM_G11 1
>
> +/* RPL */
> +#define INTEL_SUBPLATFORM_RPL 0
The comment here should say to which platform the subplatform bits
apply. In this case that seems to be ADL_S.
Regards,
Tvrtko
> +
> enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index c00ac54692d7..00deb011b74c 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -666,4 +666,15 @@
> INTEL_VGA_DEVICE(0x46C2, info), \
> INTEL_VGA_DEVICE(0x46C3, info)
>
> +/* RPL-S */
> +#define INTEL_RPLS_IDS(info) \
> + INTEL_VGA_DEVICE(0xA780, info), \
> + INTEL_VGA_DEVICE(0xA781, info), \
> + INTEL_VGA_DEVICE(0xA782, info), \
> + INTEL_VGA_DEVICE(0xA783, info), \
> + INTEL_VGA_DEVICE(0xA788, info), \
> + INTEL_VGA_DEVICE(0xA789, info), \
> + INTEL_VGA_DEVICE(0xA78A, info), \
> + INTEL_VGA_DEVICE(0xA78B, info)
> +
> #endif /* _I915_PCIIDS_H */
>
next prev parent reply other threads:[~2021-11-15 12:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 21:08 [Intel-gfx] [PATCH 0/3] Introduce Raptor Lake S Anusha Srivatsa
2021-11-12 21:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/rpl-s: Add PCI IDS Anusha Srivatsa
2021-11-15 12:06 ` Jani Nikula
2021-11-16 18:08 ` Srivatsa, Anusha
2021-11-15 12:20 ` Tvrtko Ursulin [this message]
2021-11-12 21:08 ` [Intel-gfx] [PATCH 2/3] drm/i915/rpl-s: Add PCH ID Anusha Srivatsa
2021-11-15 12:08 ` Jani Nikula
2021-11-16 18:08 ` Srivatsa, Anusha
2021-11-12 21:08 ` [Intel-gfx] [PATCH 3/3] drm/i915/rpl-s: Enable guc submission by default Anusha Srivatsa
2021-11-15 12:10 ` Jani Nikula
2021-11-16 18:07 ` Srivatsa, Anusha
2021-11-12 21:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Raptor Lake S Patchwork
2021-11-12 21:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-11-12 21:56 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-11-12 22:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-13 1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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