Re: [Intel-gfx] [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC

["Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>]

On 2/28/2022 9:42 AM, Matt Roper wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Tell GuC that CCS is enabled by setting a bit in its ADS.
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Original-author: Michel Thierry
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_regs.h    | 3 +++
>   drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 84f189738a68..e629443e07ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1327,6 +1327,9 @@
>   #define   ECOBITS_PPGTT_CACHE64B		(3 << 8)
>   #define   ECOBITS_PPGTT_CACHE4B			(0 << 8)
>   
> +#define GEN12_RCU_MODE				_MMIO(0x14800)
> +#define   GEN12_RCU_MODE_CCS_ENABLE		REG_BIT(0)

Having the definition of this register in this patch is a bit weird, 
because we're save/restoring a register we're not programming. Maybe 
flip the order of this patch and the next one and move the register 
definition to that?

Daniele

> +
>   #define CHV_FUSE_GT				_MMIO(VLV_DISPLAY_BASE + 0x2168)
>   #define   CHV_FGT_DISABLE_SS0			(1 << 10)
>   #define   CHV_FGT_DISABLE_SS1			(1 << 11)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 847e00390b00..9bb551b83e7a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -335,6 +335,10 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
>   	ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
>   	ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
>   
> +	if (engine->class == RENDER_CLASS &&
> +	    CCS_MASK(engine->gt))
> +		ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true);
> +
>   	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
>   		ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
>   
> @@ -430,6 +434,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
>   				     struct iosys_map *info_map)
>   {
>   	info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1);
> +	info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt));
>   	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
>   	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
>   	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));