* [PATCH] drm/i915/display: change pipe order for platforms with big joiner
@ 2025-11-18 9:58 Jani Nikula
2025-11-18 13:28 ` ✗ i915.CI.BAT: failure for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Jani Nikula @ 2025-11-18 9:58 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
When big joiner is enabled, it reserves the adjacent pipe as the
secondary pipe. This happens without the user space knowing, and
subsequent attempts at using the CRTC with that pipe will fail. If the
user space does not have a coping mechanism, i.e. trying another pipe,
this leads to a black screen.
If the platform allows joining A+B, map the CRTCs to pipes in order A,
C, B, and D to trick userspace to using pipes that are more likely to be
available for joining.
Although there are currently no platforms with more than four pipes, add
a fallback for initializing the rest of the pipes to not miss them.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Let's see what breaks...
---
.../drm/i915/display/intel_display_driver.c | 26 ++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 7e000ba3e08b..83aad727017b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -452,6 +452,7 @@ bool intel_display_driver_check_access(struct intel_display *display)
/* part #2: call after irq install, but before gem init */
int intel_display_driver_probe_nogem(struct intel_display *display)
{
+ u8 pipe_mask = U8_MAX;
enum pipe pipe;
int ret;
@@ -470,7 +471,30 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
INTEL_NUM_PIPES(display),
INTEL_NUM_PIPES(display) > 1 ? "s" : "");
- for_each_pipe(display, pipe) {
+ /*
+ * If we have a joiner that can join A+B, expose the pipes in order A,
+ * C, B, D to trick user space into using pipes that are more likely to
+ * be available for both a) user space if pipe B has been reserved for
+ * the joiner, and b) the joiner if pipe A doesn't need the joiner.
+ *
+ * Fall back to normal initialization for the remaining pipes, if any.
+ */
+ if (HAS_BIGJOINER(display) && DISPLAY_VER(display) >= 12) {
+ enum pipe pipe_order[] = { PIPE_A, PIPE_C, PIPE_B, PIPE_D };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pipe_order); i++) {
+ pipe = pipe_order[i];
+
+ ret = intel_crtc_init(display, pipe);
+ if (ret)
+ goto err_mode_config;
+
+ pipe_mask &= ~BIT(pipe);
+ }
+ }
+
+ for_each_pipe_masked(display, pipe, pipe_mask) {
ret = intel_crtc_init(display, pipe);
if (ret)
goto err_mode_config;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 9:58 [PATCH] drm/i915/display: change pipe order for platforms with big joiner Jani Nikula
@ 2025-11-18 13:28 ` Patchwork
2025-11-18 13:37 ` [PATCH v2] " Jani Nikula
2025-11-18 16:32 ` ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner (rev2) Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2025-11-18 13:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7883 bytes --]
== Series Details ==
Series: drm/i915/display: change pipe order for platforms with big joiner
URL : https://patchwork.freedesktop.org/series/157704/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_17563 -> Patchwork_157704v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_157704v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_157704v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/index.html
Participating hosts (42 -> 42)
------------------------------
Additional (1): bat-adls-6
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_157704v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-adlp-6: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-adlp-6/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-adlp-6/igt@i915_module_load@load.html
- bat-arlh-2: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-arlh-2/igt@i915_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-arlh-2/igt@i915_module_load@load.html
- fi-rkl-11600: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/fi-rkl-11600/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/fi-rkl-11600/igt@i915_module_load@load.html
- bat-arlh-3: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-arlh-3/igt@i915_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-arlh-3/igt@i915_module_load@load.html
- bat-dg1-7: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg1-7/igt@i915_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg1-7/igt@i915_module_load@load.html
- bat-dg2-13: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg2-13/igt@i915_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg2-13/igt@i915_module_load@load.html
- bat-adlp-9: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-adlp-9/igt@i915_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-adlp-9/igt@i915_module_load@load.html
- bat-twl-2: [PASS][15] -> [ABORT][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-twl-2/igt@i915_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-twl-2/igt@i915_module_load@load.html
- bat-dg2-11: [PASS][17] -> [ABORT][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg2-11/igt@i915_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg2-11/igt@i915_module_load@load.html
- bat-rpls-4: [PASS][19] -> [ABORT][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-rpls-4/igt@i915_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-rpls-4/igt@i915_module_load@load.html
- bat-twl-1: [PASS][21] -> [ABORT][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-twl-1/igt@i915_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-twl-1/igt@i915_module_load@load.html
- bat-dg2-14: [PASS][23] -> [ABORT][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg2-14/igt@i915_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg2-14/igt@i915_module_load@load.html
- bat-arls-5: [PASS][25] -> [ABORT][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-arls-5/igt@i915_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-arls-5/igt@i915_module_load@load.html
- bat-rplp-1: [PASS][27] -> [ABORT][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-rplp-1/igt@i915_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-rplp-1/igt@i915_module_load@load.html
- fi-tgl-1115g4: [PASS][29] -> [ABORT][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/fi-tgl-1115g4/igt@i915_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/fi-tgl-1115g4/igt@i915_module_load@load.html
- bat-mtlp-6: [PASS][31] -> [ABORT][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-mtlp-6/igt@i915_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-mtlp-6/igt@i915_module_load@load.html
- bat-arls-6: [PASS][33] -> [ABORT][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-arls-6/igt@i915_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-arls-6/igt@i915_module_load@load.html
- bat-dg2-9: [PASS][35] -> [ABORT][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg2-9/igt@i915_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg2-9/igt@i915_module_load@load.html
- bat-adlp-11: [PASS][37] -> [ABORT][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-adlp-11/igt@i915_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-adlp-11/igt@i915_module_load@load.html
- bat-mtlp-8: [PASS][39] -> [ABORT][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-mtlp-8/igt@i915_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-mtlp-8/igt@i915_module_load@load.html
- bat-dg1-6: [PASS][41] -> [ABORT][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-dg1-6/igt@i915_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-dg1-6/igt@i915_module_load@load.html
- bat-adls-6: NOTRUN -> [ABORT][43]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-adls-6/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_157704v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@load:
- bat-mtlp-9: [PASS][44] -> [ABORT][45] ([i915#13494])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17563/bat-mtlp-9/igt@i915_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/bat-mtlp-9/igt@i915_module_load@load.html
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
Build changes
-------------
* Linux: CI_DRM_17563 -> Patchwork_157704v1
CI-20190529: 20190529
CI_DRM_17563: 78cb12e003b386a1935954330ade391f86beb18b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8630: 8630
Patchwork_157704v1: 78cb12e003b386a1935954330ade391f86beb18b @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v1/index.html
[-- Attachment #2: Type: text/html, Size: 8610 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 9:58 [PATCH] drm/i915/display: change pipe order for platforms with big joiner Jani Nikula
2025-11-18 13:28 ` ✗ i915.CI.BAT: failure for " Patchwork
@ 2025-11-18 13:37 ` Jani Nikula
2025-11-18 13:43 ` Jani Nikula
2025-11-18 16:32 ` ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner (rev2) Patchwork
2 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2025-11-18 13:37 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe
When big joiner is enabled, it reserves the adjacent pipe as the
secondary pipe. This happens without the user space knowing, and
subsequent attempts at using the CRTC with that pipe will fail. If the
user space does not have a coping mechanism, i.e. trying another pipe,
this leads to a black screen.
If the platform allows joining A+B, map the CRTCs to pipes in order A,
C, B, and D to trick userspace to using pipes that are more likely to be
available for joining.
Although there are currently no platforms with more than four pipes, add
a fallback for initializing the rest of the pipes to not miss them.
v2: Also remove WARN_ON()
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Let's see what breaks...
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 --
.../drm/i915/display/intel_display_driver.c | 26 ++++++++++++++++++-
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 9d2a23c96c61..11e58d07ddef 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -394,8 +394,6 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
- drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
-
if (HAS_CASF(display))
drm_crtc_create_sharpness_strength_property(&crtc->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 7e000ba3e08b..83aad727017b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -452,6 +452,7 @@ bool intel_display_driver_check_access(struct intel_display *display)
/* part #2: call after irq install, but before gem init */
int intel_display_driver_probe_nogem(struct intel_display *display)
{
+ u8 pipe_mask = U8_MAX;
enum pipe pipe;
int ret;
@@ -470,7 +471,30 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
INTEL_NUM_PIPES(display),
INTEL_NUM_PIPES(display) > 1 ? "s" : "");
- for_each_pipe(display, pipe) {
+ /*
+ * If we have a joiner that can join A+B, expose the pipes in order A,
+ * C, B, D to trick user space into using pipes that are more likely to
+ * be available for both a) user space if pipe B has been reserved for
+ * the joiner, and b) the joiner if pipe A doesn't need the joiner.
+ *
+ * Fall back to normal initialization for the remaining pipes, if any.
+ */
+ if (HAS_BIGJOINER(display) && DISPLAY_VER(display) >= 12) {
+ enum pipe pipe_order[] = { PIPE_A, PIPE_C, PIPE_B, PIPE_D };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pipe_order); i++) {
+ pipe = pipe_order[i];
+
+ ret = intel_crtc_init(display, pipe);
+ if (ret)
+ goto err_mode_config;
+
+ pipe_mask &= ~BIT(pipe);
+ }
+ }
+
+ for_each_pipe_masked(display, pipe, pipe_mask) {
ret = intel_crtc_init(display, pipe);
if (ret)
goto err_mode_config;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 13:37 ` [PATCH v2] " Jani Nikula
@ 2025-11-18 13:43 ` Jani Nikula
2025-11-18 17:40 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2025-11-18 13:43 UTC (permalink / raw)
To: intel-gfx, intel-xe
On Tue, 18 Nov 2025, Jani Nikula <jani.nikula@intel.com> wrote:
> When big joiner is enabled, it reserves the adjacent pipe as the
> secondary pipe. This happens without the user space knowing, and
> subsequent attempts at using the CRTC with that pipe will fail. If the
> user space does not have a coping mechanism, i.e. trying another pipe,
> this leads to a black screen.
>
> If the platform allows joining A+B, map the CRTCs to pipes in order A,
> C, B, and D to trick userspace to using pipes that are more likely to be
> available for joining.
>
> Although there are currently no platforms with more than four pipes, add
> a fallback for initializing the rest of the pipes to not miss them.
>
> v2: Also remove WARN_ON()
There's still this in intel_atomic_check_joiner():
/*
* The state copy logic assumes the primary crtc gets processed
* before the secondary crtc during the main compute_config loop.
* This works because the crtcs are created in pipe order,
* and the hardware requires primary pipe < secondary pipe as well.
* Should that change we need to rethink the logic.
*/
if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
drm_crtc_index(&secondary_crtc->base)))
return -EINVAL;
This still works for A+B and C+D joining, but will fail loudly for B+C
joining.
Ideas?
BR,
Jani.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Let's see what breaks...
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 --
> .../drm/i915/display/intel_display_driver.c | 26 ++++++++++++++++++-
> 2 files changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 9d2a23c96c61..11e58d07ddef 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -394,8 +394,6 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
>
> cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
>
> - drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
> -
> if (HAS_CASF(display))
> drm_crtc_create_sharpness_strength_property(&crtc->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 7e000ba3e08b..83aad727017b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -452,6 +452,7 @@ bool intel_display_driver_check_access(struct intel_display *display)
> /* part #2: call after irq install, but before gem init */
> int intel_display_driver_probe_nogem(struct intel_display *display)
> {
> + u8 pipe_mask = U8_MAX;
> enum pipe pipe;
> int ret;
>
> @@ -470,7 +471,30 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
> INTEL_NUM_PIPES(display),
> INTEL_NUM_PIPES(display) > 1 ? "s" : "");
>
> - for_each_pipe(display, pipe) {
> + /*
> + * If we have a joiner that can join A+B, expose the pipes in order A,
> + * C, B, D to trick user space into using pipes that are more likely to
> + * be available for both a) user space if pipe B has been reserved for
> + * the joiner, and b) the joiner if pipe A doesn't need the joiner.
> + *
> + * Fall back to normal initialization for the remaining pipes, if any.
> + */
> + if (HAS_BIGJOINER(display) && DISPLAY_VER(display) >= 12) {
> + enum pipe pipe_order[] = { PIPE_A, PIPE_C, PIPE_B, PIPE_D };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pipe_order); i++) {
> + pipe = pipe_order[i];
> +
> + ret = intel_crtc_init(display, pipe);
> + if (ret)
> + goto err_mode_config;
> +
> + pipe_mask &= ~BIT(pipe);
> + }
> + }
> +
> + for_each_pipe_masked(display, pipe, pipe_mask) {
> ret = intel_crtc_init(display, pipe);
> if (ret)
> goto err_mode_config;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner (rev2)
2025-11-18 9:58 [PATCH] drm/i915/display: change pipe order for platforms with big joiner Jani Nikula
2025-11-18 13:28 ` ✗ i915.CI.BAT: failure for " Patchwork
2025-11-18 13:37 ` [PATCH v2] " Jani Nikula
@ 2025-11-18 16:32 ` Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2025-11-18 16:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10504 bytes --]
== Series Details ==
Series: drm/i915/display: change pipe order for platforms with big joiner (rev2)
URL : https://patchwork.freedesktop.org/series/157704/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_17565 -> Patchwork_157704v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_157704v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_157704v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/index.html
Participating hosts (46 -> 45)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_157704v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- fi-rkl-11600: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/fi-rkl-11600/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/fi-rkl-11600/igt@i915_module_load@load.html
- bat-twl-1: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-twl-1/igt@i915_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-twl-1/igt@i915_module_load@load.html
- bat-twl-2: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-twl-2/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-twl-2/igt@i915_module_load@load.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-1:
- bat-dg2-8: [PASS][7] -> [FAIL][8] +20 other tests fail
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-b-dp-6:
- bat-mtlp-9: [PASS][9] -> [FAIL][10] +20 other tests fail
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-b-dp-6.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-b-dp-6.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-rplp-1: [PASS][11] -> [FAIL][12] +20 other tests fail
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-rplp-1/igt@kms_pipe_crc_basic@hang-read-crc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-rplp-1/igt@kms_pipe_crc_basic@hang-read-crc.html
- fi-tgl-1115g4: [PASS][13] -> [FAIL][14] +20 other tests fail
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/fi-tgl-1115g4/igt@kms_pipe_crc_basic@hang-read-crc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/fi-tgl-1115g4/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-3:
- bat-arls-5: [PASS][15] -> [FAIL][16] +20 other tests fail
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-arls-5/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-3.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-arls-5/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-3.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-hdmi-a-1:
- bat-adls-6: [PASS][17] -> [FAIL][18] +20 other tests fail
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-adls-6/igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-hdmi-a-1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-adls-6/igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-hdmi-a-1.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-arlh-3: [PASS][19] -> [FAIL][20] +20 other tests fail
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-arlh-3/igt@kms_pipe_crc_basic@nonblocking-crc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-arlh-3/igt@kms_pipe_crc_basic@nonblocking-crc.html
- bat-dg1-7: [PASS][21] -> [FAIL][22] +20 other tests fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg1-7/igt@kms_pipe_crc_basic@nonblocking-crc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg1-7/igt@kms_pipe_crc_basic@nonblocking-crc.html
- bat-adlp-9: [PASS][23] -> [FAIL][24] +20 other tests fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-adlp-9/igt@kms_pipe_crc_basic@nonblocking-crc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-adlp-9/igt@kms_pipe_crc_basic@nonblocking-crc.html
- bat-rpls-4: [PASS][25] -> [FAIL][26] +20 other tests fail
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-rpls-4/igt@kms_pipe_crc_basic@nonblocking-crc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-rpls-4/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][27] -> [FAIL][28] +20 other tests fail
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-9: [PASS][29] -> [FAIL][30] +20 other tests fail
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-edp-1:
- bat-mtlp-8: [PASS][31] -> [FAIL][32] +20 other tests fail
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-mtlp-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-edp-1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-mtlp-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-edp-1.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-dg2-14: [PASS][33] -> [FAIL][34] +20 other tests fail
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-14/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-14/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
- bat-arls-6: [PASS][35] -> [FAIL][36] +20 other tests fail
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-arls-6/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-arls-6/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-3:
- bat-adlp-6: [PASS][37] -> [FAIL][38] +20 other tests fail
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-3.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-3.html
Known issues
------------
Here are the changes found in Patchwork_157704v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live:
- bat-adlp-6: [PASS][39] -> [ABORT][40] ([i915#14365]) +1 other test abort
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-adlp-6/igt@i915_selftest@live.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-adlp-6/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-9: [PASS][41] -> [DMESG-FAIL][42] ([i915#12061]) +1 other test dmesg-fail
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-9/igt@i915_selftest@live@workarounds.html
- bat-dg2-14: [PASS][43] -> [DMESG-FAIL][44] ([i915#12061]) +1 other test dmesg-fail
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-atsm-1: [DMESG-FAIL][45] ([i915#12061] / [i915#13929]) -> [DMESG-FAIL][46] ([i915#12061] / [i915#14204])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-atsm-1/igt@i915_selftest@live.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-atsm-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@mman:
- bat-atsm-1: [DMESG-FAIL][47] ([i915#13929]) -> [DMESG-FAIL][48] ([i915#14204])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17565/bat-atsm-1/igt@i915_selftest@live@mman.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-atsm-1/igt@i915_selftest@live@mman.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
[i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
[i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
Build changes
-------------
* Linux: CI_DRM_17565 -> Patchwork_157704v2
CI-20190529: 20190529
CI_DRM_17565: b603326a067916accf680fd623f4fc3c22bba487 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8631: 8631
Patchwork_157704v2: b603326a067916accf680fd623f4fc3c22bba487 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/index.html
[-- Attachment #2: Type: text/html, Size: 11946 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 13:43 ` Jani Nikula
@ 2025-11-18 17:40 ` Ville Syrjälä
2025-11-18 19:34 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2025-11-18 17:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Nov 18, 2025 at 03:43:35PM +0200, Jani Nikula wrote:
> On Tue, 18 Nov 2025, Jani Nikula <jani.nikula@intel.com> wrote:
> > When big joiner is enabled, it reserves the adjacent pipe as the
> > secondary pipe. This happens without the user space knowing, and
> > subsequent attempts at using the CRTC with that pipe will fail. If the
> > user space does not have a coping mechanism, i.e. trying another pipe,
> > this leads to a black screen.
> >
> > If the platform allows joining A+B, map the CRTCs to pipes in order A,
> > C, B, and D to trick userspace to using pipes that are more likely to be
> > available for joining.
> >
> > Although there are currently no platforms with more than four pipes, add
> > a fallback for initializing the rest of the pipes to not miss them.
> >
> > v2: Also remove WARN_ON()
>
> There's still this in intel_atomic_check_joiner():
>
> /*
> * The state copy logic assumes the primary crtc gets processed
> * before the secondary crtc during the main compute_config loop.
> * This works because the crtcs are created in pipe order,
> * and the hardware requires primary pipe < secondary pipe as well.
> * Should that change we need to rethink the logic.
> */
> if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
> drm_crtc_index(&secondary_crtc->base)))
> return -EINVAL;
>
> This still works for A+B and C+D joining, but will fail loudly for B+C
> joining.
>
> Ideas?
Hmm, I think I got rid of that requirement semi-accidentally in
commit 3a5e09d82f97 ("drm/i915: Fix intel_modeset_pipe_config_late() for
bigjoiner")
So it looks to me like we can just drop that check entirely.
>
> BR,
> Jani.
>
>
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > ---
> >
> > Let's see what breaks...
> > ---
> > drivers/gpu/drm/i915/display/intel_crtc.c | 2 --
> > .../drm/i915/display/intel_display_driver.c | 26 ++++++++++++++++++-
> > 2 files changed, 25 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 9d2a23c96c61..11e58d07ddef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -394,8 +394,6 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
> >
> > cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
> >
> > - drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
> > -
> > if (HAS_CASF(display))
> > drm_crtc_create_sharpness_strength_property(&crtc->base);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 7e000ba3e08b..83aad727017b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -452,6 +452,7 @@ bool intel_display_driver_check_access(struct intel_display *display)
> > /* part #2: call after irq install, but before gem init */
> > int intel_display_driver_probe_nogem(struct intel_display *display)
> > {
> > + u8 pipe_mask = U8_MAX;
> > enum pipe pipe;
> > int ret;
> >
> > @@ -470,7 +471,30 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
> > INTEL_NUM_PIPES(display),
> > INTEL_NUM_PIPES(display) > 1 ? "s" : "");
> >
> > - for_each_pipe(display, pipe) {
> > + /*
> > + * If we have a joiner that can join A+B, expose the pipes in order A,
> > + * C, B, D to trick user space into using pipes that are more likely to
> > + * be available for both a) user space if pipe B has been reserved for
> > + * the joiner, and b) the joiner if pipe A doesn't need the joiner.
> > + *
> > + * Fall back to normal initialization for the remaining pipes, if any.
> > + */
> > + if (HAS_BIGJOINER(display) && DISPLAY_VER(display) >= 12) {
> > + enum pipe pipe_order[] = { PIPE_A, PIPE_C, PIPE_B, PIPE_D };
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pipe_order); i++) {
> > + pipe = pipe_order[i];
> > +
> > + ret = intel_crtc_init(display, pipe);
> > + if (ret)
> > + goto err_mode_config;
> > +
> > + pipe_mask &= ~BIT(pipe);
> > + }
> > + }
> > +
> > + for_each_pipe_masked(display, pipe, pipe_mask) {
> > ret = intel_crtc_init(display, pipe);
> > if (ret)
> > goto err_mode_config;
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 17:40 ` Ville Syrjälä
@ 2025-11-18 19:34 ` Ville Syrjälä
2025-11-19 13:09 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2025-11-18 19:34 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Nov 18, 2025 at 07:40:06PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 18, 2025 at 03:43:35PM +0200, Jani Nikula wrote:
> > On Tue, 18 Nov 2025, Jani Nikula <jani.nikula@intel.com> wrote:
> > > When big joiner is enabled, it reserves the adjacent pipe as the
> > > secondary pipe. This happens without the user space knowing, and
> > > subsequent attempts at using the CRTC with that pipe will fail. If the
> > > user space does not have a coping mechanism, i.e. trying another pipe,
> > > this leads to a black screen.
> > >
> > > If the platform allows joining A+B, map the CRTCs to pipes in order A,
> > > C, B, and D to trick userspace to using pipes that are more likely to be
> > > available for joining.
> > >
> > > Although there are currently no platforms with more than four pipes, add
> > > a fallback for initializing the rest of the pipes to not miss them.
> > >
> > > v2: Also remove WARN_ON()
> >
> > There's still this in intel_atomic_check_joiner():
> >
> > /*
> > * The state copy logic assumes the primary crtc gets processed
> > * before the secondary crtc during the main compute_config loop.
> > * This works because the crtcs are created in pipe order,
> > * and the hardware requires primary pipe < secondary pipe as well.
> > * Should that change we need to rethink the logic.
> > */
> > if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
> > drm_crtc_index(&secondary_crtc->base)))
> > return -EINVAL;
> >
> > This still works for A+B and C+D joining, but will fail loudly for B+C
> > joining.
> >
> > Ideas?
>
> Hmm, I think I got rid of that requirement semi-accidentally in
> commit 3a5e09d82f97 ("drm/i915: Fix intel_modeset_pipe_config_late() for
> bigjoiner")
>
> So it looks to me like we can just drop that check entirely.
After some pondering we might have a bit of problem with
the for_each_intel_crtc*() stuff. At least during
the hardware programming phase we'd like those to walk the
crtcs in pipe order but currently they use the crtc index
order.
Say we have a commit with pipes A+B,C. Currently we do
everything in the C->B->A or A->B->C order. Thus the joined
pipe A+B are always updated back-to-back, giving us the best
chance to get an atomic update across them. With the shuffling
pipe C will now sneak in between A and B, making it less likely
that the updates on A and B will happen on the same frame.
So I'm thinking we probably want to change all the
for_each_intel_crtc*() macros to use the pipe order as well.
Either that or we need to review each use case and rewrite
the important ones to use the pipe order.
for_each_pipe_crtc_modeset_{disable,enable}() are fortunately
already immune to crtc shuffling. Those absolutely have to use
the correct pipe order or else we'd completely screw up the
joiner programming sequence during modesets.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 19:34 ` Ville Syrjälä
@ 2025-11-19 13:09 ` Jani Nikula
2025-11-19 18:36 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2025-11-19 13:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On Tue, 18 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Nov 18, 2025 at 07:40:06PM +0200, Ville Syrjälä wrote:
>> On Tue, Nov 18, 2025 at 03:43:35PM +0200, Jani Nikula wrote:
>> > On Tue, 18 Nov 2025, Jani Nikula <jani.nikula@intel.com> wrote:
>> > > When big joiner is enabled, it reserves the adjacent pipe as the
>> > > secondary pipe. This happens without the user space knowing, and
>> > > subsequent attempts at using the CRTC with that pipe will fail. If the
>> > > user space does not have a coping mechanism, i.e. trying another pipe,
>> > > this leads to a black screen.
>> > >
>> > > If the platform allows joining A+B, map the CRTCs to pipes in order A,
>> > > C, B, and D to trick userspace to using pipes that are more likely to be
>> > > available for joining.
>> > >
>> > > Although there are currently no platforms with more than four pipes, add
>> > > a fallback for initializing the rest of the pipes to not miss them.
>> > >
>> > > v2: Also remove WARN_ON()
>> >
>> > There's still this in intel_atomic_check_joiner():
>> >
>> > /*
>> > * The state copy logic assumes the primary crtc gets processed
>> > * before the secondary crtc during the main compute_config loop.
>> > * This works because the crtcs are created in pipe order,
>> > * and the hardware requires primary pipe < secondary pipe as well.
>> > * Should that change we need to rethink the logic.
>> > */
>> > if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
>> > drm_crtc_index(&secondary_crtc->base)))
>> > return -EINVAL;
>> >
>> > This still works for A+B and C+D joining, but will fail loudly for B+C
>> > joining.
>> >
>> > Ideas?
>>
>> Hmm, I think I got rid of that requirement semi-accidentally in
>> commit 3a5e09d82f97 ("drm/i915: Fix intel_modeset_pipe_config_late() for
>> bigjoiner")
>>
>> So it looks to me like we can just drop that check entirely.
>
> After some pondering we might have a bit of problem with
> the for_each_intel_crtc*() stuff. At least during
> the hardware programming phase we'd like those to walk the
> crtcs in pipe order but currently they use the crtc index
> order.
>
> Say we have a commit with pipes A+B,C. Currently we do
> everything in the C->B->A or A->B->C order. Thus the joined
> pipe A+B are always updated back-to-back, giving us the best
> chance to get an atomic update across them. With the shuffling
> pipe C will now sneak in between A and B, making it less likely
> that the updates on A and B will happen on the same frame.
>
> So I'm thinking we probably want to change all the
> for_each_intel_crtc*() macros to use the pipe order as well.
> Either that or we need to review each use case and rewrite
> the important ones to use the pipe order.
Could this be the cause for [1]?
BR,
Jani.
[1] https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-twl-2/igt@i915_module_load@load.html#dmesg-warnings352
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915/display: change pipe order for platforms with big joiner
2025-11-19 13:09 ` Jani Nikula
@ 2025-11-19 18:36 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2025-11-19 18:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Wed, Nov 19, 2025 at 03:09:20PM +0200, Jani Nikula wrote:
> On Tue, 18 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Nov 18, 2025 at 07:40:06PM +0200, Ville Syrjälä wrote:
> >> On Tue, Nov 18, 2025 at 03:43:35PM +0200, Jani Nikula wrote:
> >> > On Tue, 18 Nov 2025, Jani Nikula <jani.nikula@intel.com> wrote:
> >> > > When big joiner is enabled, it reserves the adjacent pipe as the
> >> > > secondary pipe. This happens without the user space knowing, and
> >> > > subsequent attempts at using the CRTC with that pipe will fail. If the
> >> > > user space does not have a coping mechanism, i.e. trying another pipe,
> >> > > this leads to a black screen.
> >> > >
> >> > > If the platform allows joining A+B, map the CRTCs to pipes in order A,
> >> > > C, B, and D to trick userspace to using pipes that are more likely to be
> >> > > available for joining.
> >> > >
> >> > > Although there are currently no platforms with more than four pipes, add
> >> > > a fallback for initializing the rest of the pipes to not miss them.
> >> > >
> >> > > v2: Also remove WARN_ON()
> >> >
> >> > There's still this in intel_atomic_check_joiner():
> >> >
> >> > /*
> >> > * The state copy logic assumes the primary crtc gets processed
> >> > * before the secondary crtc during the main compute_config loop.
> >> > * This works because the crtcs are created in pipe order,
> >> > * and the hardware requires primary pipe < secondary pipe as well.
> >> > * Should that change we need to rethink the logic.
> >> > */
> >> > if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
> >> > drm_crtc_index(&secondary_crtc->base)))
> >> > return -EINVAL;
> >> >
> >> > This still works for A+B and C+D joining, but will fail loudly for B+C
> >> > joining.
> >> >
> >> > Ideas?
> >>
> >> Hmm, I think I got rid of that requirement semi-accidentally in
> >> commit 3a5e09d82f97 ("drm/i915: Fix intel_modeset_pipe_config_late() for
> >> bigjoiner")
> >>
> >> So it looks to me like we can just drop that check entirely.
> >
> > After some pondering we might have a bit of problem with
> > the for_each_intel_crtc*() stuff. At least during
> > the hardware programming phase we'd like those to walk the
> > crtcs in pipe order but currently they use the crtc index
> > order.
> >
> > Say we have a commit with pipes A+B,C. Currently we do
> > everything in the C->B->A or A->B->C order. Thus the joined
> > pipe A+B are always updated back-to-back, giving us the best
> > chance to get an atomic update across them. With the shuffling
> > pipe C will now sneak in between A and B, making it less likely
> > that the updates on A and B will happen on the same frame.
> >
> > So I'm thinking we probably want to change all the
> > for_each_intel_crtc*() macros to use the pipe order as well.
> > Either that or we need to review each use case and rewrite
> > the important ones to use the pipe order.
>
> Could this be the cause for [1]?
>
> BR,
> Jani.
>
>
> [1] https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157704v2/bat-twl-2/igt@i915_module_load@load.html#dmesg-warnings352
That seems to claim that someone used a vblank work already during
driver load, or the list is corrupted or something. I don't think
that should happen, so I guess someone needs to figure out where
that is coming from. Also I can't think of a reason why it would
only happen with the crts reordered...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-11-19 18:36 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-18 9:58 [PATCH] drm/i915/display: change pipe order for platforms with big joiner Jani Nikula
2025-11-18 13:28 ` ✗ i915.CI.BAT: failure for " Patchwork
2025-11-18 13:37 ` [PATCH v2] " Jani Nikula
2025-11-18 13:43 ` Jani Nikula
2025-11-18 17:40 ` Ville Syrjälä
2025-11-18 19:34 ` Ville Syrjälä
2025-11-19 13:09 ` Jani Nikula
2025-11-19 18:36 ` Ville Syrjälä
2025-11-18 16:32 ` ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner (rev2) Patchwork
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