From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eric Anholt <eric@anholt.net>, intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Prevent use of pages >4GiB on 965G[M]
Date: Thu, 21 Apr 2011 07:03:13 +0100 [thread overview]
Message-ID: <0d30dc$lu8ama@orsmga001.jf.intel.com> (raw)
In-Reply-To: <87oc40o3o0.fsf@pollan.anholt.net>
On Wed, 20 Apr 2011 17:21:03 -0700, Eric Anholt <eric@anholt.net> wrote:
> On Sun, 17 Apr 2011 17:37:32 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > The 965G (Broadwater) and 965GM (Crestline) chipsets had many errata in
> > handling pages allocation above 4GiB. So we should be careful never to
> > allocate and attempt to pass such through to the GPU and so limit
> > ourselves to GFP_DMA32 on those chipsets.
>
> Unfortunate to see this -- were there more particular bugs in >4GB
> handling found, or is it just "I'm tired of worrying about it, let's
> avoid this class of problem"? I'm not saying "no" to this patch for
> either answer, just curious.
It's an investigatory patch because 965GM is still misbehaving, and those
warnings in the docs scared me.
A solution in search of a problem, i.e. it may help someone and that would
be very useful to know.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
prev parent reply other threads:[~2011-04-21 6:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-17 16:37 [PATCH] drm/i915: Prevent use of pages >4GiB on 965G[M] Chris Wilson
2011-04-21 0:21 ` Eric Anholt
2011-04-21 6:03 ` Chris Wilson [this message]
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