From: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Souza, Jose" <jose.souza@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE
Date: Thu, 22 Apr 2021 11:01:18 +0000 [thread overview]
Message-ID: <0dee62fca74a24216a60afa945b4f02582d1b720.camel@intel.com> (raw)
In-Reply-To: <20210421220224.200729-2-jose.souza@intel.com>
Looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote:
> EDP_Y_COORDINATE_ENABLE became a reserved register in display 13.
> EDP_Y_COORDINATE_VALID have the same fate as EDP_Y_COORDINATE_ENABLE
> but as we don't need it, removing the macro definition of it.
>
> BSpec: 50422
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4ad756e238c5..66335ec6b7d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -524,7 +524,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> val = psr_compute_idle_frames(intel_dp) <<
> EDP_PSR2_IDLE_FRAME_SHIFT;
>
> val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> val |= EDP_Y_COORDINATE_ENABLE;
>
> val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency
> + 1);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 66a902b3bb8e..e18576c94cef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4569,8 +4569,7 @@ enum {
> #define EDP_SU_TRACK_ENABLE (1 << 30)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
> -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and
> CNL+ */
> -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and
> CNL+ */
> +#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display
> 10, 11 and 12 */
> #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
> #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
> #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
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next prev parent reply other threads:[~2021-04-22 11:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 22:02 [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec José Roberto de Souza
2021-04-21 22:02 ` [Intel-gfx] [PATCH 2/2] drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE José Roberto de Souza
2021-04-22 11:01 ` Mun, Gwan-gyeong [this message]
2021-04-21 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec Patchwork
2021-04-21 22:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-21 23:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-22 9:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-04-23 15:23 ` Souza, Jose
2021-04-22 11:00 ` [Intel-gfx] [PATCH 1/2] " Mun, Gwan-gyeong
2021-04-23 10:25 ` Maarten Lankhorst
2021-04-23 14:52 ` Souza, Jose
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