[RESEND 0/4] drm/i915/display: start switching to display specific reg types

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* [RESEND 0/4] drm/i915/display: start switching to display specific reg types
@ 2026-05-05  9:16 Jani Nikula
  2026-05-05  9:16 ` [RESEND 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
                   ` (6 more replies)
  0 siblings, 7 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-05  9:16 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Michał Grzelak, ville.syrjala


Jani Nikula (4):
  drm/i915/display: add typedef for intel_reg_t and use it
  drm/i915/display: add struct intel_irq_regs and use it
  drm/i915/display: add struct intel_error_regs and use it
  drm/i915/display: define and use intel_reg_{offset,equal,valid}()
    helpers

 drivers/gpu/drm/i915/display/g4x_dp.c         |  4 +-
 drivers/gpu/drm/i915/display/g4x_dp.h         | 10 ++--
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |  2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.h       |  6 +--
 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_color.c    |  4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |  6 +--
 drivers/gpu/drm/i915/display/intel_crt.h      |  6 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 26 +++++-----
 drivers/gpu/drm/i915/display/intel_ddi.h      |  6 +--
 drivers/gpu/drm/i915/display/intel_de.c       | 30 +++++------
 drivers/gpu/drm/i915/display/intel_de.h       | 48 +++++++++---------
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +--
 drivers/gpu/drm/i915/display/intel_display.h  | 10 ++--
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  | 20 ++++----
 .../drm/i915/display/intel_display_power.c    |  4 +-
 .../i915/display/intel_display_power_well.c   |  8 +--
 .../drm/i915/display/intel_display_reg_defs.h | 35 +++++++++++++
 .../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++----------
 .../drm/i915/display/intel_display_types.h    | 12 ++---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 50 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   | 14 +++---
 drivers/gpu/drm/i915/display/intel_dmc_wl.h   |  6 +--
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   | 28 +++++------
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  8 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 ++++++------
 drivers/gpu/drm/i915/display/intel_dsb.c      | 22 ++++----
 drivers/gpu/drm/i915/display/intel_dsb.h      | 10 ++--
 drivers/gpu/drm/i915/display/intel_dvo_dev.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      | 12 ++---
 .../drm/i915/display/intel_fifo_underrun.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 28 +++++------
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  6 +--
 drivers/gpu/drm/i915/display/intel_lvds.c     |  6 +--
 drivers/gpu/drm/i915/display/intel_lvds.h     |  6 +--
 drivers/gpu/drm/i915/display/intel_mchbar.c   | 14 +++---
 drivers/gpu/drm/i915/display/intel_mchbar.h   |  8 +--
 .../gpu/drm/i915/display/intel_pch_display.c  | 14 +++---
 drivers/gpu/drm/i915/display/intel_pps.c      | 38 +++++++-------
 drivers/gpu/drm/i915/display/intel_psr.c      | 36 ++++++-------
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  6 +--
 drivers/gpu/drm/i915/display/intel_sdvo.h     | 10 ++--
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  4 +-
 drivers/gpu/drm/i915/display/intel_tc.c       | 10 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 10 ++--
 drivers/gpu/drm/i915/display/intel_vga.c      |  4 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        | 16 +++---
 55 files changed, 377 insertions(+), 342 deletions(-)

-- 
2.47.3


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [RESEND 1/4] drm/i915/display: add typedef for intel_reg_t and use it
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
@ 2026-05-05  9:16 ` Jani Nikula
  2026-05-05  9:16 ` [RESEND 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-05  9:16 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Michał Grzelak, ville.syrjala

Add a typedef alias intel_reg_t for i915_reg_t, and use it exclusively
in display code. The goal is to eventually define a distinct type for
display, but for now just use an alias.

In a handful of places include intel_display_reg_defs.h instead of
i915_reg_defs.h to get the definition, and isolate the i915_reg_defs.h
include there.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c         |  4 +-
 drivers/gpu/drm/i915/display/g4x_dp.h         | 10 ++--
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |  2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.h       |  6 +--
 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_color.c    |  4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |  6 +--
 drivers/gpu/drm/i915/display/intel_crt.h      |  6 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 26 +++++-----
 drivers/gpu/drm/i915/display/intel_ddi.h      |  6 +--
 drivers/gpu/drm/i915/display/intel_de.c       | 30 ++++++------
 drivers/gpu/drm/i915/display/intel_de.h       | 48 +++++++++----------
 drivers/gpu/drm/i915/display/intel_display.c  |  8 ++--
 drivers/gpu/drm/i915/display/intel_display.h  | 10 ++--
 .../gpu/drm/i915/display/intel_display_irq.c  | 10 ++--
 .../drm/i915/display/intel_display_power.c    |  4 +-
 .../i915/display/intel_display_power_well.c   |  8 ++--
 .../drm/i915/display/intel_display_reg_defs.h |  2 +
 .../drm/i915/display/intel_display_types.h    |  8 ++--
 drivers/gpu/drm/i915/display/intel_dmc.c      | 24 +++++-----
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |  8 ++--
 drivers/gpu/drm/i915/display/intel_dmc_wl.h   |  6 +--
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   | 28 +++++------
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  8 ++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +++++------
 drivers/gpu/drm/i915/display/intel_dsb.c      | 12 ++---
 drivers/gpu/drm/i915/display/intel_dsb.h      | 10 ++--
 drivers/gpu/drm/i915/display/intel_dvo_dev.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      | 12 ++---
 .../drm/i915/display/intel_fifo_underrun.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 28 +++++------
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  6 +--
 drivers/gpu/drm/i915/display/intel_lvds.c     |  6 +--
 drivers/gpu/drm/i915/display/intel_lvds.h     |  6 +--
 drivers/gpu/drm/i915/display/intel_mchbar.c   | 10 ++--
 drivers/gpu/drm/i915/display/intel_mchbar.h   |  8 ++--
 .../gpu/drm/i915/display/intel_pch_display.c  | 14 +++---
 drivers/gpu/drm/i915/display/intel_pps.c      | 32 ++++++-------
 drivers/gpu/drm/i915/display/intel_psr.c      | 36 +++++++-------
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  6 +--
 drivers/gpu/drm/i915/display/intel_sdvo.h     | 10 ++--
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  4 +-
 drivers/gpu/drm/i915/display/intel_tc.c       | 10 ++--
 drivers/gpu/drm/i915/display/intel_vblank.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 10 ++--
 drivers/gpu/drm/i915/display/intel_vga.c      |  4 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        | 16 +++----
 53 files changed, 283 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 5e74d8a3ba5c..5ff1cdf4581a 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -273,7 +273,7 @@ static bool cpt_dp_port_selected(struct intel_display *display,
 }
 
 bool g4x_dp_port_enabled(struct intel_display *display,
-			 i915_reg_t dp_reg, enum port port,
+			 intel_reg_t dp_reg, enum port port,
 			 enum pipe *pipe)
 {
 	bool ret;
@@ -1280,7 +1280,7 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
 };
 
 bool g4x_dp_init(struct intel_display *display,
-		 i915_reg_t output_reg, enum port port)
+		 intel_reg_t output_reg, enum port port)
 {
 	const struct intel_bios_encoder_data *devdata;
 	struct intel_digital_port *dig_port;
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h
index 0b28951b8365..99de690ebe7f 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.h
+++ b/drivers/gpu/drm/i915/display/g4x_dp.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum pipe;
 enum port;
@@ -20,23 +20,23 @@ struct intel_encoder;
 #ifdef I915
 const struct dpll *vlv_get_dpll(struct intel_display *display);
 bool g4x_dp_port_enabled(struct intel_display *display,
-			 i915_reg_t dp_reg, enum port port,
+			 intel_reg_t dp_reg, enum port port,
 			 enum pipe *pipe);
 bool g4x_dp_init(struct intel_display *display,
-		 i915_reg_t output_reg, enum port port);
+		 intel_reg_t output_reg, enum port port);
 #else
 static inline const struct dpll *vlv_get_dpll(struct intel_display *display)
 {
 	return NULL;
 }
 static inline bool g4x_dp_port_enabled(struct intel_display *display,
-				       i915_reg_t dp_reg, int port,
+				       intel_reg_t dp_reg, int port,
 				       enum pipe *pipe)
 {
 	return false;
 }
 static inline bool g4x_dp_init(struct intel_display *display,
-			       i915_reg_t output_reg, int port)
+			       intel_reg_t output_reg, int port)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 5fe5067c4237..9ea90a6d906f 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -666,7 +666,7 @@ static bool assert_hdmi_port_valid(struct intel_display *display, enum port port
 }
 
 bool g4x_hdmi_init(struct intel_display *display,
-		   i915_reg_t hdmi_reg, enum port port)
+		   intel_reg_t hdmi_reg, enum port port)
 {
 	const struct intel_bios_encoder_data *devdata;
 	struct intel_digital_port *dig_port;
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h
index 039d2bdba06c..0557322efe5a 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.h
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum port;
 struct drm_atomic_state;
@@ -17,12 +17,12 @@ struct intel_display;
 
 #ifdef I915
 bool g4x_hdmi_init(struct intel_display *display,
-		   i915_reg_t hdmi_reg, enum port port);
+		   intel_reg_t hdmi_reg, enum port port);
 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 				    struct drm_atomic_state *state);
 #else
 static inline bool g4x_hdmi_init(struct intel_display *display,
-				 i915_reg_t hdmi_reg, int port)
+				 intel_reg_t hdmi_reg, int port)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index afbaa0465842..a549f1fac810 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -296,7 +296,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
-	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+	intel_reg_t dss_ctl1_reg, dss_ctl2_reg;
 	u32 dss_ctl1;
 
 	/* FIXME: Move all DSS handling to intel_vdsc.c */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 2a6476ccc85b..77e54cac56e2 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -595,7 +595,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 }
 
 struct ibx_audio_regs {
-	i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
+	intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 };
 
 static void ibx_audio_regs_init(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 0531c60e5e5d..2d318e922671 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1348,7 +1348,7 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 }
 
 static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
-			  i915_reg_t reg, u32 val)
+			  intel_reg_t reg, u32 val)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
@@ -1359,7 +1359,7 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
 }
 
 static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
-				  i915_reg_t reg, u32 val)
+				  intel_reg_t reg, u32 val)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index f401558ac14e..9b4ecfbbed4f 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -92,7 +92,7 @@ static void icl_set_procmon_ref_values(struct intel_display *display,
 }
 
 static bool check_phy_reg(struct intel_display *display,
-			  enum phy phy, i915_reg_t reg, u32 mask,
+			  enum phy phy, intel_reg_t reg, u32 mask,
 			  u32 expected_val)
 {
 	u32 val = intel_de_read(display, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 6aa6a1dd6e1b..c19e0c591a3c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -77,7 +77,7 @@
 struct intel_crt {
 	struct intel_encoder base;
 	bool force_hotplug_required;
-	i915_reg_t adpa_reg;
+	intel_reg_t adpa_reg;
 };
 
 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
@@ -91,7 +91,7 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
 }
 
 bool intel_crt_port_enabled(struct intel_display *display,
-			    i915_reg_t adpa_reg, enum pipe *pipe)
+			    intel_reg_t adpa_reg, enum pipe *pipe)
 {
 	u32 val;
 
@@ -1011,7 +1011,7 @@ void intel_crt_init(struct intel_display *display)
 {
 	struct intel_connector *connector;
 	struct intel_crt *crt;
-	i915_reg_t adpa_reg;
+	intel_reg_t adpa_reg;
 	u8 ddc_pin;
 	u32 adpa;
 
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
index e0abfe96a3d2..7d0ae8d8c28d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.h
+++ b/drivers/gpu/drm/i915/display/intel_crt.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_CRT_H__
 #define __INTEL_CRT_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum pipe;
 struct drm_encoder;
@@ -14,12 +14,12 @@ struct intel_display;
 
 #ifdef I915
 bool intel_crt_port_enabled(struct intel_display *display,
-			    i915_reg_t adpa_reg, enum pipe *pipe);
+			    intel_reg_t adpa_reg, enum pipe *pipe);
 void intel_crt_init(struct intel_display *display);
 void intel_crt_reset(struct drm_encoder *encoder);
 #else
 static inline bool intel_crt_port_enabled(struct intel_display *display,
-					  i915_reg_t adpa_reg, enum pipe *pipe)
+					  intel_reg_t adpa_reg, enum pipe *pipe)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d832e44ef62a..24a51ab21b55 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2980,7 +2980,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
 	enum phy phy = intel_encoder_to_phy(encoder);
-	i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
+	intel_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
 	int lane;
 
 	intel_de_rmw(display, buf_ctl2_reg,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2681940a5cfe..fc2618ab028d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -188,7 +188,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 		       trans->entries[level].hsw.trans2);
 }
 
-static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
+static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
 {
 	if (DISPLAY_VER(display) >= 14)
 		return XELPDP_PORT_BUF_CTL1(display, port);
@@ -1556,7 +1556,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
 	intel_de_posting_read(display, DDI_BUF_CTL(port));
 }
 
-static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
+static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg,
 				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
 {
 	mutex_lock(&display->dpll.lock);
@@ -1572,7 +1572,7 @@ static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
 	mutex_unlock(&display->dpll.lock);
 }
 
-static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
+static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg,
 				   u32 clk_off)
 {
 	mutex_lock(&display->dpll.lock);
@@ -1582,14 +1582,14 @@ static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg
 	mutex_unlock(&display->dpll.lock);
 }
 
-static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
+static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg,
 				      u32 clk_off)
 {
 	return !(intel_de_read(display, reg) & clk_off);
 }
 
 static struct intel_dpll *
-_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg,
 		 u32 clk_sel_mask, u32 clk_sel_shift)
 {
 	enum intel_dpll_id id;
@@ -2270,8 +2270,8 @@ tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
 		return crtc_state->cpu_transcoder;
 }
 
-i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
-			 const struct intel_crtc_state *crtc_state)
+intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
@@ -2282,8 +2282,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
 		return DP_TP_CTL(encoder->port);
 }
 
-static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
-				   const struct intel_crtc_state *crtc_state)
+static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
@@ -2559,7 +2559,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 set_bits, wait_bits;
 	int ret;
 
@@ -3059,7 +3059,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 clr_bits, wait_bits;
 	int ret;
 
@@ -3386,7 +3386,7 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state,
 	trans_port_sync_stop_link_train(state, encoder, crtc_state);
 }
 
-static i915_reg_t
+static intel_reg_t
 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
 {
 	static const enum transcoder trans[] = {
@@ -3439,7 +3439,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 		 * the bits affect a specific DDI port rather than
 		 * a specific transcoder.
 		 */
-		i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
+		intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
 		u32 val;
 
 		val = intel_de_read(display, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f6f511bb0431..580ecb09b8b6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_DDI_H__
 #define __INTEL_DDI_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 struct drm_connector_state;
 struct intel_atomic_state;
@@ -23,8 +23,8 @@ enum pipe;
 enum port;
 enum transcoder;
 
-i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
-			 const struct intel_crtc_state *crtc_state);
+intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state);
 
 void intel_ddi_clear_act_sent(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c
index a96e83d76eaa..6daee9e82503 100644
--- a/drivers/gpu/drm/i915/display/intel_de.c
+++ b/drivers/gpu/drm/i915/display/intel_de.c
@@ -10,9 +10,9 @@
 #include "intel_de.h"
 
 static int __intel_de_wait_for_register(struct intel_display *display,
-					i915_reg_t reg, u32 mask, u32 value,
+					intel_reg_t reg, u32 mask, u32 value,
 					unsigned int timeout_us,
-					u32 (*read)(struct intel_display *display, i915_reg_t reg),
+					u32 (*read)(struct intel_display *display, intel_reg_t reg),
 					u32 *out_val, bool is_atomic)
 {
 	const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us);
@@ -61,10 +61,10 @@ static int __intel_de_wait_for_register(struct intel_display *display,
 }
 
 static int intel_de_wait_for_register(struct intel_display *display,
-				      i915_reg_t reg, u32 mask, u32 value,
+				      intel_reg_t reg, u32 mask, u32 value,
 				      unsigned int fast_timeout_us,
 				      unsigned int slow_timeout_us,
-				      u32 (*read)(struct intel_display *display, i915_reg_t reg),
+				      u32 (*read)(struct intel_display *display, intel_reg_t reg),
 				      u32 *out_value, bool is_atomic)
 {
 	int ret = -EINVAL;
@@ -82,7 +82,7 @@ static int intel_de_wait_for_register(struct intel_display *display,
 	return ret;
 }
 
-int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
 		     u32 mask, u32 value, unsigned int timeout_us,
 		     u32 *out_value)
 {
@@ -100,7 +100,7 @@ int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
 	return ret;
 }
 
-int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
 		     u32 mask, u32 value, unsigned int timeout_ms,
 		     u32 *out_value)
 {
@@ -118,7 +118,7 @@ int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
 	return ret;
 }
 
-int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
 			u32 mask, u32 value, unsigned int timeout_ms,
 			u32 *out_value)
 {
@@ -128,7 +128,7 @@ int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
 					  out_value, false);
 }
 
-int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, u32 value, unsigned int timeout_us,
 			       u32 *out_value)
 {
@@ -138,31 +138,31 @@ int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
 					  out_value, true);
 }
 
-int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
 			     u32 mask, unsigned int timeout_us)
 {
 	return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
 }
 
-int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, unsigned int timeout_us)
 {
 	return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
 }
 
-int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
 			     u32 mask, unsigned int timeout_ms)
 {
 	return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
 }
 
-int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, unsigned int timeout_ms)
 {
 	return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
 }
 
-u8 intel_de_read8(struct intel_display *display, i915_reg_t reg)
+u8 intel_de_read8(struct intel_display *display, intel_reg_t reg)
 {
 	/* this is only used on VGA registers (possible on pre-g4x) */
 	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
@@ -170,14 +170,14 @@ u8 intel_de_read8(struct intel_display *display, i915_reg_t reg)
 	return intel_uncore_read8(__to_uncore(display), reg);
 }
 
-void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
+void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val)
 {
 	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
 
 	intel_uncore_write8(__to_uncore(display), reg, val);
 }
 
-u16 intel_de_read16(struct intel_display *display, i915_reg_t reg)
+u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
 {
 	/* this is only used on MCHBAR registers on pre-SNB */
 	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6);
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index 14f9dc7b6dfd..d17f14843f98 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -17,12 +17,12 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display)
 	return to_intel_uncore(display->drm);
 }
 
-u8 intel_de_read8(struct intel_display *display, i915_reg_t reg);
-void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val);
-u16 intel_de_read16(struct intel_display *display, i915_reg_t reg);
+u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
+void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
+u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
 
 static inline u32
-intel_de_read(struct intel_display *display, i915_reg_t reg)
+intel_de_read(struct intel_display *display, intel_reg_t reg)
 {
 	u32 val;
 
@@ -37,7 +37,7 @@ intel_de_read(struct intel_display *display, i915_reg_t reg)
 
 static inline u64
 intel_de_read64_2x32_volatile(struct intel_display *display,
-			      i915_reg_t lower_reg, i915_reg_t upper_reg)
+			      intel_reg_t lower_reg, intel_reg_t upper_reg)
 {
 	u64 val;
 
@@ -54,9 +54,9 @@ intel_de_read64_2x32_volatile(struct intel_display *display,
 }
 
 static inline u64
-intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg)
+intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg)
 {
-	i915_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4);
+	intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4);
 	u32 lower, upper;
 
 	lower = intel_de_read(display, reg);
@@ -66,7 +66,7 @@ intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg)
 }
 
 static inline void
-intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
+intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
 {
 	intel_dmc_wl_get(display, reg);
 
@@ -76,7 +76,7 @@ intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
 }
 
 static inline void
-intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
 {
 	intel_dmc_wl_get(display, reg);
 
@@ -86,7 +86,7 @@ intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
 }
 
 static inline u32
-intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
+intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
 {
 	u32 val;
 
@@ -99,25 +99,25 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
 	return val;
 }
 
-int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
 		     u32 mask, u32 value, unsigned int timeout_us,
 		     u32 *out_value);
-int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
 		     u32 mask, u32 value, unsigned int timeout_ms,
 		     u32 *out_value);
-int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
 			u32 mask, u32 value, unsigned int timeout_ms,
 			u32 *out_value);
-int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, u32 value, unsigned int timeout_us,
 			       u32 *out_value);
-int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
 			     u32 mask, unsigned int timeout_us);
-int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, unsigned int timeout_us);
-int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
 			     u32 mask, unsigned int timeout_ms);
-int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
 			       u32 mask, unsigned int timeout_ms);
 
 /*
@@ -129,7 +129,7 @@ int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
  * a more localised lock guarding all access to that bank of registers.
  */
 static inline u32
-intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
+intel_de_read_fw(struct intel_display *display, intel_reg_t reg)
 {
 	u32 val;
 
@@ -140,14 +140,14 @@ intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
 }
 
 static inline void
-intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val)
 {
 	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
 	intel_uncore_write_fw(__to_uncore(display), reg, val);
 }
 
 static inline u32
-intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
+intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
 {
 	u32 old, val;
 
@@ -159,20 +159,20 @@ intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 se
 }
 
 static inline u32
-intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
+intel_de_read_notrace(struct intel_display *display, intel_reg_t reg)
 {
 	return intel_uncore_read_notrace(__to_uncore(display), reg);
 }
 
 static inline void
-intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val)
 {
 	intel_uncore_write_notrace(__to_uncore(display), reg, val);
 }
 
 static __always_inline void
 intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
-		   i915_reg_t reg, u32 val)
+		   intel_reg_t reg, u32 val)
 {
 	if (dsb)
 		intel_dsb_reg_write(dsb, reg, val);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2fa10f858279..30e68e3b9b11 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2579,8 +2579,8 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
 
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
-		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(display, data_n_reg, m_n->data_n);
@@ -3342,8 +3342,8 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
 
 void intel_get_m_n(struct intel_display *display,
 		   struct intel_link_m_n *m_n,
-		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+		   intel_reg_t link_m_reg, intel_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1e76a455d7c4..43b2d6de833c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,7 +27,7 @@
 
 #include <drm/drm_util.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 #include "intel_display_limits.h"
 
 struct drm_atomic_state;
@@ -426,12 +426,12 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);
 void intel_zero_m_n(struct intel_link_m_n *m_n);
 void intel_set_m_n(struct intel_display *display,
 		   const struct intel_link_m_n *m_n,
-		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
+		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+		   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
 void intel_get_m_n(struct intel_display *display,
 		   struct intel_link_m_n *m_n,
-		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
+		   intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+		   intel_reg_t link_m_reg, intel_reg_t link_n_reg);
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
 				    enum transcoder transcoder);
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b5bfdebc66ca..9bd72a99db2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -47,7 +47,7 @@ static void irq_reset(struct intel_display *display, struct i915_irq_regs regs)
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg)
+static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg)
 {
 	u32 val = intel_de_read(display, reg);
 
@@ -343,7 +343,7 @@ u32 i915_pipestat_enable_mask(struct intel_display *display,
 void i915_enable_pipestat(struct intel_display *display,
 			  enum pipe pipe, u32 status_mask)
 {
-	i915_reg_t reg = PIPESTAT(display, pipe);
+	intel_reg_t reg = PIPESTAT(display, pipe);
 	u32 enable_mask;
 
 	drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -366,7 +366,7 @@ void i915_enable_pipestat(struct intel_display *display,
 void i915_disable_pipestat(struct intel_display *display,
 			   enum pipe pipe, u32 status_mask)
 {
-	i915_reg_t reg = PIPESTAT(display, pipe);
+	intel_reg_t reg = PIPESTAT(display, pipe);
 	u32 enable_mask;
 
 	drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -543,7 +543,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display,
 	}
 
 	for_each_pipe(display, pipe) {
-		i915_reg_t reg;
+		intel_reg_t reg;
 		u32 status_mask, enable_mask, iir_bit = 0;
 
 		/*
@@ -1284,7 +1284,7 @@ gen8_de_misc_irq_handler(struct intel_display *display, u32 iir)
 	if (iir & GEN8_DE_EDP_PSR) {
 		struct intel_encoder *encoder;
 		u32 psr_iir;
-		i915_reg_t iir_reg;
+		intel_reg_t iir_reg;
 
 		for_each_intel_encoder_with_psr(display->drm, encoder) {
 			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..751e6b7d4a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1069,7 +1069,7 @@ static void intel_power_domains_sync_hw(struct intel_display *display)
 static void gen9_dbuf_slice_set(struct intel_display *display,
 				enum dbuf_slice slice, bool enable)
 {
-	i915_reg_t reg = DBUF_CTL_S(slice);
+	intel_reg_t reg = DBUF_CTL_S(slice);
 	bool state;
 
 	intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
@@ -1426,7 +1426,7 @@ static void hsw_disable_pc8(struct intel_display *display)
 static void intel_pch_reset_handshake(struct intel_display *display,
 				      bool enable)
 {
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 reset_bits;
 
 	if (DISPLAY_VER(display) >= 35)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6fbfd46461b0..04bd0dde5bed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -49,10 +49,10 @@ static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_id
 }
 
 struct i915_power_well_regs {
-	i915_reg_t bios;
-	i915_reg_t driver;
-	i915_reg_t kvmr;
-	i915_reg_t debug;
+	intel_reg_t bios;
+	intel_reg_t driver;
+	intel_reg_t kvmr;
+	intel_reg_t debug;
 };
 
 struct i915_power_well_ops {
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 175334b41bba..cb46863693cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -8,6 +8,8 @@
 
 #include "i915_reg_defs.h"
 
+typedef i915_reg_t intel_reg_t;
+
 #define VLV_DISPLAY_BASE		0x180000
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c81916761850..7fcee3ee319c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1662,7 +1662,7 @@ struct intel_plane {
 	container_of_const((fb), struct intel_framebuffer, base)
 
 struct intel_hdmi {
-	i915_reg_t hdmi_reg;
+	intel_reg_t hdmi_reg;
 	struct {
 		enum drm_dp_dual_mode_type type;
 		int max_tmds_clock;
@@ -1792,7 +1792,7 @@ struct intel_psr {
 };
 
 struct intel_dp {
-	i915_reg_t output_reg;
+	intel_reg_t output_reg;
 	u32 DP;
 	int link_rate;
 	u8 lane_count;
@@ -1889,8 +1889,8 @@ struct intel_dp {
 	u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
 				u32 aux_clock_divider);
 
-	i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
-	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
+	intel_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
+	intel_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
 
 	/* This is called before a link training is starterd */
 	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 0df4f42ba3e3..6a39ad19b339 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -71,7 +71,7 @@ struct intel_dmc {
 	} dc6_allowed;
 	struct dmc_fw_info {
 		u32 mmio_count;
-		i915_reg_t mmioaddr[20];
+		intel_reg_t mmioaddr[20];
 		u32 mmiodata[20];
 		u32 dmc_offset;
 		u32 start_mmioaddr;
@@ -434,7 +434,7 @@ static void gen9_set_dc_state_debugmask(struct intel_display *display)
 }
 
 static void disable_event_handler(struct intel_display *display,
-				  i915_reg_t ctl_reg, i915_reg_t htp_reg)
+				  intel_reg_t ctl_reg, intel_reg_t htp_reg)
 {
 	intel_de_write(display, ctl_reg,
 		       REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
@@ -538,7 +538,7 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl)
 }
 
 static bool is_dmc_evt_ctl_reg(struct intel_display *display,
-			       enum intel_dmc_id dmc_id, i915_reg_t reg)
+			       enum intel_dmc_id dmc_id, intel_reg_t reg)
 {
 	u32 offset = i915_mmio_reg_offset(reg);
 	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
@@ -548,7 +548,7 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display,
 }
 
 static bool is_dmc_evt_htp_reg(struct intel_display *display,
-			       enum intel_dmc_id dmc_id, i915_reg_t reg)
+			       enum intel_dmc_id dmc_id, intel_reg_t reg)
 {
 	u32 offset = i915_mmio_reg_offset(reg);
 	u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
@@ -560,7 +560,7 @@ static bool is_dmc_evt_htp_reg(struct intel_display *display,
 static bool is_event_handler(struct intel_display *display,
 			     enum intel_dmc_id dmc_id,
 			     unsigned int event_id,
-			     i915_reg_t reg, u32 data)
+			     intel_reg_t reg, u32 data)
 {
 	return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&
 		REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;
@@ -568,8 +568,8 @@ static bool is_event_handler(struct intel_display *display,
 
 static bool fixup_dmc_evt(struct intel_display *display,
 			  enum intel_dmc_id dmc_id,
-			  i915_reg_t reg_ctl, u32 *data_ctl,
-			  i915_reg_t reg_htp, u32 *data_htp)
+			  intel_reg_t reg_ctl, u32 *data_ctl,
+			  intel_reg_t reg_htp, u32 *data_htp)
 {
 	if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))
 		return false;
@@ -613,7 +613,7 @@ static bool fixup_dmc_evt(struct intel_display *display,
 
 static bool disable_dmc_evt(struct intel_display *display,
 			    enum intel_dmc_id dmc_id,
-			    i915_reg_t reg, u32 data)
+			    intel_reg_t reg, u32 data)
 {
 	if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
 		return false;
@@ -696,7 +696,7 @@ static void assert_dmc_loaded(struct intel_display *display,
 		 dmc_id, expected, found);
 
 	for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
-		i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
+		intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
 
 		found = intel_de_read(display, reg);
 		expected = dmc_mmiodata(display, dmc, dmc_id, i);
@@ -847,7 +847,7 @@ static void dmc_configure_event(struct intel_display *display,
 	int i;
 
 	for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
-		i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
+		intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
 		u32 data = dmc->dmc_info[dmc_id].mmiodata[i];
 
 		if (!is_event_handler(display, dmc_id, event_id, reg, data))
@@ -1618,7 +1618,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_display *display = m->private;
 	struct intel_dmc *dmc = display_to_dmc(display);
 	struct ref_tracker *wakeref;
-	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
 	u32 dc6_allowed_count;
 
 	if (!HAS_DMC(display))
@@ -1647,7 +1647,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 		   DMC_VERSION_MINOR(dmc->version));
 
 	if (DISPLAY_VER(display) >= 12) {
-		i915_reg_t dc3co_reg;
+		intel_reg_t dc3co_reg;
 
 		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
 			dc3co_reg = DG1_DMC_DEBUG3;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index ddf1a1f1ebc3..82afb60fa973 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -224,7 +224,7 @@ static void __intel_dmc_wl_take(struct intel_display *display)
 	wl->taken = true;
 }
 
-static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
+static bool intel_dmc_wl_reg_in_range(intel_reg_t reg,
 				      const struct intel_dmc_wl_range ranges[])
 {
 	u32 offset = i915_mmio_reg_offset(reg);
@@ -240,7 +240,7 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
 }
 
 static bool intel_dmc_wl_check_range(struct intel_display *display,
-				     i915_reg_t reg,
+				     intel_reg_t reg,
 				     u32 dc_state)
 {
 	const struct intel_dmc_wl_range *ranges;
@@ -431,7 +431,7 @@ void intel_dmc_wl_flush_release_work(struct intel_display *display)
 	flush_delayed_work(&wl->work);
 }
 
-void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
+void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg)
 {
 	struct intel_dmc_wl *wl = &display->wl;
 	unsigned long flags;
@@ -464,7 +464,7 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
 	spin_unlock_irqrestore(&wl->lock, flags);
 }
 
-void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)
+void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg)
 {
 	struct intel_dmc_wl *wl = &display->wl;
 	unsigned long flags;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
index 5488fbdf29b8..215107f0a4f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
@@ -10,7 +10,7 @@
 #include <linux/workqueue.h>
 #include <linux/refcount.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 struct intel_display;
 
@@ -33,8 +33,8 @@ void intel_dmc_wl_init(struct intel_display *display);
 void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
 void intel_dmc_wl_disable(struct intel_display *display);
 void intel_dmc_wl_flush_release_work(struct intel_display *display);
-void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
-void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
+void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg);
+void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg);
 void intel_dmc_wl_get_noreg(struct intel_display *display);
 void intel_dmc_wl_put_noreg(struct intel_display *display);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 98df93884e9a..fe2150543ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5318,7 +5318,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
+	intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
 	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
 			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b20ec3e589fa..ef33ecd81f28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -58,7 +58,7 @@ static u32
 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+	intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 	const unsigned int timeout_ms = 10;
 	u32 status;
 	bool done;
@@ -244,7 +244,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
-	i915_reg_t ch_ctl, ch_data[5];
+	intel_reg_t ch_ctl, ch_data[5];
 	u32 aux_clock_divider;
 	enum intel_display_power_domain aux_domain;
 	struct ref_tracker *aux_wakeref;
@@ -554,7 +554,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 	return ret;
 }
 
-static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -570,7 +570,7 @@ static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -586,7 +586,7 @@ static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
-static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -602,7 +602,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -618,7 +618,7 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
-static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -636,7 +636,7 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -654,7 +654,7 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
-static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -673,7 +673,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -692,7 +692,7 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
-static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -714,7 +714,7 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum aux_ch aux_ch = dig_port->aux_ch;
@@ -736,7 +736,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	}
 }
 
-static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -756,7 +756,7 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
 	}
 }
 
-static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 68802b652316..8055f6ccc5c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -279,8 +279,8 @@ void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
  * writes to the group register to write the same value to all the lanes.
  */
 static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
-				i915_reg_t reg_single,
-				i915_reg_t reg_group,
+				intel_reg_t reg_single,
+				intel_reg_t reg_group,
 				u32 clear, u32 set)
 {
 	u32 old, val;
@@ -512,7 +512,7 @@ void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
 
 static bool __printf(6, 7)
 __phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
-		       i915_reg_t reg, u32 mask, u32 expected,
+		       intel_reg_t reg, u32 mask, u32 expected,
 		       const char *reg_fmt, ...)
 {
 	struct va_format vaf;
@@ -1172,7 +1172,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	u32 port_mask;
-	i915_reg_t dpll_reg;
+	intel_reg_t dpll_reg;
 	u32 val;
 
 	switch (encoder->port) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e97b38f5d98e..6acdfa97deaa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -220,7 +220,7 @@ enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port p
 	}
 }
 
-static i915_reg_t
+static intel_reg_t
 intel_combo_pll_enable_reg(struct intel_display *display,
 			   struct intel_dpll *pll)
 {
@@ -233,7 +233,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
 	return ICL_DPLL_ENABLE(pll->info->id);
 }
 
-static i915_reg_t
+static intel_reg_t
 intel_tc_pll_enable_reg(struct intel_display *display,
 			struct intel_dpll *pll)
 {
@@ -1350,7 +1350,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
 };
 
 struct skl_dpll_regs {
-	i915_reg_t ctl, cfgcr1, cfgcr2;
+	intel_reg_t ctl, cfgcr1, cfgcr2;
 };
 
 /* this array is indexed by the *shared* pll id */
@@ -3603,7 +3603,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
 	bool ret = false;
 	u32 val;
 
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
 	wakeref = intel_display_power_get_if_enabled(display,
 						     POWER_DOMAIN_DISPLAY_CORE);
@@ -3734,7 +3734,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
 static bool icl_pll_get_hw_state(struct intel_display *display,
 				 struct intel_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state,
-				 i915_reg_t enable_reg)
+				 intel_reg_t enable_reg)
 {
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
@@ -3796,7 +3796,7 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
 				   struct intel_dpll *pll,
 				   struct intel_dpll_hw_state *dpll_hw_state)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
@@ -3813,7 +3813,7 @@ static void icl_dpll_write(struct intel_display *display,
 			   const struct icl_dpll_hw_state *hw_state)
 {
 	const enum intel_dpll_id id = pll->info->id;
-	i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
+	intel_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
 
 	if (display->platform.alderlake_s) {
 		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
@@ -3960,7 +3960,7 @@ static void dkl_pll_write(struct intel_display *display,
 
 static void icl_pll_power_enable(struct intel_display *display,
 				 struct intel_dpll *pll,
-				 i915_reg_t enable_reg)
+				 intel_reg_t enable_reg)
 {
 	intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
 
@@ -3975,7 +3975,7 @@ static void icl_pll_power_enable(struct intel_display *display,
 
 static void icl_pll_enable(struct intel_display *display,
 			   struct intel_dpll *pll,
-			   i915_reg_t enable_reg)
+			   intel_reg_t enable_reg)
 {
 	intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
 
@@ -4013,7 +4013,7 @@ static void combo_pll_enable(struct intel_display *display,
 			     const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
 	icl_pll_power_enable(display, pll, enable_reg);
 
@@ -4058,7 +4058,7 @@ static void mg_pll_enable(struct intel_display *display,
 			  const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
 	icl_pll_power_enable(display, pll, enable_reg);
 
@@ -4080,7 +4080,7 @@ static void mg_pll_enable(struct intel_display *display,
 
 static void icl_pll_disable(struct intel_display *display,
 			    struct intel_dpll *pll,
-			    i915_reg_t enable_reg)
+			    intel_reg_t enable_reg)
 {
 	/* The first steps are done by intel_ddi_post_disable(). */
 
@@ -4112,7 +4112,7 @@ static void icl_pll_disable(struct intel_display *display,
 static void combo_pll_disable(struct intel_display *display,
 			      struct intel_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
 	icl_pll_disable(display, pll, enable_reg);
 }
@@ -4126,7 +4126,7 @@ static void icl_tbt_pll_disable(struct intel_display *display,
 static void mg_pll_disable(struct intel_display *display,
 			   struct intel_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+	intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
 	icl_pll_disable(display, pll, enable_reg);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index c8d3968f659f..ce4d452ae695 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -326,7 +326,7 @@ static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
 }
 
 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
-					u32 opcode, i915_reg_t reg)
+					u32 opcode, intel_reg_t reg)
 {
 	u32 prev_opcode, prev_reg;
 
@@ -344,7 +344,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
 	return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
 }
 
-static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
+static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg)
 {
 	return intel_dsb_prev_ins_is_write(dsb,
 					   DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT,
@@ -365,7 +365,7 @@ static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_
  * register.
  */
 void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
-				 i915_reg_t reg, u32 val)
+				 intel_reg_t reg, u32 val)
 {
 	/*
 	 * For example the buffer will look like below for 3 dwords for auto
@@ -402,7 +402,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
 }
 
 void intel_dsb_reg_write(struct intel_dsb *dsb,
-			 i915_reg_t reg, u32 val)
+			 intel_reg_t reg, u32 val)
 {
 	intel_dsb_emit(dsb, val,
 		       (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
@@ -420,7 +420,7 @@ static u32 intel_dsb_mask_to_byte_en(u32 mask)
 
 /* Note: mask implemented via byte enables! */
 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
-				i915_reg_t reg, u32 mask, u32 val)
+				intel_reg_t reg, u32 mask, u32 val)
 {
 	intel_dsb_emit(dsb, val,
 		       (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
@@ -550,7 +550,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
 }
 
 void intel_dsb_poll(struct intel_dsb *dsb,
-		    i915_reg_t reg, u32 mask, u32 val,
+		    intel_reg_t reg, u32 mask, u32 val,
 		    int wait_us, int count)
 {
 	struct intel_crtc *crtc = dsb->crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 386a5a942572..3dcca9ed5371 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 struct intel_atomic_state;
 struct intel_crtc;
@@ -37,11 +37,11 @@ void intel_dsb_gosub_finish(struct intel_dsb *dsb);
 void intel_dsb_cleanup(struct intel_dsb *dsb);
 int intel_dsb_exec_time_us(void);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
-			 i915_reg_t reg, u32 val);
+			 intel_reg_t reg, u32 val);
 void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
-				 i915_reg_t reg, u32 val);
+				 intel_reg_t reg, u32 val);
 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
-				i915_reg_t reg, u32 mask, u32 val);
+				intel_reg_t reg, u32 mask, u32 val);
 void intel_dsb_noop(struct intel_dsb *dsb, int count);
 void intel_dsb_nonpost_start(struct intel_dsb *dsb);
 void intel_dsb_nonpost_end(struct intel_dsb *dsb);
@@ -59,7 +59,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
 void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 			    struct intel_dsb *dsb);
 void intel_dsb_poll(struct intel_dsb *dsb,
-		    i915_reg_t reg, u32 mask, u32 val,
+		    intel_reg_t reg, u32 mask, u32 val,
 		    int wait_us, int count);
 void intel_dsb_gosub(struct intel_dsb *dsb,
 		     struct intel_dsb *sub_dsb);
diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
index f1e939aaf7fa..1f049f79a534 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
+++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
@@ -23,7 +23,7 @@
 #ifndef __INTEL_DVO_DEV_H__
 #define __INTEL_DVO_DEV_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #include "intel_display_limits.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index f5094655a63b..c41881a2be15 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -439,7 +439,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp;
 
 	/* enable normal train */
@@ -480,7 +480,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp, tries;
 
 	/*
@@ -581,7 +581,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp, i, retry;
 
 	/*
@@ -716,7 +716,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp, i, j;
 
 	ivb_update_fdi_bc_bifurcation(crtc_state);
@@ -997,7 +997,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp;
 
 	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
@@ -1050,7 +1050,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 temp;
 
 	/* disable CPU FDI tx and PCH FDI rx */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index bf047180def9..02013e89d8f2 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -189,7 +189,7 @@ static bool cpt_can_enable_serr_int(struct intel_display *display)
 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
-	i915_reg_t reg = PIPESTAT(display, crtc->pipe);
+	intel_reg_t reg = PIPESTAT(display, crtc->pipe);
 	u32 enable_mask;
 
 	lockdep_assert_held(&display->irq.lock);
@@ -209,7 +209,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
 					     enum pipe pipe,
 					     bool enable, bool old)
 {
-	i915_reg_t reg = PIPESTAT(display, pipe);
+	intel_reg_t reg = PIPESTAT(display, pipe);
 
 	lockdep_assert_held(&display->irq.lock);
 
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index ea5cf8f51b31..049157c41fe2 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -48,7 +48,7 @@ struct intel_gmbus {
 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 	u32 force_bit;
 	u32 reg0;
-	i915_reg_t gpio_reg;
+	intel_reg_t gpio_reg;
 	struct i2c_algo_bit_data bit_algo;
 	struct intel_display *display;
 };
@@ -368,7 +368,7 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter)
 }
 
 static void
-intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
+intel_gpio_setup(struct intel_gmbus *bus, intel_reg_t gpio_reg)
 {
 	struct i2c_algo_bit_data *algo;
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 982f698e9814..823b5a14182e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -46,7 +46,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder,
 				     bool enable)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	i915_reg_t rekey_reg;
+	intel_reg_t rekey_reg;
 	u32 rekey_bit = 0;
 
 	/* Here we assume HDMI is in TMDS mode of operation */
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 874076a29da4..a8eab7af3706 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -173,7 +173,7 @@ static u32 hsw_infoframe_enable(unsigned int type)
 	}
 }
 
-static i915_reg_t
+static intel_reg_t
 hsw_dip_data_reg(struct intel_display *display,
 		 enum transcoder cpu_transcoder,
 		 unsigned int type,
@@ -298,7 +298,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	const u32 *data = frame;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 	int i;
 
@@ -351,7 +351,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
-	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
+	intel_reg_t reg = TVIDEO_DIP_CTL(pipe);
 	u32 val = intel_de_read(display, reg);
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -373,7 +373,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	const u32 *data = frame;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 	int i;
 
@@ -447,7 +447,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	const u32 *data = frame;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 	int i;
 
@@ -523,7 +523,7 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	const u32 *data = frame;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
+	intel_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
 	int data_size;
 	int i;
 	u32 val = intel_de_read(display, ctl_reg);
@@ -884,7 +884,7 @@ static void g4x_set_infoframes(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
-	i915_reg_t reg = VIDEO_DIP_CTL;
+	intel_reg_t reg = VIDEO_DIP_CTL;
 	u32 val = intel_de_read(display, reg);
 	u32 port = VIDEO_DIP_PORT(encoder->port);
 
@@ -995,7 +995,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	i915_reg_t reg;
+	intel_reg_t reg;
 
 	if ((crtc_state->infoframes.enable &
 	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
@@ -1020,7 +1020,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	i915_reg_t reg;
+	intel_reg_t reg;
 
 	if ((crtc_state->infoframes.enable &
 	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
@@ -1069,7 +1069,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
-	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 	u32 port = VIDEO_DIP_PORT(encoder->port);
 
@@ -1127,7 +1127,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 
 	assert_hdmi_port_disabled(intel_hdmi);
@@ -1176,7 +1176,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
+	intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 	u32 val = intel_de_read(display, reg);
 	u32 port = VIDEO_DIP_PORT(encoder->port);
 
@@ -1231,7 +1231,7 @@ void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
 				   const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
+	intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
 					    crtc_state->cpu_transcoder);
 	u32 val = intel_de_read(display, reg);
 
@@ -1256,7 +1256,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
 			       const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
+	intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
 					    crtc_state->cpu_transcoder);
 	u32 val = intel_de_read(display, reg);
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index e2f9e1a2745f..615ee980470e 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1007,7 +1007,7 @@ assert_dc_off(struct intel_display *display)
 
 static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
 					 int lane, u16 addr, u8 data,
-					 i915_reg_t mac_reg_addr,
+					 intel_reg_t mac_reg_addr,
 					 u8 expected_mac_val)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -1062,7 +1062,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
 
 static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
 				     int lane, u16 addr, u8 data,
-				     i915_reg_t mac_reg_addr,
+				     intel_reg_t mac_reg_addr,
 				     u8 expected_mac_val)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -1086,7 +1086,7 @@ static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
 
 static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
 				   u8 lane_mask, u16 addr, u8 data,
-				   i915_reg_t mac_reg_addr,
+				   intel_reg_t mac_reg_addr,
 				   u8 expected_mac_val)
 {
 	int lane;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index cc6d4bfcff10..a60661d5c7ed 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -70,7 +70,7 @@ struct intel_lvds_encoder {
 	struct intel_encoder base;
 
 	bool is_dual_link;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 a3_power;
 
 	struct intel_lvds_pps init_pps;
@@ -85,7 +85,7 @@ static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
 }
 
 bool intel_lvds_port_enabled(struct intel_display *display,
-			     i915_reg_t lvds_reg, enum pipe *pipe)
+			     intel_reg_t lvds_reg, enum pipe *pipe)
 {
 	u32 val;
 
@@ -846,7 +846,7 @@ void intel_lvds_init(struct intel_display *display)
 	struct intel_connector *connector;
 	const struct drm_edid *drm_edid;
 	struct intel_encoder *encoder;
-	i915_reg_t lvds_reg;
+	intel_reg_t lvds_reg;
 	u32 lvds;
 	u8 ddc_pin;
 
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h
index a6db1706a97c..6ac70d5e8ce6 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.h
+++ b/drivers/gpu/drm/i915/display/intel_lvds.h
@@ -8,20 +8,20 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum pipe;
 struct intel_display;
 
 #ifdef I915
 bool intel_lvds_port_enabled(struct intel_display *display,
-			     i915_reg_t lvds_reg, enum pipe *pipe);
+			     intel_reg_t lvds_reg, enum pipe *pipe);
 void intel_lvds_init(struct intel_display *display);
 struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display);
 bool intel_is_dual_link_lvds(struct intel_display *display);
 #else
 static inline bool intel_lvds_port_enabled(struct intel_display *display,
-					   i915_reg_t lvds_reg, enum pipe *pipe)
+					   intel_reg_t lvds_reg, enum pipe *pipe)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c
index a0d0a796c6bb..8cfcee4a08a4 100644
--- a/drivers/gpu/drm/i915/display/intel_mchbar.c
+++ b/drivers/gpu/drm/i915/display/intel_mchbar.c
@@ -41,7 +41,7 @@ static u32 mchbar_mirror_len(struct intel_display *display)
 	return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1;
 }
 
-static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg)
+static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
 {
 	return has_mchbar_mirror(display) &&
 		in_range32(i915_mmio_reg_offset(reg),
@@ -49,28 +49,28 @@ static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg)
 			   mchbar_mirror_len(display));
 }
 
-static void assert_is_mchbar_reg(struct intel_display *display, i915_reg_t reg)
+static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
 {
 	drm_WARN(display->drm, !is_mchbar_reg(display, reg),
 		 "Reading non-MCHBAR register 0x%x\n",
 		 i915_mmio_reg_offset(reg));
 }
 
-u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg)
+u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg)
 {
 	assert_is_mchbar_reg(display, reg);
 
 	return intel_de_read16(display, reg);
 }
 
-u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg)
+u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg)
 {
 	assert_is_mchbar_reg(display, reg);
 
 	return intel_de_read(display, reg);
 }
 
-u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg)
+u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg)
 {
 	assert_is_mchbar_reg(display, reg);
 
diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.h b/drivers/gpu/drm/i915/display/intel_mchbar.h
index fb645c64796c..1ced5dc8a8fd 100644
--- a/drivers/gpu/drm/i915/display/intel_mchbar.h
+++ b/drivers/gpu/drm/i915/display/intel_mchbar.h
@@ -10,12 +10,12 @@
 
 #include <drm/intel/mchbar_regs.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 struct intel_display;
 
-u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg);
-u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg);
-u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg);
+u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg);
+u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg);
+u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg);
 
 #endif /* __INTEL_MCHBAR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 69c7952a1413..2fcf6c9c84cc 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -40,7 +40,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
 
 static void assert_pch_dp_disabled(struct intel_display *display,
 				   enum pipe pipe, enum port port,
-				   i915_reg_t dp_reg)
+				   intel_reg_t dp_reg)
 {
 	enum pipe port_pipe;
 	bool state;
@@ -59,7 +59,7 @@ static void assert_pch_dp_disabled(struct intel_display *display,
 
 static void assert_pch_hdmi_disabled(struct intel_display *display,
 				     enum pipe pipe, enum port port,
-				     i915_reg_t hdmi_reg)
+				     intel_reg_t hdmi_reg)
 {
 	enum pipe port_pipe;
 	bool state;
@@ -115,7 +115,7 @@ static void assert_pch_transcoder_disabled(struct intel_display *display,
 }
 
 static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,
-				       enum port port, i915_reg_t hdmi_reg)
+				       enum port port, intel_reg_t hdmi_reg)
 {
 	u32 val = intel_de_read(display, hdmi_reg);
 
@@ -134,7 +134,7 @@ static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,
 }
 
 static void ibx_sanitize_pch_dp_port(struct intel_display *display,
-				     enum port port, i915_reg_t dp_reg)
+				     enum port port, intel_reg_t dp_reg)
 {
 	u32 val = intel_de_read(display, dp_reg);
 
@@ -247,7 +247,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 val, pipeconf_val;
 
 	/* Make sure PCH DPLL is enabled */
@@ -313,7 +313,7 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg;
+	intel_reg_t reg;
 
 	/* FDI relies on the transcoder */
 	assert_fdi_tx_disabled(display, pipe);
@@ -417,7 +417,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 			&crtc_state->hw.adjusted_mode;
 		u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
 			   & TRANSCONF_BPC_MASK) >> 5;
-		i915_reg_t reg = TRANS_DP_CTL(pipe);
+		intel_reg_t reg = TRANS_DP_CTL(pipe);
 		enum port port;
 
 		temp = intel_de_read(display, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 2d799af73bb7..ea5e8f75acef 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -488,11 +488,11 @@ void bxt_pps_reset_all(struct intel_display *display)
 }
 
 struct pps_registers {
-	i915_reg_t pp_ctrl;
-	i915_reg_t pp_stat;
-	i915_reg_t pp_on;
-	i915_reg_t pp_off;
-	i915_reg_t pp_div;
+	intel_reg_t pp_ctrl;
+	intel_reg_t pp_stat;
+	intel_reg_t pp_on;
+	intel_reg_t pp_off;
+	intel_reg_t pp_div;
 };
 
 static void intel_pps_get_registers(struct intel_dp *intel_dp,
@@ -523,7 +523,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 		regs->pp_div = PP_DIVISOR(display, pps_idx);
 }
 
-static i915_reg_t
+static intel_reg_t
 _pp_ctrl_reg(struct intel_dp *intel_dp)
 {
 	struct pps_registers regs;
@@ -533,7 +533,7 @@ _pp_ctrl_reg(struct intel_dp *intel_dp)
 	return regs.pp_ctrl;
 }
 
-static i915_reg_t
+static intel_reg_t
 _pp_stat_reg(struct intel_dp *intel_dp)
 {
 	struct pps_registers regs;
@@ -607,7 +607,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	i915_reg_t pp_stat_reg, pp_ctrl_reg;
+	intel_reg_t pp_stat_reg, pp_ctrl_reg;
 	int ret;
 	u32 val;
 
@@ -744,7 +744,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	u32 pp;
-	i915_reg_t pp_stat_reg, pp_ctrl_reg;
+	intel_reg_t pp_stat_reg, pp_ctrl_reg;
 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
 
 	if (!intel_dp_is_edp(intel_dp))
@@ -826,7 +826,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	u32 pp;
-	i915_reg_t pp_stat_reg, pp_ctrl_reg;
+	intel_reg_t pp_stat_reg, pp_ctrl_reg;
 
 	lockdep_assert_held(&display->pps.mutex);
 
@@ -955,7 +955,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	u32 pp;
-	i915_reg_t pp_ctrl_reg;
+	intel_reg_t pp_ctrl_reg;
 
 	lockdep_assert_held(&display->pps.mutex);
 
@@ -1028,7 +1028,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	u32 pp;
-	i915_reg_t pp_ctrl_reg;
+	intel_reg_t pp_ctrl_reg;
 
 	lockdep_assert_held(&display->pps.mutex);
 
@@ -1091,7 +1091,7 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp)
 	wait_backlight_on(intel_dp);
 
 	with_intel_pps_lock(intel_dp) {
-		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+		intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 		u32 pp;
 
 		pp = ilk_get_pp_control(intel_dp);
@@ -1111,7 +1111,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
 		return;
 
 	with_intel_pps_lock(intel_dp) {
-		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+		intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 		u32 pp;
 
 		pp = ilk_get_pp_control(intel_dp);
@@ -1155,7 +1155,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
-	i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
+	intel_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
 
 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
 
@@ -1814,7 +1814,7 @@ void intel_pps_connector_debugfs_add(struct intel_connector *connector)
 
 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
 {
-	i915_reg_t pp_reg;
+	intel_reg_t pp_reg;
 	u32 val;
 	enum pipe panel_pipe = INVALID_PIPE;
 	bool locked = true;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d1bae7d32617..248832f812cf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -303,8 +303,8 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
 		EDP_PSR_MASK(intel_dp->psr.transcoder);
 }
 
-static i915_reg_t psr_ctl_reg(struct intel_display *display,
-			      enum transcoder cpu_transcoder)
+static intel_reg_t psr_ctl_reg(struct intel_display *display,
+			       enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_CTL(display, cpu_transcoder);
@@ -312,8 +312,8 @@ static i915_reg_t psr_ctl_reg(struct intel_display *display,
 		return HSW_SRD_CTL;
 }
 
-static i915_reg_t psr_debug_reg(struct intel_display *display,
-				enum transcoder cpu_transcoder)
+static intel_reg_t psr_debug_reg(struct intel_display *display,
+				 enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_DEBUG(display, cpu_transcoder);
@@ -321,8 +321,8 @@ static i915_reg_t psr_debug_reg(struct intel_display *display,
 		return HSW_SRD_DEBUG;
 }
 
-static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,
-				   enum transcoder cpu_transcoder)
+static intel_reg_t psr_perf_cnt_reg(struct intel_display *display,
+				    enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_PERF_CNT(display, cpu_transcoder);
@@ -330,8 +330,8 @@ static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,
 		return HSW_SRD_PERF_CNT;
 }
 
-static i915_reg_t psr_status_reg(struct intel_display *display,
-				 enum transcoder cpu_transcoder)
+static intel_reg_t psr_status_reg(struct intel_display *display,
+				  enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_STATUS(display, cpu_transcoder);
@@ -339,8 +339,8 @@ static i915_reg_t psr_status_reg(struct intel_display *display,
 		return HSW_SRD_STATUS;
 }
 
-static i915_reg_t psr_imr_reg(struct intel_display *display,
-			      enum transcoder cpu_transcoder)
+static intel_reg_t psr_imr_reg(struct intel_display *display,
+			       enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 12)
 		return TRANS_PSR_IMR(display, cpu_transcoder);
@@ -348,8 +348,8 @@ static i915_reg_t psr_imr_reg(struct intel_display *display,
 		return EDP_PSR_IMR;
 }
 
-static i915_reg_t psr_iir_reg(struct intel_display *display,
-			      enum transcoder cpu_transcoder)
+static intel_reg_t psr_iir_reg(struct intel_display *display,
+			       enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 12)
 		return TRANS_PSR_IIR(display, cpu_transcoder);
@@ -357,8 +357,8 @@ static i915_reg_t psr_iir_reg(struct intel_display *display,
 		return EDP_PSR_IIR;
 }
 
-static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,
-				  enum transcoder cpu_transcoder)
+static intel_reg_t psr_aux_ctl_reg(struct intel_display *display,
+				   enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_AUX_CTL(display, cpu_transcoder);
@@ -366,8 +366,8 @@ static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,
 		return HSW_SRD_AUX_CTL;
 }
 
-static i915_reg_t psr_aux_data_reg(struct intel_display *display,
-				   enum transcoder cpu_transcoder, int i)
+static intel_reg_t psr_aux_data_reg(struct intel_display *display,
+				    enum transcoder cpu_transcoder, int i)
 {
 	if (DISPLAY_VER(display) >= 8)
 		return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);
@@ -2319,7 +2319,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
-	i915_reg_t psr_status;
+	intel_reg_t psr_status;
 	u32 psr_status_mask;
 
 	if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
@@ -3350,7 +3350,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 mask;
 	int err;
 
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 2e1af9e869de..56005b046f00 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -101,7 +101,7 @@ struct intel_sdvo {
 	struct intel_sdvo_ddc ddc[3];
 
 	/* Register for the SDVO device: SDVOB or SDVOC */
-	i915_reg_t sdvo_reg;
+	intel_reg_t sdvo_reg;
 
 	/*
 	 * Capabilities of the SDVO device returned by
@@ -1665,7 +1665,7 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
 }
 
 bool intel_sdvo_port_enabled(struct intel_display *display,
-			     i915_reg_t sdvo_reg, enum pipe *pipe)
+			     intel_reg_t sdvo_reg, enum pipe *pipe)
 {
 	u32 val;
 
@@ -3377,7 +3377,7 @@ static bool assert_sdvo_port_valid(struct intel_display *display, enum port port
 }
 
 bool intel_sdvo_init(struct intel_display *display,
-		     i915_reg_t sdvo_reg, enum port port)
+		     intel_reg_t sdvo_reg, enum port port)
 {
 	struct intel_encoder *intel_encoder;
 	struct intel_sdvo *intel_sdvo;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h
index 1a9e40fdd8a8..d1e1083de037 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.h
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum pipe;
 enum port;
@@ -16,17 +16,17 @@ struct intel_display;
 
 #ifdef I915
 bool intel_sdvo_port_enabled(struct intel_display *display,
-			     i915_reg_t sdvo_reg, enum pipe *pipe);
+			     intel_reg_t sdvo_reg, enum pipe *pipe);
 bool intel_sdvo_init(struct intel_display *display,
-		     i915_reg_t reg, enum port port);
+		     intel_reg_t reg, enum port port);
 #else
 static inline bool intel_sdvo_port_enabled(struct intel_display *display,
-					   i915_reg_t sdvo_reg, enum pipe *pipe)
+					   intel_reg_t sdvo_reg, enum pipe *pipe)
 {
 	return false;
 }
 static inline bool intel_sdvo_init(struct intel_display *display,
-				   i915_reg_t reg, enum port port)
+				   intel_reg_t reg, enum port port)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 5e5dde8f3e3a..bf9df566630f 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -1822,7 +1822,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
 	struct intel_display *display = to_intel_display(encoder);
 	const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
 	enum phy phy = intel_encoder_to_phy(encoder);
-	i915_reg_t enable_reg = (phy <= PHY_D ?
+	intel_reg_t enable_reg = (phy <= PHY_D ?
 				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
 
 	/*
@@ -1879,7 +1879,7 @@ void intel_mpllb_disable(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
-	i915_reg_t enable_reg = (phy <= PHY_D ?
+	intel_reg_t enable_reg = (phy <= PHY_D ?
 				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index a21dd4e3fe4c..ef1cf62749ec 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -294,7 +294,7 @@ get_pin_assignment(struct intel_tc_port *tc)
 	struct intel_display *display = to_intel_display(tc->dig_port);
 	enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
 	enum intel_tc_pin_assignment pin_assignment;
-	i915_reg_t reg;
+	intel_reg_t reg;
 	u32 mask;
 	u32 val;
 
@@ -1034,7 +1034,7 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
 {
 	struct intel_display *display = to_intel_display(tc->dig_port);
 	enum port port = tc->dig_port->base.port;
-	i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+	intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
 
 	assert_tc_cold_blocked(tc);
 
@@ -1094,7 +1094,7 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena
 {
 	struct intel_display *display = to_intel_display(tc->dig_port);
 	enum port port = tc->dig_port->base.port;
-	i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+	intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
 	u32 val;
 
 	assert_tc_cold_blocked(tc);
@@ -1141,7 +1141,7 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
 {
 	struct intel_display *display = to_intel_display(tc->dig_port);
 	enum port port = tc->dig_port->base.port;
-	i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+	intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
 	u32 val;
 
 	assert_tc_cold_blocked(tc);
@@ -1158,7 +1158,7 @@ static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
 {
 	struct intel_display *display = to_intel_display(tc->dig_port);
 	enum port port = tc->dig_port->base.port;
-	i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+	intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
 
 	assert_tc_cold_blocked(tc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0726a2abed38..28d81199792e 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -482,7 +482,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 static bool pipe_scanline_is_moving(struct intel_display *display,
 				    enum pipe pipe)
 {
-	i915_reg_t reg = PIPEDSL(display, pipe);
+	intel_reg_t reg = PIPEDSL(display, pipe);
 	u32 line1, line2;
 
 	line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6c09c6d99ffe..8f06c3a4d56d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -483,7 +483,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 }
 
 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
-				  i915_reg_t *dsc_reg, int dsc_reg_num)
+				  intel_reg_t *dsc_reg, int dsc_reg_num)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -506,7 +506,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
 				int pps, u32 pps_val)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	i915_reg_t dsc_reg[3];
+	intel_reg_t dsc_reg[3];
 	int i, vdsc_per_pipe, dsc_reg_num;
 
 	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
@@ -843,13 +843,13 @@ void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_en
 		intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
 }
 
-static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+static intel_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
 	return is_pipe_dsc(crtc, cpu_transcoder) ?
 		ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
 }
 
-static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+static intel_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
 	return is_pipe_dsc(crtc, cpu_transcoder) ?
 		ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
@@ -929,7 +929,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
 			      bool *all_equal)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	i915_reg_t dsc_reg[3];
+	intel_reg_t dsc_reg[3];
 	int i, vdsc_per_pipe, dsc_reg_num;
 	u32 val;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index 9832a4ade318..4966fd7eea92 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -35,7 +35,7 @@ static bool intel_vga_decode_is_enabled(struct intel_display *display)
 	return !(gmch_ctrl & INTEL_GMCH_VGA_DISABLE);
 }
 
-static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
+static intel_reg_t intel_vga_cntrl_reg(struct intel_display *display)
 {
 	if (display->platform.valleyview || display->platform.cherryview)
 		return VLV_VGACNTRL;
@@ -179,7 +179,7 @@ static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool
 void intel_vga_disable(struct intel_display *display)
 {
 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
-	i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
+	intel_reg_t vga_reg = intel_vga_cntrl_reg(display);
 	bool mmio = has_vga_mmio_access(display);
 	bool io_decode;
 	u8 msr, sr1;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 76e8cd0f65a4..877eab75f19a 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -99,7 +99,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 }
 
 static void write_data(struct intel_display *display,
-		       i915_reg_t reg,
+		       intel_reg_t reg,
 		       const u8 *data, u32 len)
 {
 	u32 i, j;
@@ -115,7 +115,7 @@ static void write_data(struct intel_display *display,
 }
 
 static void read_data(struct intel_display *display,
-		      i915_reg_t reg,
+		      intel_reg_t reg,
 		      u8 *data, u32 len)
 {
 	u32 i, j;
@@ -138,7 +138,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 	struct mipi_dsi_packet packet;
 	ssize_t ret;
 	const u8 *header;
-	i915_reg_t data_reg, ctrl_reg;
+	intel_reg_t data_reg, ctrl_reg;
 	u32 data_mask, ctrl_mask;
 
 	ret = mipi_dsi_create_packet(&packet, msg);
@@ -559,7 +559,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 	glk_dsi_disable_mipi_io(encoder);
 }
 
-static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
+static intel_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
 {
 	return display->platform.geminilake || display->platform.broxton ?
 		BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
@@ -574,7 +574,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 	drm_dbg_kms(display->drm, "\n");
 	for_each_dsi_port(port, intel_dsi->ports) {
 		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
-		i915_reg_t port_ctrl = display->platform.broxton ?
+		intel_reg_t port_ctrl = display->platform.broxton ?
 			BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
 
 		intel_de_write(display, MIPI_DEVICE_READY(display, port),
@@ -631,7 +631,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+		intel_reg_t port_ctrl = port_ctrl_reg(display, port);
 		u32 temp;
 
 		temp = intel_de_read(display, port_ctrl);
@@ -666,7 +666,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 	enum port port;
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+		intel_reg_t port_ctrl = port_ctrl_reg(display, port);
 
 		/* de-assert ip_tg_enable signal */
 		intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
@@ -957,7 +957,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 
 	/* XXX: this only works for one DSI output */
 	for_each_dsi_port(port, intel_dsi->ports) {
-		i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+		intel_reg_t port_ctrl = port_ctrl_reg(display, port);
 		bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
 
 		/*
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [RESEND 2/4] drm/i915/display: add struct intel_irq_regs and use it
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
  2026-05-05  9:16 ` [RESEND 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
@ 2026-05-05  9:16 ` Jani Nikula
  2026-05-05  9:16 ` [RESEND 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-05  9:16 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Michał Grzelak, ville.syrjala

Add struct intel_irq_regs, a display version of struct i915_irq_regs,
and use it. The goal is to reduce the dependency on i915 core types and
headers.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  4 +-
 .../drm/i915/display/intel_display_reg_defs.h | 10 ++++
 .../gpu/drm/i915/display/intel_display_regs.h | 48 +++++++++----------
 3 files changed, 36 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9bd72a99db2b..0c9c21b1290b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -30,7 +30,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 
-static void irq_reset(struct intel_display *display, struct i915_irq_regs regs)
+static void irq_reset(struct intel_display *display, struct intel_irq_regs regs)
 {
 	intel_de_write(display, regs.imr, 0xffffffff);
 	intel_de_posting_read(display, regs.imr);
@@ -63,7 +63,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg)
 	intel_de_posting_read(display, reg);
 }
 
-static void irq_init(struct intel_display *display, struct i915_irq_regs regs,
+static void irq_init(struct intel_display *display, struct intel_irq_regs regs,
 		     u32 imr_val, u32 ier_val)
 {
 	assert_iir_is_zero(display, regs.iir);
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index cb46863693cd..d044967aa6d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -10,6 +10,16 @@
 
 typedef i915_reg_t intel_reg_t;
 
+/* A triplet for IMR/IER/IIR registers. */
+struct intel_irq_regs {
+	intel_reg_t imr;
+	intel_reg_t ier;
+	intel_reg_t iir;
+};
+
+#define INTEL_IRQ_REGS(_imr, _ier, _iir) \
+	((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
+
 #define VLV_DISPLAY_BASE		0x180000
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..4fc18e5ee239 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -105,9 +105,9 @@
 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
 
-#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
-					      VLV_IER, \
-					      VLV_IIR)
+#define VLV_IRQ_REGS		INTEL_IRQ_REGS(VLV_IMR, \
+					       VLV_IER, \
+					       VLV_IIR)
 
 #define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
 #define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
@@ -1116,9 +1116,9 @@
 #define DEIIR   _MMIO(0x44008)
 #define DEIER   _MMIO(0x4400c)
 
-#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
-					      DEIER, \
-					      DEIIR)
+#define DE_IRQ_REGS		INTEL_IRQ_REGS(DEIMR, \
+					       DEIER, \
+					       DEIIR)
 
 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
@@ -1407,9 +1407,9 @@
 #define  GEN8_PIPE_VSYNC		REG_BIT(1)
 #define  GEN8_PIPE_VBLANK		REG_BIT(0)
 
-#define GEN8_DE_PIPE_IRQ_REGS(pipe)	I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
-						      GEN8_DE_PIPE_IER(pipe), \
-						      GEN8_DE_PIPE_IIR(pipe))
+#define GEN8_DE_PIPE_IRQ_REGS(pipe)	INTEL_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
+						       GEN8_DE_PIPE_IER(pipe), \
+						       GEN8_DE_PIPE_IIR(pipe))
 
 #define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
 #define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
@@ -1446,9 +1446,9 @@
 #define  TGL_DE_PORT_AUX_DDIB		REG_BIT(1)
 #define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
 
-#define GEN8_DE_PORT_IRQ_REGS		I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
-						      GEN8_DE_PORT_IER, \
-						      GEN8_DE_PORT_IIR)
+#define GEN8_DE_PORT_IRQ_REGS		INTEL_IRQ_REGS(GEN8_DE_PORT_IMR, \
+						       GEN8_DE_PORT_IER, \
+						       GEN8_DE_PORT_IIR)
 
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
@@ -1499,9 +1499,9 @@
 #define  XELPDP_PMDEMAND_RSP		REG_BIT(3)
 #define  XE2LPD_DBUF_OVERLAP_DETECTED	REG_BIT(1)
 
-#define GEN8_DE_MISC_IRQ_REGS		I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
-						      GEN8_DE_MISC_IER, \
-						      GEN8_DE_MISC_IIR)
+#define GEN8_DE_MISC_IRQ_REGS		INTEL_IRQ_REGS(GEN8_DE_MISC_IMR, \
+						       GEN8_DE_MISC_IER, \
+						       GEN8_DE_MISC_IIR)
 
 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
 #define  GEN11_DISPLAY_IRQ_ENABLE	(1 << 31)
@@ -1533,9 +1533,9 @@
 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
 
-#define GEN11_DE_HPD_IRQ_REGS		I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
-						      GEN11_DE_HPD_IER, \
-						      GEN11_DE_HPD_IIR)
+#define GEN11_DE_HPD_IRQ_REGS		INTEL_IRQ_REGS(GEN11_DE_HPD_IMR, \
+						       GEN11_DE_HPD_IER, \
+						       GEN11_DE_HPD_IIR)
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
@@ -1557,9 +1557,9 @@
 #define  XELPDP_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
 #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
 
-#define PICAINTERRUPT_IRQ_REGS			I915_IRQ_REGS(PICAINTERRUPT_IMR, \
-							      PICAINTERRUPT_IER, \
-							      PICAINTERRUPT_IIR)
+#define PICAINTERRUPT_IRQ_REGS			INTEL_IRQ_REGS(PICAINTERRUPT_IMR, \
+							       PICAINTERRUPT_IER, \
+							       PICAINTERRUPT_IIR)
 
 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin)	_MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
 #define  XELPDP_TBT_HOTPLUG_ENABLE		REG_BIT(6)
@@ -1875,9 +1875,9 @@
 #define SDEIIR  _MMIO(0xc4008)
 #define SDEIER  _MMIO(0xc400c)
 
-#define SDE_IRQ_REGS			I915_IRQ_REGS(SDEIMR, \
-						      SDEIER, \
-						      SDEIIR)
+#define SDE_IRQ_REGS			INTEL_IRQ_REGS(SDEIMR, \
+						       SDEIER, \
+						       SDEIIR)
 
 #define SERR_INT			_MMIO(0xc4040)
 #define  SERR_INT_POISON		(1 << 31)
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [RESEND 3/4] drm/i915/display: add struct intel_error_regs and use it
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
  2026-05-05  9:16 ` [RESEND 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
  2026-05-05  9:16 ` [RESEND 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula
@ 2026-05-05  9:16 ` Jani Nikula
  2026-05-05  9:16 ` [RESEND 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-05  9:16 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Michał Grzelak, ville.syrjala

Add struct intel_error_regs, a display version of struct
i915_error_regs, and use it. The goal is to reduce the dependency on
i915 core types and headers.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_display_regs.h     | 2 +-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0c9c21b1290b..b679992cb1e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -73,7 +73,7 @@ static void irq_init(struct intel_display *display, struct intel_irq_regs regs,
 	intel_de_posting_read(display, regs.imr);
 }
 
-static void error_reset(struct intel_display *display, struct i915_error_regs regs)
+static void error_reset(struct intel_display *display, struct intel_error_regs regs)
 {
 	intel_de_write(display, regs.emr, 0xffffffff);
 	intel_de_posting_read(display, regs.emr);
@@ -84,7 +84,7 @@ static void error_reset(struct intel_display *display, struct i915_error_regs re
 	intel_de_posting_read(display, regs.eir);
 }
 
-static void error_init(struct intel_display *display, struct i915_error_regs regs,
+static void error_init(struct intel_display *display, struct intel_error_regs regs,
 		       u32 emr_val)
 {
 	intel_de_write(display, regs.eir, 0xffffffff);
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index d044967aa6d9..a56f8ed055f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -20,6 +20,14 @@ struct intel_irq_regs {
 #define INTEL_IRQ_REGS(_imr, _ier, _iir) \
 	((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
 
+struct intel_error_regs {
+	intel_reg_t emr;
+	intel_reg_t eir;
+};
+
+#define INTEL_ERROR_REGS(_emr, _eir) \
+	((const struct intel_error_regs){ .emr = (_emr), .eir = (_eir) })
+
 #define VLV_DISPLAY_BASE		0x180000
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4fc18e5ee239..d87e52d278c7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -117,7 +117,7 @@
 #define   VLV_ERROR_PAGE_TABLE				(1 << 4)
 #define   VLV_ERROR_CLAIM				(1 << 0)
 
-#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+#define VLV_ERROR_REGS		INTEL_ERROR_REGS(VLV_EMR, VLV_EIR)
 
 #define _MBUS_ABOX0_CTL			0x45038
 #define _MBUS_ABOX1_CTL			0x45048
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [RESEND 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
                   ` (2 preceding siblings ...)
  2026-05-05  9:16 ` [RESEND 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula
@ 2026-05-05  9:16 ` Jani Nikula
  2026-05-05 13:13 ` ✓ i915.CI.BAT: success for drm/i915/display: start switching to display specific reg types (rev2) Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-05  9:16 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula, Michał Grzelak, ville.syrjala

Add display specific helpers for getting the register offset, checking
for equality and validity. Add them as static inlines for increased type
safety.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_de.h       |  2 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  2 +-
 .../drm/i915/display/intel_display_reg_defs.h | 15 +++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +--
 drivers/gpu/drm/i915/display/intel_dmc.c      | 26 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |  6 ++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  4 +--
 drivers/gpu/drm/i915/display/intel_dsb.c      | 10 +++----
 drivers/gpu/drm/i915/display/intel_mchbar.c   |  4 +--
 drivers/gpu/drm/i915/display/intel_pps.c      |  6 ++---
 11 files changed, 48 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index d17f14843f98..102979019429 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -56,7 +56,7 @@ intel_de_read64_2x32_volatile(struct intel_display *display,
 static inline u64
 intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg)
 {
-	intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4);
+	intel_reg_t upper_reg = _MMIO(intel_reg_offset(reg) + 4);
 	u32 lower, upper;
 
 	lower = intel_de_read(display, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 7260990038dd..69a9f782935c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1525,7 +1525,7 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
 	u32 val;
 	int i;
 
-	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
+	addr = pci_iomap_range(pdev, 0, intel_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
 	if (!addr) {
 		drm_err(display->drm,
 			"Cannot map MMIO BAR to read display GMD_ID\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b679992cb1e6..27fb72e5cefb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -56,7 +56,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg)
 
 	drm_WARN(display->drm, 1,
 		 "Interrupt register 0x%x is not zero: 0x%08x\n",
-		 i915_mmio_reg_offset(reg), val);
+		 intel_reg_offset(reg), val);
 	intel_de_write(display, reg, 0xffffffff);
 	intel_de_posting_read(display, reg);
 	intel_de_write(display, reg, 0xffffffff);
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index a56f8ed055f6..9220fcbfcb24 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -10,6 +10,21 @@
 
 typedef i915_reg_t intel_reg_t;
 
+static inline u32 intel_reg_offset(intel_reg_t r)
+{
+	return r.reg;
+}
+
+static inline bool intel_reg_equal(intel_reg_t a, intel_reg_t b)
+{
+	return intel_reg_offset(a) == intel_reg_offset(b);
+}
+
+static inline bool intel_reg_valid(intel_reg_t r)
+{
+	return !intel_reg_equal(r, INVALID_MMIO_REG);
+}
+
 /* A triplet for IMR/IER/IIR registers. */
 struct intel_irq_regs {
 	intel_reg_t imr;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7fcee3ee319c..c9e69f8a3626 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2117,7 +2117,7 @@ static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
 		return true;
 	case INTEL_OUTPUT_DDI:
 		/* Skip pure HDMI/DVI DDI encoders */
-		return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
+		return intel_reg_valid(enc_to_intel_dp(encoder)->output_reg);
 	default:
 		return false;
 	}
@@ -2130,7 +2130,7 @@ static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
 		return true;
 	case INTEL_OUTPUT_DDI:
 		/* See if the HDMI encoder is valid. */
-		return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
+		return intel_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg);
 	default:
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 6a39ad19b339..481fb65b7110 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -540,9 +540,9 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl)
 static bool is_dmc_evt_ctl_reg(struct intel_display *display,
 			       enum intel_dmc_id dmc_id, intel_reg_t reg)
 {
-	u32 offset = i915_mmio_reg_offset(reg);
-	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
-	u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
+	u32 offset = intel_reg_offset(reg);
+	u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
+	u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
 
 	return offset >= start && offset < end;
 }
@@ -550,9 +550,9 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display,
 static bool is_dmc_evt_htp_reg(struct intel_display *display,
 			       enum intel_dmc_id dmc_id, intel_reg_t reg)
 {
-	u32 offset = i915_mmio_reg_offset(reg);
-	u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
-	u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
+	u32 offset = intel_reg_offset(reg);
+	u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
+	u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
 
 	return offset >= start && offset < end;
 }
@@ -578,8 +578,8 @@ static bool fixup_dmc_evt(struct intel_display *display,
 		return false;
 
 	/* make sure reg_ctl and reg_htp are for the same event */
-	if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=
-	    i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))
+	if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=
+	    intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))
 		return false;
 
 	/*
@@ -703,7 +703,7 @@ static void assert_dmc_loaded(struct intel_display *display,
 
 		drm_WARN(display->drm, found != expected,
 			 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n",
-			 dmc_id, i, i915_mmio_reg_offset(reg), expected, found);
+			 dmc_id, i, intel_reg_offset(reg), expected, found);
 	}
 }
 
@@ -1146,17 +1146,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 
 		drm_dbg_kms(display->drm,
 			    " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n",
-			    i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]),
+			    i, intel_reg_offset(dmc_info->mmioaddr[i]),
 			    orig_mmiodata[0], dmc_info->mmiodata[i]);
 		drm_dbg_kms(display->drm,
 			    " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n",
-			    i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]),
+			    i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]),
 			    orig_mmiodata[1], dmc_info->mmiodata[i+1]);
 	}
 
 	for (i = 0; i < mmio_count; i++) {
 		drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
-			    i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i],
+			    i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i],
 			    is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
 			    is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
 			    disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
@@ -1672,7 +1672,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
 		seq_printf(m, "DC5 -> DC6 allowed count: %d\n",
 			   dc6_allowed_count);
-	else if (i915_mmio_reg_valid(dc6_reg))
+	else if (intel_reg_valid(dc6_reg))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   intel_de_read(display, dc6_reg));
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 82afb60fa973..605a4a555601 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -227,7 +227,7 @@ static void __intel_dmc_wl_take(struct intel_display *display)
 static bool intel_dmc_wl_reg_in_range(intel_reg_t reg,
 				      const struct intel_dmc_wl_range ranges[])
 {
-	u32 offset = i915_mmio_reg_offset(reg);
+	u32 offset = intel_reg_offset(reg);
 
 	for (int i = 0; ranges[i].start; i++) {
 		u32 end = ranges[i].end ?: ranges[i].start;
@@ -441,7 +441,7 @@ void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg)
 
 	spin_lock_irqsave(&wl->lock, flags);
 
-	if (i915_mmio_reg_valid(reg) &&
+	if (intel_reg_valid(reg) &&
 	    !intel_dmc_wl_check_range(display, reg, wl->dc_state))
 		goto out_unlock;
 
@@ -474,7 +474,7 @@ void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg)
 
 	spin_lock_irqsave(&wl->lock, flags);
 
-	if (i915_mmio_reg_valid(reg) &&
+	if (intel_reg_valid(reg) &&
 	    !intel_dmc_wl_check_range(display, reg, wl->dc_state))
 		goto out_unlock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6acdfa97deaa..e2e2a1c2a6e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3842,9 +3842,9 @@ static void icl_dpll_write(struct intel_display *display,
 	intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
 	intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
 	drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
-			 !i915_mmio_reg_valid(div0_reg));
+			 !intel_reg_valid(div0_reg));
 	if (display->vbt.override_afc_startup &&
-	    i915_mmio_reg_valid(div0_reg))
+	    intel_reg_valid(div0_reg))
 		intel_de_rmw(display, div0_reg,
 			     TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
 	intel_de_posting_read(display, cfgcr1_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ce4d452ae695..fec8a56e21ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -341,7 +341,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
 	prev_opcode = dsb->ins[1] & ~DSB_REG_VALUE_MASK;
 	prev_reg =  dsb->ins[1] & DSB_REG_VALUE_MASK;
 
-	return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
+	return prev_opcode == opcode && prev_reg == intel_reg_offset(reg);
 }
 
 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg)
@@ -386,7 +386,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
 	if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg))
 		intel_dsb_emit(dsb, 0, /* count */
 			       (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) |
-			       i915_mmio_reg_offset(reg));
+			       intel_reg_offset(reg));
 
 	if (!assert_dsb_has_room(dsb))
 		return;
@@ -407,7 +407,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
 	intel_dsb_emit(dsb, val,
 		       (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
 		       (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
-		       i915_mmio_reg_offset(reg));
+		       intel_reg_offset(reg));
 }
 
 static u32 intel_dsb_mask_to_byte_en(u32 mask)
@@ -425,7 +425,7 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
 	intel_dsb_emit(dsb, val,
 		       (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
 		       (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) |
-		       i915_mmio_reg_offset(reg));
+		       intel_reg_offset(reg));
 }
 
 void intel_dsb_noop(struct intel_dsb *dsb, int count)
@@ -565,7 +565,7 @@ void intel_dsb_poll(struct intel_dsb *dsb,
 
 	intel_dsb_emit(dsb, val,
 		       (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) |
-		       i915_mmio_reg_offset(reg));
+		       intel_reg_offset(reg));
 }
 
 static void intel_dsb_align_tail(struct intel_dsb *dsb)
diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c
index 8cfcee4a08a4..a3a69e11c390 100644
--- a/drivers/gpu/drm/i915/display/intel_mchbar.c
+++ b/drivers/gpu/drm/i915/display/intel_mchbar.c
@@ -44,7 +44,7 @@ static u32 mchbar_mirror_len(struct intel_display *display)
 static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
 {
 	return has_mchbar_mirror(display) &&
-		in_range32(i915_mmio_reg_offset(reg),
+		in_range32(intel_reg_offset(reg),
 			   mchbar_mirror_base(display),
 			   mchbar_mirror_len(display));
 }
@@ -53,7 +53,7 @@ static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
 {
 	drm_WARN(display->drm, !is_mchbar_reg(display, reg),
 		 "Reading non-MCHBAR register 0x%x\n",
-		 i915_mmio_reg_offset(reg));
+		 intel_reg_offset(reg));
 }
 
 u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index ea5e8f75acef..d4c98b150fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1388,7 +1388,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *s
 	seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
 	seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
 
-	if (i915_mmio_reg_valid(regs.pp_div)) {
+	if (intel_reg_valid(regs.pp_div)) {
 		u32 pp_div;
 
 		pp_div = intel_de_read(display, regs.pp_div);
@@ -1647,7 +1647,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
 	/*
 	 * Compute the divisor for the pp clock, simply match the Bspec formula.
 	 */
-	if (i915_mmio_reg_valid(regs.pp_div))
+	if (intel_reg_valid(regs.pp_div))
 		intel_de_write(display, regs.pp_div,
 			       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK,
 					      (100 * div) / 2 - 1) |
@@ -1662,7 +1662,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
 		    "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
 		    intel_de_read(display, regs.pp_on),
 		    intel_de_read(display, regs.pp_off),
-		    i915_mmio_reg_valid(regs.pp_div) ?
+		    intel_reg_valid(regs.pp_div) ?
 		    intel_de_read(display, regs.pp_div) :
 		    (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
 }
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* ✓ i915.CI.BAT: success for drm/i915/display: start switching to display specific reg types (rev2)
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
                   ` (3 preceding siblings ...)
  2026-05-05  9:16 ` [RESEND 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula
@ 2026-05-05 13:13 ` Patchwork
  2026-05-05 21:11 ` ✗ i915.CI.Full: failure " Patchwork
  2026-05-08 11:29 ` [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
  6 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-05-05 13:13 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 2732 bytes --]

== Series Details ==

Series: drm/i915/display: start switching to display specific reg types (rev2)
URL   : https://patchwork.freedesktop.org/series/164541/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18416 -> Patchwork_164541v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/index.html

Participating hosts (42 -> 39)
------------------------------

  Missing    (3): bat-dg2-13 fi-snb-2520m bat-adls-6 

Known issues
------------

  Here are the changes found in Patchwork_164541v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/bat-arls-5/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_18416 -> Patchwork_164541v2

  CI-20190529: 20190529
  CI_DRM_18416: 1dac77f19ea5122c3a99646ff44e5a0fa10eca1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8886: 0c1d7a87341d565ed0dfb6ae37e6aa851fede9cd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_164541v2: 1dac77f19ea5122c3a99646ff44e5a0fa10eca1c @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/index.html

[-- Attachment #2: Type: text/html, Size: 3617 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* ✗ i915.CI.Full: failure for drm/i915/display: start switching to display specific reg types (rev2)
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
                   ` (4 preceding siblings ...)
  2026-05-05 13:13 ` ✓ i915.CI.BAT: success for drm/i915/display: start switching to display specific reg types (rev2) Patchwork
@ 2026-05-05 21:11 ` Patchwork
  2026-05-08 11:29 ` [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
  6 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-05-05 21:11 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 107803 bytes --]

== Series Details ==

Series: drm/i915/display: start switching to display specific reg types (rev2)
URL   : https://patchwork.freedesktop.org/series/164541/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18416_full -> Patchwork_164541v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_164541v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_164541v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_164541v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_linear_blits@interruptible:
    - shard-dg2:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-7/igt@gem_linear_blits@interruptible.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_linear_blits@interruptible.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbchdr-suspend:
    - shard-glk:          [SKIP][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk4/igt@kms_frontbuffer_tracking@fbchdr-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_164541v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-tglu:         NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@device_reset@cold-reset-bound.html
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#11078])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@device_reset@cold-reset-bound.html

  * igt@dmabuf@all-tests:
    - shard-rkl:          NOTRUN -> [SKIP][8] ([i915#15931])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@dmabuf@all-tests.html

  * igt@gem_basic@multigpu-create-close:
    - shard-rkl:          NOTRUN -> [SKIP][9] ([i915#7697])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][12] ([i915#13356]) +1 other test incomplete
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk11/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@heartbeat-hang:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#8555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hang.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#280]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#4036])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu-1:       NOTRUN -> [SKIP][16] ([i915#6334]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][17] ([i915#11965]) +4 other tests fail
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_endless@dispatch@vcs1:
    - shard-dg1:          [PASS][18] -> [TIMEOUT][19] ([i915#3778]) +1 other test timeout
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-17/igt@gem_exec_endless@dispatch@vcs1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-16/igt@gem_exec_endless@dispatch@vcs1.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#3539] / [i915#4852]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#3281]) +5 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-wc-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3281]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_exec_reloc@basic-wc-gtt.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4537] / [i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#4860])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#4613] / [i915#7582])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_lmem_evict@dontneed-evict-race.html
    - shard-tglu:         NOTRUN -> [SKIP][26] ([i915#4613] / [i915#7582])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][27] ([i915#4613])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          NOTRUN -> [SKIP][28] ([i915#4613]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-glk:          NOTRUN -> [SKIP][29] ([i915#4613]) +5 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap_gtt@zero-extend:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4077]) +7 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_mmap_gtt@zero-extend.html

  * igt@gem_mmap_wc@coherency:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#4083]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@gem_mmap_wc@coherency.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#3282]) +5 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pread@exhaustion:
    - shard-glk10:        NOTRUN -> [WARN][33] ([i915#2658])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-random:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#3282]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_pwrite@basic-random.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4270])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#13717])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#5190] / [i915#8428]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#8411])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#4885])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gem_softpin@evict-snoop.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#4879])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#3297] / [i915#3323])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#3297] / [i915#4880]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#3297])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3297])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-rkl:          NOTRUN -> [SKIP][45] ([i915#3297]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gen7_exec_parse@basic-rejected:
    - shard-dg2:          NOTRUN -> [SKIP][46] +5 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gen7_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][47] ([i915#2527] / [i915#2856])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-tglu:         NOTRUN -> [SKIP][48] ([i915#2527] / [i915#2856])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#2527]) +6 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@gen9_exec_parse@shadow-peek.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#2856]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_drm_fdinfo@isolation@rcs0:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#14073]) +7 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@i915_drm_fdinfo@isolation@rcs0.html

  * igt@i915_module_load@fault-injection@intel_connector_register:
    - shard-glk:          NOTRUN -> [ABORT][52] ([i915#15342]) +1 other test abort
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk4/igt@i915_module_load@fault-injection@intel_connector_register.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#8399])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rps@thresholds-park:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#11681])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@i915_pm_rps@thresholds-park.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#4387])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#6188])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_suspend@forcewake:
    - shard-glk:          NOTRUN -> [INCOMPLETE][57] ([i915#4817])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk2/igt@i915_suspend@forcewake.html
    - shard-dg2:          NOTRUN -> [ABORT][58] ([i915#15140])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@i915_suspend@forcewake.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-dg1:          [PASS][59] -> [FAIL][60] ([i915#14888])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-19/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-c-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [FAIL][61] ([i915#14888])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-15/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-c-hdmi-a-1.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [FAIL][62] ([i915#14888]) +1 other test fail
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-c-hdmi-a-2.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][63] ([i915#12761])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][64] ([i915#12761] / [i915#14995])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#1769] / [i915#3555])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][66] -> [FAIL][67] ([i915#15662]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-tglu-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-2/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][68] ([i915#5286])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#5286]) +7 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][70] ([i915#5286])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#3638]) +5 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#3828])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#4538] / [i915#5190]) +4 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#10307] / [i915#6095]) +73 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#14098] / [i915#14544] / [i915#6095]) +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#12313]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][78] ([i915#12313])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#6095]) +19 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][80] ([i915#12805])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#14098] / [i915#6095]) +63 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#6095]) +12 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#12313])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#6095]) +71 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#6095]) +93 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#14544] / [i915#6095]) +13 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#13781]) +4 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          NOTRUN -> [SKIP][88] ([i915#3742])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#11151] / [i915#7828]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#11151] / [i915#7828]) +11 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([i915#11151] / [i915#7828]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] ([i915#11151] / [i915#7828]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#15330] / [i915#3299])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#15330] / [i915#3116])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#15330])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#15330])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#15330])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#15865]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#13049])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-rkl:          NOTRUN -> [FAIL][100] ([i915#13566]) +6 other tests fail
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         [PASS][101] -> [FAIL][102] ([i915#13566]) +3 other tests fail
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-tglu-9/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-256x85.html
    - shard-rkl:          [PASS][103] -> [FAIL][104] ([i915#13566])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-dg2:          NOTRUN -> [SKIP][105] ([i915#3555]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [FAIL][106] ([i915#13566]) +1 other test fail
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][107] ([i915#3555])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#13049]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][109] +498 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#3555]) +5 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#4103])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#13046] / [i915#5354]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          NOTRUN -> [FAIL][113] ([i915#15804]) +1 other test fail
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
    - shard-dg1:          [PASS][114] -> [FAIL][115] ([i915#15999])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-14/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-14/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#4103] / [i915#4213]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#3555] / [i915#3804])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#3804])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-tglu-1:       NOTRUN -> [SKIP][119] ([i915#13749])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#13748])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu:         NOTRUN -> [SKIP][121] ([i915#3555] / [i915#3840])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-tglu-1:       NOTRUN -> [SKIP][122] ([i915#3840])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#3555] / [i915#3840])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][124] ([i915#3840] / [i915#9053])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#1839]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#658])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] ([i915#3637] / [i915#9934]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][128] ([i915#12745] / [i915#4839])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk6/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][129] ([i915#12745])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk6/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-tglu:         NOTRUN -> [SKIP][130] ([i915#3637] / [i915#9934])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#9934]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#9934]) +7 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-rkl:          [PASS][133] -> [FAIL][134] ([i915#10826])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-4/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1:
    - shard-rkl:          NOTRUN -> [FAIL][135] ([i915#10826])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-8/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg2:          [PASS][136] -> [FAIL][137] ([i915#13027])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3:
    - shard-dg2:          NOTRUN -> [FAIL][138] ([i915#13027])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [PASS][139] -> [INCOMPLETE][140] ([i915#6113]) +1 other test incomplete
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-7/igt@kms_flip@flip-vs-suspend.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#15643]) +3 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
    - shard-tglu:         NOTRUN -> [SKIP][142] ([i915#15643])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#15643] / [i915#5190])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#15643]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#15104] / [i915#15990]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#15989]) +27 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#15989]) +2 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][148] +79 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][149] +28 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy:
    - shard-dg2:          [PASS][150] -> [SKIP][151] ([i915#15989]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-7/igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][152] ([i915#15989]) +9 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#15991] / [i915#5354]) +13 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-onoff:
    - shard-glk10:        NOTRUN -> [SKIP][154] +73 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#15102]) +32 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-shrfb-fliptrack-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#15990]) +14 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#15989]) +4 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-onoff:
    - shard-rkl:          [PASS][158] -> [SKIP][159] ([i915#15989]) +3 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-onoff.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@hdr-rgb565-draw-mmap-wc:
    - shard-glk:          [PASS][160] -> [SKIP][161] +3 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk8/igt@kms_frontbuffer_tracking@hdr-rgb565-draw-mmap-wc.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk6/igt@kms_frontbuffer_tracking@hdr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#15102] / [i915#3023]) +22 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-rte:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#15102] / [i915#3458]) +8 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#1825]) +52 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#15990] / [i915#8708]) +3 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-glk11:        NOTRUN -> [SKIP][166] +6 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk11/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-tglu:         NOTRUN -> [SKIP][167] ([i915#15102]) +9 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#15102]) +9 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move:
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#15102]) +13 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][170] +25 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#15991]) +18 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#3555] / [i915#8228]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#15460])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_joiner@basic-big-joiner.html
    - shard-tglu:         NOTRUN -> [SKIP][174] ([i915#15460])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][175] ([i915#15458])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][176] ([i915#6301])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_panel_fitting@legacy.html
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#6301])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#14712])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#15709]) +2 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier@pipe-b-plane-5:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#15608]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][181] ([i915#15709]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#15709]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#15709]) +2 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][184] ([i915#13026]) +1 other test incomplete
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk11/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#15329] / [i915#3555])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#15329]) +2 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html

  * igt@kms_pm_backlight@fade:
    - shard-tglu:         NOTRUN -> [SKIP][187] ([i915#9812])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#5354]) +2 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2:          NOTRUN -> [SKIP][189] ([i915#15948])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-tglu-1:       NOTRUN -> [SKIP][190] ([i915#3828])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#15073]) +1 other test skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress.html
    - shard-dg1:          [PASS][192] -> [SKIP][193] ([i915#15073]) +2 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-13/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][194] -> [SKIP][195] ([i915#15073]) +2 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#15073])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][197] ([i915#10553])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][198] ([i915#11520]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] ([i915#11520]) +1 other test skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][200] ([i915#11520]) +10 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk2/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][201] ([i915#11520]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk10/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#11520]) +3 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][203] ([i915#11520]) +8 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#9683])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][205] ([i915#9683])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-cursor-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][206] ([i915#9732]) +4 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html

  * igt@kms_psr@fbc-psr-primary-blt:
    - shard-rkl:          NOTRUN -> [SKIP][207] ([i915#1072] / [i915#9732]) +25 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_psr@fbc-psr-primary-blt.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][208] ([i915#9732]) +4 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#1072] / [i915#9732]) +9 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@kms_psr@psr-cursor-mmap-cpu.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#15949])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-tglu:         NOTRUN -> [SKIP][211] ([i915#15949])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          NOTRUN -> [INCOMPLETE][212] ([i915#15500])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          NOTRUN -> [INCOMPLETE][213] ([i915#15492])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk1/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][214] ([i915#5289])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#12755] / [i915#15867] / [i915#5190]) +1 other test skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#8623])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_universal_plane@universal-plane-pageflip-windowed:
    - shard-dg1:          [PASS][217] -> [DMESG-WARN][218] ([i915#4423]) +4 other tests dmesg-warn
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-16/igt@kms_universal_plane@universal-plane-pageflip-windowed.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-17/igt@kms_universal_plane@universal-plane-pageflip-windowed.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-rkl:          [PASS][219] -> [ABORT][220] ([i915#15132])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-1/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][221] -> [INCOMPLETE][222] ([i915#12276])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk4/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][223] ([i915#15132])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2.html

  * igt@kms_vrr@flip-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][224] ([i915#15243] / [i915#3555])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#9906])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@perf_pmu@frequency:
    - shard-dg2:          NOTRUN -> [FAIL][226] ([i915#12549] / [i915#6806]) +1 other test fail
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@perf_pmu@frequency.html

  * igt@perf_pmu@module-unload:
    - shard-glk:          NOTRUN -> [ABORT][227] ([i915#15778])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk1/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#8516])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-2/igt@perf_pmu@rc6-all-gts.html

  * igt@perf_pmu@rc6-suspend:
    - shard-rkl:          [PASS][229] -> [INCOMPLETE][230] ([i915#13520])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-7/igt@perf_pmu@rc6-suspend.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@perf_pmu@rc6-suspend.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#8516])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-8/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#3291] / [i915#3708])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-write:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#3291] / [i915#3708])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-6/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          NOTRUN -> [SKIP][234] ([i915#3708]) +1 other test skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#9917])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@sriov_basic@enable-vfs-autoprobe-off.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [INCOMPLETE][236] ([i915#13356]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-1/igt@gem_ccs@suspend-resume.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][238] ([i915#12392] / [i915#13356]) -> [PASS][239]
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-1/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-10/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-rkl:          [INCOMPLETE][240] ([i915#13356]) -> [PASS][241] +3 other tests pass
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@gem_ctx_isolation@preservation-s3.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-7/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_softpin@noreloc-s3:
    - shard-glk:          [INCOMPLETE][242] ([i915#13809]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk8/igt@gem_softpin@noreloc-s3.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk6/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [INCOMPLETE][244] ([i915#13356] / [i915#13820]) -> [PASS][245] +1 other test pass
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-3/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-4/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [INCOMPLETE][246] ([i915#4817]) -> [PASS][247]
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@i915_suspend@forcewake.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][248] ([i915#13566]) -> [PASS][249] +1 other test pass
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-9/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][250] ([i915#13027]) -> [PASS][251] +1 other test pass
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-snb:          [FAIL][252] ([i915#13027]) -> [PASS][253] +1 other test pass
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-snb1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-snb4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-dg1:          [DMESG-WARN][254] ([i915#4423]) -> [PASS][255]
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-12/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-12/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-mtlp:         [SKIP][256] ([i915#15672]) -> [PASS][257]
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-mtlp-1/igt@kms_force_connector_basic@prune-stale-modes.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-mtlp-2/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-pwrite:
    - shard-glk:          [SKIP][258] -> [PASS][259] +13 other tests pass
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-glk4/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-pwrite.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-wc:
    - shard-rkl:          [SKIP][260] ([i915#15989]) -> [PASS][261] +14 other tests pass
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-wc.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          [SKIP][262] ([i915#3555] / [i915#8228]) -> [PASS][263]
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_hdr@static-toggle-dpms.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_plane_cursor@overlay@pipe-d-edp-1-size-64:
    - shard-mtlp:         [DMESG-WARN][264] -> [PASS][265] +1 other test pass
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-mtlp-4/igt@kms_plane_cursor@overlay@pipe-d-edp-1-size-64.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-mtlp-8/igt@kms_plane_cursor@overlay@pipe-d-edp-1-size-64.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][266] ([i915#15073]) -> [PASS][267] +1 other test pass
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-19/igt@kms_pm_rpm@dpms-lpsp.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][268] ([i915#15073]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [SKIP][270] ([i915#15073]) -> [PASS][271] +3 other tests pass
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html

  
#### Warnings ####

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][272] ([i915#11078]) -> [SKIP][273] ([i915#11078] / [i915#14544])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@device_reset@unbind-cold-reset-rebind.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-rkl:          [SKIP][274] ([i915#3281]) -> [SKIP][275] ([i915#14544] / [i915#3281]) +3 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_bad_reloc@negative-reloc-lut.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][276] ([i915#14544] / [i915#9323]) -> [SKIP][277] ([i915#9323])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@gem_ccs@suspend-resume.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_ccs@suspend-resume.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][278] ([i915#14544] / [i915#4525]) -> [SKIP][279] ([i915#4525])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@gem_exec_balancer@parallel.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-rkl:          [SKIP][280] ([i915#4525]) -> [SKIP][281] ([i915#14544] / [i915#4525])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-rkl:          [SKIP][282] ([i915#14544] / [i915#3281]) -> [SKIP][283] ([i915#3281]) +1 other test skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@gem_exec_reloc@basic-write-gtt-active.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-rkl:          [SKIP][284] ([i915#4613]) -> [SKIP][285] ([i915#14544] / [i915#4613]) +1 other test skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_lmem_swapping@parallel-multi.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][286] ([i915#3282]) -> [SKIP][287] ([i915#14544] / [i915#3282]) +3 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_set_tiling_vs_pwrite.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          [SKIP][288] ([i915#3297]) -> [SKIP][289] ([i915#14544] / [i915#3297]) +1 other test skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_userptr_blits@coherency-sync.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          [SKIP][290] ([i915#3282] / [i915#3297]) -> [SKIP][291] ([i915#14544] / [i915#3282] / [i915#3297])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gem_userptr_blits@forbidden-operations.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          [SKIP][292] ([i915#14544] / [i915#3297]) -> [SKIP][293] ([i915#3297])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@gem_userptr_blits@unsync-unmap-cycles.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [SKIP][294] ([i915#2527]) -> [SKIP][295] ([i915#14544] / [i915#2527]) +1 other test skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@gen9_exec_parse@bb-start-param.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@gen9_exec_parse@bb-start-param.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-rkl:          [SKIP][296] ([i915#5286]) -> [SKIP][297] ([i915#14544] / [i915#5286]) +2 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-rkl:          [SKIP][298] ([i915#14544] / [i915#5286]) -> [SKIP][299] ([i915#5286])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-rkl:          [SKIP][300] ([i915#14544] / [i915#3638]) -> [SKIP][301] ([i915#3638])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-rkl:          [SKIP][302] -> [SKIP][303] ([i915#14544]) +30 other tests skip
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
    - shard-rkl:          [SKIP][304] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][305] ([i915#14098] / [i915#6095]) +3 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
    - shard-rkl:          [SKIP][306] ([i915#14098] / [i915#6095]) -> [SKIP][307] ([i915#14098] / [i915#14544] / [i915#6095]) +6 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][308] ([i915#12313] / [i915#14544]) -> [SKIP][309] ([i915#12313])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][310] ([i915#14544] / [i915#6095]) -> [SKIP][311] ([i915#6095]) +1 other test skip
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][312] ([i915#12313]) -> [SKIP][313] ([i915#12313] / [i915#14544])
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - shard-rkl:          [SKIP][314] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][315] ([i915#11151] / [i915#7828])
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-rkl:          [SKIP][316] ([i915#11151] / [i915#7828]) -> [SKIP][317] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_chamelium_hpd@dp-hpd-storm.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][318] ([i915#15865]) -> [SKIP][319] ([i915#14544] / [i915#15865]) +1 other test skip
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_content_protection@atomic.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          [SKIP][320] ([i915#14544] / [i915#15330] / [i915#3116]) -> [SKIP][321] ([i915#15330] / [i915#3116])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][322] ([i915#14544] / [i915#15865]) -> [SKIP][323] ([i915#15865])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_content_protection@mei-interface.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-3/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@uevent:
    - shard-dg2:          [FAIL][324] ([i915#1339] / [i915#7173]) -> [SKIP][325] ([i915#15865])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-10/igt@kms_content_protection@uevent.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-7/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-rkl:          [SKIP][326] ([i915#3555]) -> [SKIP][327] ([i915#14544] / [i915#3555])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_cursor_crc@cursor-offscreen-max-size.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-rkl:          [SKIP][328] ([i915#14544] / [i915#3555]) -> [SKIP][329] ([i915#3555])
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          [SKIP][330] ([i915#13049]) -> [SKIP][331] ([i915#13049] / [i915#14544])
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-rkl:          [SKIP][332] ([i915#14544]) -> [SKIP][333] +14 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][334] ([i915#13707]) -> [SKIP][335] ([i915#13707] / [i915#14544])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          [SKIP][336] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][337] ([i915#3555] / [i915#3840])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_dsc@dsc-basic.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          [SKIP][338] ([i915#3840]) -> [SKIP][339] ([i915#14544] / [i915#3840])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][340] ([i915#14544] / [i915#3955]) -> [SKIP][341] ([i915#3955])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][342] ([i915#14544] / [i915#9934]) -> [SKIP][343] ([i915#9934])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          [SKIP][344] ([i915#9934]) -> [SKIP][345] ([i915#14544] / [i915#9934]) +3 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_flip@2x-blocking-wf_vblank.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-rkl:          [SKIP][346] ([i915#14544] / [i915#15643]) -> [SKIP][347] ([i915#15643])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][348] ([i915#15643]) -> [SKIP][349] ([i915#14544] / [i915#15643]) +2 other tests skip
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][350] ([i915#14544] / [i915#15102]) -> [SKIP][351] ([i915#15102]) +7 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-rkl:          [SKIP][352] ([i915#15102] / [i915#3023]) -> [SKIP][353] ([i915#14544] / [i915#15102] / [i915#3023]) +6 other tests skip
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][354] ([i915#14544] / [i915#1825]) -> [SKIP][355] ([i915#1825]) +6 other tests skip
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][356] ([i915#1825]) -> [SKIP][357] ([i915#14544] / [i915#1825]) +15 other tests skip
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-dg2:          [SKIP][358] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][359] ([i915#15102] / [i915#3458])
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
    - shard-rkl:          [SKIP][360] ([i915#5439]) -> [SKIP][361] ([i915#14544] / [i915#5439])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-rkl:          [SKIP][362] ([i915#15102]) -> [SKIP][363] ([i915#14544] / [i915#15102]) +12 other tests skip
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          [SKIP][364] ([i915#15990] / [i915#8708]) -> [SKIP][365] ([i915#15990] / [i915#4423] / [i915#8708]) +1 other test skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-rkl:          [SKIP][366] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][367] ([i915#15102] / [i915#3023]) +5 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-tglu:         [SKIP][368] ([i915#1187] / [i915#12713]) -> [SKIP][369] ([i915#12713])
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][370] ([i915#14544] / [i915#3555] / [i915#8228]) -> [SKIP][371] ([i915#3555] / [i915#8228])
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_hdr@invalid-hdr.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-dg1:          [SKIP][372] ([i915#3555] / [i915#8228]) -> [SKIP][373] ([i915#3555] / [i915#4423] / [i915#8228])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-16/igt@kms_hdr@static-toggle.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-17/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          [SKIP][374] ([i915#13688]) -> [SKIP][375] ([i915#13688] / [i915#14544])
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_joiner@basic-max-non-joiner.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          [SKIP][376] ([i915#15638] / [i915#15722]) -> [SKIP][377] ([i915#14544] / [i915#15638] / [i915#15722])
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-rkl:          [SKIP][378] ([i915#15709]) -> [SKIP][379] ([i915#14544] / [i915#15709]) +1 other test skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-7/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][380] ([i915#14544] / [i915#15709]) -> [SKIP][381] ([i915#15709]) +3 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-4/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][382] ([i915#13958]) -> [SKIP][383] ([i915#13958] / [i915#14544]) +1 other test skip
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-none.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][384] ([i915#12343] / [i915#14544]) -> [SKIP][385] ([i915#12343])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          [SKIP][386] ([i915#15948]) -> [SKIP][387] ([i915#14544] / [i915#15948])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_pm_dc@dc5-psr.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [SKIP][388] ([i915#15128]) -> [FAIL][389] ([i915#15752])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][390] ([i915#9340]) -> [SKIP][391] ([i915#3828])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-8/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-rkl:          [SKIP][392] ([i915#11520] / [i915#14544]) -> [SKIP][393] ([i915#11520]) +2 other tests skip
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][394] ([i915#11520]) -> [SKIP][395] ([i915#11520] / [i915#14544]) +4 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-rkl:          [SKIP][396] ([i915#1072] / [i915#9732]) -> [SKIP][397] ([i915#1072] / [i915#14544] / [i915#9732]) +10 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-rkl:          [SKIP][398] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][399] ([i915#1072] / [i915#9732]) +3 other tests skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-6/igt@kms_psr@psr-sprite-plane-onoff.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-5/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_psr@psr2-basic:
    - shard-dg1:          [SKIP][400] ([i915#1072] / [i915#9732]) -> [SKIP][401] ([i915#1072] / [i915#4423] / [i915#9732])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg1-16/igt@kms_psr@psr2-basic.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg1-17/igt@kms_psr@psr2-basic.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-rkl:          [SKIP][402] ([i915#5289]) -> [SKIP][403] ([i915#14544] / [i915#5289])
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          [SKIP][404] ([i915#15867] / [i915#5190]) -> [SKIP][405] ([i915#12755] / [i915#15867] / [i915#5190])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-dg2-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-dg2-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_vrr@flipline:
    - shard-rkl:          [SKIP][406] ([i915#15243] / [i915#3555]) -> [SKIP][407] ([i915#14544] / [i915#15243] / [i915#3555])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@kms_vrr@flipline.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@kms_vrr@flipline.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][408] ([i915#2434]) -> [SKIP][409] ([i915#14544] / [i915#2434])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18416/shard-rkl-8/igt@perf@mi-rpc.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/shard-rkl-6/igt@perf@mi-rpc.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10553
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12549]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12549
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
  [i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#14995]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14995
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15342
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15500
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
  [i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15722]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15722
  [i915#15752]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15752
  [i915#15778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15778
  [i915#15804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15804
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15931
  [i915#15948]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15948
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#15999]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15999
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18416 -> Patchwork_164541v2

  CI-20190529: 20190529
  CI_DRM_18416: 1dac77f19ea5122c3a99646ff44e5a0fa10eca1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8886: 0c1d7a87341d565ed0dfb6ae37e6aa851fede9cd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_164541v2: 1dac77f19ea5122c3a99646ff44e5a0fa10eca1c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164541v2/index.html

[-- Attachment #2: Type: text/html, Size: 141721 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [RESEND 0/4] drm/i915/display: start switching to display specific reg types
  2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
                   ` (5 preceding siblings ...)
  2026-05-05 21:11 ` ✗ i915.CI.Full: failure " Patchwork
@ 2026-05-08 11:29 ` Jani Nikula
  6 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2026-05-08 11:29 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Michał Grzelak, ville.syrjala

On Tue, 05 May 2026, Jani Nikula <jani.nikula@intel.com> wrote:
> Jani Nikula (4):
>   drm/i915/display: add typedef for intel_reg_t and use it
>   drm/i915/display: add struct intel_irq_regs and use it
>   drm/i915/display: add struct intel_error_regs and use it
>   drm/i915/display: define and use intel_reg_{offset,equal,valid}()
>     helpers

Ville, ack on this one?

BR,
Jani


-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2026-05-08 11:29 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-05  9:16 [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
2026-05-05  9:16 ` [RESEND 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
2026-05-05  9:16 ` [RESEND 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula
2026-05-05  9:16 ` [RESEND 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula
2026-05-05  9:16 ` [RESEND 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula
2026-05-05 13:13 ` ✓ i915.CI.BAT: success for drm/i915/display: start switching to display specific reg types (rev2) Patchwork
2026-05-05 21:11 ` ✗ i915.CI.Full: failure " Patchwork
2026-05-08 11:29 ` [RESEND 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula

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