* [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming
@ 2019-09-26 21:06 José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: José Roberto de Souza @ 2019-09-26 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clinton A Taylor <clinton.a.taylor@intel.com>
BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
now taking in consideration the pin assignment and allowing us to
optimize power by shutting down available but not needed lanes.
It was tested on ICL and TGL, with adaptors that used pin assignment
C and B, reversing the connector and going to different modes testing
the not needed lane shutdown.
v5:
Using crtc_state->lane_count instead of dp.lane_count
BSpec: 21735
BSpec: 49292
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++++++++++++-----------
drivers/gpu/drm/i915/display/intel_tc.c | 15 ++++
drivers/gpu/drm/i915/display/intel_tc.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5 ++
4 files changed, 72 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa470c70a198..20393d39a29a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3091,11 +3091,14 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
I915_WRITE(MG_MISC_SUS0(tc_port), val);
}
-static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
+static void
+icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
- u32 ln0, ln1, lane_mask;
+ u32 ln0, ln1, pin_assignment;
+ u8 width;
if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
return;
@@ -3103,50 +3106,57 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
ln0 = I915_READ(MG_DP_MODE(0, port));
ln1 = I915_READ(MG_DP_MODE(1, port));
- switch (intel_dig_port->tc_mode) {
- case TC_PORT_DP_ALT:
- ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
- ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
+ ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
+ ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
- lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
+ /* DPPATC */
+ pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
+ width = crtc_state->lane_count;
- switch (lane_mask) {
- case 0x1:
- case 0x4:
- break;
- case 0x2:
+ switch (pin_assignment) {
+ case 0x0:
+ WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
+ if (width == 1) {
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
+ } else {
+ ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ }
+ break;
+ case 0x1:
+ if (width == 4) {
+ ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ }
+ break;
+ case 0x2:
+ if (width == 2) {
+ ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ }
+ break;
+ case 0x3:
+ case 0x5:
+ if (width == 1) {
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
- break;
- case 0x3:
- ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
- MG_DP_MODE_CFG_DP_X2_MODE;
- break;
- case 0x8:
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
- break;
- case 0xC:
- ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
- MG_DP_MODE_CFG_DP_X2_MODE;
- break;
- case 0xF:
- ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
- MG_DP_MODE_CFG_DP_X2_MODE;
- ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
- MG_DP_MODE_CFG_DP_X2_MODE;
- break;
- default:
- MISSING_CASE(lane_mask);
+ } else {
+ ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
}
break;
-
- case TC_PORT_LEGACY:
- ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
- ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
+ case 0x4:
+ case 0x6:
+ if (width == 1) {
+ ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
+ } else {
+ ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
+ }
break;
-
default:
- MISSING_CASE(intel_dig_port->tc_mode);
- return;
+ MISSING_CASE(pin_assignment);
}
I915_WRITE(MG_DP_MODE(0, port), ln0);
@@ -3239,7 +3249,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
dig_port->ddi_io_power_domain);
/* 6. */
- icl_program_mg_dp_mode(dig_port);
+ icl_program_mg_dp_mode(dig_port, crtc_state);
/*
* 7.a - Steps in this function should only be executed over MST
@@ -3321,7 +3331,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv,
dig_port->ddi_io_power_domain);
- icl_program_mg_dp_mode(dig_port);
+ icl_program_mg_dp_mode(dig_port, crtc_state);
icl_phy_set_clock_gating(dig_port, false);
if (INTEL_GEN(dev_priv) >= 11)
@@ -3391,7 +3401,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- icl_program_mg_dp_mode(dig_port);
+ icl_program_mg_dp_mode(dig_port, crtc_state);
icl_phy_set_clock_gating(dig_port, false);
if (INTEL_GEN(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index f923f9cbd33c..7773169b7331 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -67,6 +67,21 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
}
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 pin_mask;
+
+ pin_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
+
+ WARN_ON(pin_mask == 0xffffffff);
+
+ return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
+ DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
+}
+
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 783d75531435..463f1b3c836f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -13,6 +13,7 @@ struct intel_digital_port;
bool intel_tc_port_connected(struct intel_digital_port *dig_port);
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
+u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..bcf449c1d152 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11857,6 +11857,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
+#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
+#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
+#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
+#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
+
/* This register controls the Display State Buffer (DSB) engines. */
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH CI 2/4] drm/i915/tgl: Add dkl phy programming sequences
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
@ 2019-09-26 21:06 ` José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: José Roberto de Souza @ 2019-09-26 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clinton A Taylor <clinton.a.taylor@intel.com>
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the following trainings to fail
so not enabling it for.
v2:
Setting the right HIP_INDEX_REG bits (José)
v3:
Adding the meaning of each column of tgl_dkl_phy_ddi_translations
Adding if gen >= 12 on intel_ddi_hdmi_level() and
intel_ddi_pre_enable_hdmi() instead of reuse part of gen >= 11 if
v4:
Moved the DP_MODE lane programing to another patch as ICL also
needed it
Sharing icl_phy_set_clock_gating() and icl_program_mg_dp_mode() with
TGL as bits and programing as now it almost identical to ICL
BSpec: 49292
BSpec: 49190
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 174 ++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 8 --
2 files changed, 154 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 20393d39a29a..b463e51f8b45 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -586,6 +586,26 @@ static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
{ 0x0, 0x00, 0x00 }, /* 3 0 */
};
+struct tgl_dkl_phy_ddi_buf_trans {
+ u32 dkl_vswing_control;
+ u32 dkl_preshoot_control;
+ u32 dkl_de_emphasis_control;
+};
+
+static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
+ /* VS pre-emp Non-trans mV Pre-emph dB */
+ { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
+ { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */
+ { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */
+ { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
+ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
+ { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */
+ { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
+ { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
+ { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
+ { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
+};
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
@@ -872,7 +892,14 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ if (intel_phy_is_combo(dev_priv, phy))
+ icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+ 0, &n_entries);
+ else
+ n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+ default_entry = n_entries - 1;
+ } else if (INTEL_GEN(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
@@ -2334,7 +2361,13 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
enum phy phy = intel_port_to_phy(dev_priv, port);
int n_entries;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ if (intel_phy_is_combo(dev_priv, phy))
+ icl_get_combo_buf_trans(dev_priv, encoder->type,
+ intel_dp->link_rate, &n_entries);
+ else
+ n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+ } else if (INTEL_GEN(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
@@ -2776,6 +2809,62 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
}
+static void
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
+ u32 level)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
+ const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
+ u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
+
+ n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
+ ddi_translations = tgl_dkl_phy_ddi_translations;
+
+ if (level >= n_entries)
+ level = n_entries - 1;
+
+ dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
+ DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+ DKL_TX_VSWING_CONTROL_MASK);
+ dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
+ dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
+ dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
+
+ for (ln = 0; ln < 2; ln++) {
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
+
+ /* All the registers are RMW */
+ val = I915_READ(DKL_TX_DPCNTL0(tc_port));
+ val &= ~dpcnt_mask;
+ val |= dpcnt_val;
+ I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
+
+ val = I915_READ(DKL_TX_DPCNTL1(tc_port));
+ val &= ~dpcnt_mask;
+ val |= dpcnt_val;
+ I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
+
+ val = I915_READ(DKL_TX_DPCNTL2(tc_port));
+ val &= ~DKL_TX_DP20BITMODE;
+ I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
+ }
+}
+
+static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
+ int link_clock,
+ u32 level,
+ enum intel_output_type type)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (intel_phy_is_combo(dev_priv, phy))
+ icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+ else
+ tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
+}
+
static u32 translate_signal_level(int signal_levels)
{
int i;
@@ -2807,7 +2896,10 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &dport->base;
int level = intel_ddi_dp_level(intel_dp);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
+ level, encoder->type);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
level, encoder->type);
else if (IS_CANNONLAKE(dev_priv))
@@ -3071,24 +3163,39 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
MG_DP_MODE_CFG_GAONPWR_GATING;
for (ln = 0; ln < 2; ln++) {
- val = I915_READ(MG_DP_MODE(ln, port));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
+ val = I915_READ(DKL_DP_MODE(tc_port));
+ } else {
+ val = I915_READ(MG_DP_MODE(ln, port));
+ }
+
if (enable)
val |= bits;
else
val &= ~bits;
- I915_WRITE(MG_DP_MODE(ln, port), val);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(DKL_DP_MODE(tc_port), val);
+ else
+ I915_WRITE(MG_DP_MODE(ln, port), val);
}
- bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING |
- MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING |
- MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING;
+ if (INTEL_GEN(dev_priv) == 11) {
+ bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
+ MG_MISC_SUS0_CFG_CL2PWR_GATING |
+ MG_MISC_SUS0_CFG_GAONPWR_GATING |
+ MG_MISC_SUS0_CFG_TRPWR_GATING |
+ MG_MISC_SUS0_CFG_CL1PWR_GATING |
+ MG_MISC_SUS0_CFG_DGPWR_GATING;
- val = I915_READ(MG_MISC_SUS0(tc_port));
- if (enable)
- val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
- else
- val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
- I915_WRITE(MG_MISC_SUS0(tc_port), val);
+ val = I915_READ(MG_MISC_SUS0(tc_port));
+ if (enable)
+ val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
+ else
+ val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
+ I915_WRITE(MG_MISC_SUS0(tc_port), val);
+ }
}
static void
@@ -3097,14 +3204,22 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
{
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
u32 ln0, ln1, pin_assignment;
u8 width;
if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
return;
- ln0 = I915_READ(MG_DP_MODE(0, port));
- ln1 = I915_READ(MG_DP_MODE(1, port));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
+ ln0 = I915_READ(DKL_DP_MODE(tc_port));
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
+ ln1 = I915_READ(DKL_DP_MODE(tc_port));
+ } else {
+ ln0 = I915_READ(MG_DP_MODE(0, port));
+ ln1 = I915_READ(MG_DP_MODE(1, port));
+ }
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -3159,8 +3274,15 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
MISSING_CASE(pin_assignment);
}
- I915_WRITE(MG_DP_MODE(0, port), ln0);
- I915_WRITE(MG_DP_MODE(1, port), ln1);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
+ I915_WRITE(DKL_DP_MODE(tc_port), ln0);
+ I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
+ I915_WRITE(DKL_DP_MODE(tc_port), ln1);
+ } else {
+ I915_WRITE(MG_DP_MODE(0, port), ln0);
+ I915_WRITE(MG_DP_MODE(1, port), ln1);
+ }
}
static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
@@ -3265,7 +3387,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
icl_phy_set_clock_gating(dig_port, false);
/* 7.e */
- icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
+ tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
encoder->type);
/* 7.f */
@@ -3297,6 +3419,15 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
/* 7.k */
intel_dp_stop_link_train(intel_dp);
+ /*
+ * TODO: enable clock gating
+ *
+ * It is not written in DP enabling sequence but "PHY Clockgating
+ * programming" states that clock gating should be enabled after the
+ * link training but doing so causes all the following trainings to fail
+ * so not enabling it for now.
+ */
+
/* 7.l */
intel_ddi_enable_fec(encoder, crtc_state);
intel_dsc_enable(encoder, crtc_state);
@@ -3404,7 +3535,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
icl_program_mg_dp_mode(dig_port, crtc_state);
icl_phy_set_clock_gating(dig_port, false);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
+ level, INTEL_OUTPUT_HDMI);
+ else if (INTEL_GEN(dev_priv) == 11)
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
level, INTEL_OUTPUT_HDMI);
else if (IS_CANNONLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcf449c1d152..7f6b59aa6348 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10245,14 +10245,6 @@ enum skl_power_gate {
_DKL_TX_DW18)
#define _DKL_DP_MODE 0xA0
-#define DKL_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
-#define DKL_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
-#define DKL_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
-#define DKL_DP_MODE_CFG_TRPWR_GATING (1 << 4)
-#define DKL_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
-#define DKL_DP_MODE_CFG_GATING_CTRL_MASK (0x1f << 1)
-#define DKL_DP_MODE_CFG_DP_X1_MODE (1 << 6)
-#define DKL_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
_DKL_PHY2_BASE) + \
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH CI 3/4] drm/i915/tgl: Fix dkl link training
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
@ 2019-09-26 21:06 ` José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: José Roberto de Souza @ 2019-09-26 21:06 UTC (permalink / raw)
To: intel-gfx
Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.
Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
div2 value, that matches with dkl hardcoded table.
So implementing this way as it proved to work in HW and leaving a
comment so we know why it do not match BSpec.
v4:
Using the same is_dp check as ICL, need testing on HDMI over tc port
Issue reported on BSpec 49204.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 69abafa45ce9..be69a2344294 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2630,13 +2630,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
continue;
if (div2 >= 2) {
- if (is_dkl) {
- a_divratio = 5;
- tlinedrv = 1;
- } else {
- a_divratio = is_dp ? 10 : 5;
- tlinedrv = 2;
- }
+ /*
+ * Note: a_divratio not matching TGL BSpec
+ * algorithm but matching hardcoded values and
+ * working on HW for DP alt-mode at least
+ */
+ a_divratio = is_dp ? 10 : 5;
+ tlinedrv = is_dkl ? 1 : 2;
} else {
a_divratio = 5;
tlinedrv = 0;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH CI 4/4] drm/i915/tgl: initialize TC and TBT ports
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
@ 2019-09-26 21:06 ` José Roberto de Souza
2019-09-26 22:40 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming Patchwork
2019-09-27 17:24 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 7+ messages in thread
From: José Roberto de Souza @ 2019-09-26 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Now that TC support was added, initialize DDIs.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8f125f1624bd..bbe088b9d057 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15340,9 +15340,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
+ intel_ddi_init(dev_priv, PORT_F);
+ intel_ddi_init(dev_priv, PORT_G);
+ intel_ddi_init(dev_priv, PORT_H);
+ intel_ddi_init(dev_priv, PORT_I);
icl_dsi_init(dev_priv);
} else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
` (2 preceding siblings ...)
2019-09-26 21:06 ` [PATCH CI 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
@ 2019-09-26 22:40 ` Patchwork
2019-09-27 17:24 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-09-26 22:40 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
URL : https://patchwork.freedesktop.org/series/67312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966 -> Patchwork_14561
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/
Known issues
------------
Here are the changes found in Patchwork_14561 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/fi-icl-u3/igt@gem_mmap_gtt@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/fi-icl-u3/igt@gem_mmap_gtt@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] / [fdo#111214])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/fi-icl-u3/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/fi-icl-u3/igt@i915_module_load@reload.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/fi-icl-guc/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/fi-icl-guc/igt@gem_ctx_create@basic-files.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/fi-icl-u3/igt@gem_linear_blits@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/fi-icl-u3/igt@gem_linear_blits@basic.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [FAIL][10] ([fdo#111407])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 46)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6966 -> Patchwork_14561
CI-20190529: 20190529
CI_DRM_6966: 381f5de06837c7a432d0c614ca7f0ece033ce840 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14561: 6054eda706cc28ce9ff62b382a86d20e373d6b9b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6054eda706cc drm/i915/tgl: initialize TC and TBT ports
888018a8240b drm/i915/tgl: Fix dkl link training
233df550d795 drm/i915/tgl: Add dkl phy programming sequences
30672dbdffa9 drm/i915/tc: Update DP_MODE programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
` (3 preceding siblings ...)
2019-09-26 22:40 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming Patchwork
@ 2019-09-27 17:24 ` Patchwork
2019-09-27 17:50 ` Souza, Jose
4 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2019-09-27 17:24 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
URL : https://patchwork.freedesktop.org/series/67312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14561_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +16 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_tiled_wc:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb3/igt@gem_tiled_wc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@gem_tiled_wc.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@i915_suspend@sysfs-reader.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111764])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +11 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][25] ([fdo#110854]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb5/igt@gem_exec_balancer@smoke.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* {igt@i915_pm_dc@dc6-psr}:
- shard-iclb: [FAIL][31] ([fdo#110548]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl1/igt@i915_suspend@forcewake.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-kbl3/igt@i915_suspend@forcewake.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-kbl: [FAIL][35] ([fdo#105363]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-iclb: [FAIL][37] ([fdo#108134]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_flip_tiling@flip-to-x-tiled.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][41] ([fdo#109642] / [fdo#111068]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@perf@polling.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@perf@polling.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][47] ([fdo#111329]) -> [SKIP][48] ([fdo#109276])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [FAIL][49] ([fdo#111330]) -> [SKIP][50] ([fdo#109276])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][51] ([fdo#110321] / [fdo#110336]) -> [INCOMPLETE][52] ([fdo#103927])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@kms_content_protection@atomic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@kms_content_protection@atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
Participating hosts (16 -> 10)
------------------------------
Missing (6): shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6966 -> Patchwork_14561
CI-20190529: 20190529
CI_DRM_6966: 381f5de06837c7a432d0c614ca7f0ece033ce840 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14561: 6054eda706cc28ce9ff62b382a86d20e373d6b9b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
2019-09-27 17:24 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-09-27 17:50 ` Souza, Jose
0 siblings, 0 replies; 7+ messages in thread
From: Souza, Jose @ 2019-09-27 17:50 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org
On Fri, 2019-09-27 at 17:24 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE
> programming
> URL : https://patchwork.freedesktop.org/series/67312/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed to dinq, thanks for the reviews Imre and Lucas.
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_14561_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +16
> similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_schedule@promotion-bsd1.html
>
> * igt@gem_exec_schedule@reorder-wide-bsd:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4
> similar issues
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
>
> * igt@gem_tiled_wc:
> - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
> +1 similar issue
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb3/igt@gem_tiled_wc.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@gem_tiled_wc.html
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]
> / [fdo#107807])
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
>
> * igt@i915_suspend@sysfs-reader:
> - shard-apl: [PASS][9] -> [DMESG-WARN][10]
> ([fdo#108566]) +5 similar issues
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@i915_suspend@sysfs-reader.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@i915_suspend@sysfs-reader.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
> - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4
> similar issues
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_psr@psr2_sprite_mmap_gtt:
> - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2
> similar issues
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-apl: [PASS][17] -> [INCOMPLETE][18]
> ([fdo#103927]) +3 similar issues
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> - shard-skl: [PASS][19] -> [INCOMPLETE][20]
> ([fdo#104108])
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
>
> * igt@kms_vblank@pipe-c-ts-continuation-suspend:
> - shard-iclb: [PASS][21] -> [DMESG-WARN][22]
> ([fdo#111764])
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_isolation@vcs1-dirty-create:
> - shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +11
> similar issues
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [SKIP][25] ([fdo#110854]) -> [PASS][26]
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb5/igt@gem_exec_balancer@smoke.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@gem_exec_balancer@smoke.html
>
> * igt@gem_exec_schedule@preempt-other-chain-bsd:
> - shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +8
> similar issues
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-apl: [DMESG-WARN][29] ([fdo#108566]) ->
> [PASS][30] +5 similar issues
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
>
> * {igt@i915_pm_dc@dc6-psr}:
> - shard-iclb: [FAIL][31] ([fdo#110548]) -> [PASS][32]
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
>
> * igt@i915_suspend@forcewake:
> - shard-kbl: [DMESG-WARN][33] ([fdo#108566]) ->
> [PASS][34]
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl1/igt@i915_suspend@forcewake.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-kbl3/igt@i915_suspend@forcewake.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-kbl: [FAIL][35] ([fdo#105363]) -> [PASS][36]
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip_tiling@flip-to-x-tiled:
> - shard-iclb: [FAIL][37] ([fdo#108134]) -> [PASS][38]
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_flip_tiling@flip-to-x-tiled.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_flip_tiling@flip-to-x-tiled.html
>
> * igt@kms
> _frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
> - shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +3
> similar issues
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
>
> * igt@kms_psr2_su@frontbuffer:
> - shard-iclb: [SKIP][41] ([fdo#109642] / [fdo#111068]) ->
> [PASS][42]
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
>
> * igt@kms_psr@psr2_cursor_mmap_cpu:
> - shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2
> similar issues
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
>
> * igt@perf@polling:
> - shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@perf@polling.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@perf@polling.html
>
>
> #### Warnings ####
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [FAIL][47] ([fdo#111329]) -> [SKIP][48]
> ([fdo#109276])
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
>
> * igt@gem_mocs_settings@mocs-isolation-bsd2:
> - shard-iclb: [FAIL][49] ([fdo#111330]) -> [SKIP][50]
> ([fdo#109276])
> [49]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html
>
> * igt@kms_content_protection@atomic:
> - shard-apl: [FAIL][51] ([fdo#110321] / [fdo#110336]) ->
> [INCOMPLETE][52] ([fdo#103927])
> [51]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@kms_content_protection@atomic.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@kms_content_protection@atomic.html
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or
> FAILURE).
>
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
> [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
> [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
> [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
> [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
> [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
>
>
> Participating hosts (16 -> 10)
> ------------------------------
>
> Missing (6): shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4
> shard-tglb5 shard-tglb6
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6966 -> Patchwork_14561
>
> CI-20190529: 20190529
> CI_DRM_6966: 381f5de06837c7a432d0c614ca7f0ece033ce840 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14561: 6054eda706cc28ce9ff62b382a86d20e373d6b9b @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-09-27 17:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-09-26 21:06 [PATCH CI 1/4] drm/i915/tc: Update DP_MODE programming José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 2/4] drm/i915/tgl: Add dkl phy programming sequences José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 3/4] drm/i915/tgl: Fix dkl link training José Roberto de Souza
2019-09-26 21:06 ` [PATCH CI 4/4] drm/i915/tgl: initialize TC and TBT ports José Roberto de Souza
2019-09-26 22:40 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming Patchwork
2019-09-27 17:24 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-27 17:50 ` Souza, Jose
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