From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: invalidate render cache on gen2
Date: Thu, 19 Apr 2012 15:47:44 +0100 [thread overview]
Message-ID: <1334846886_26427@CP5-2952> (raw)
In-Reply-To: <1334846722-1161-1-git-send-email-daniel.vetter@ffwll.ch>
On Thu, 19 Apr 2012 16:45:22 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> It looks like we also need to flush the render cache when we just
> invalidate it. This fixes a regression in i-g-t/gem_tiled_blits on my
> i855gm. I guess the render cache there is virtually indexed, so we
> need to clean it when changing gtt mappings.
>
> This regression has been introduce in
>
> commit 46f0f8d120c4afae53a5670bf3ac80a928340ff3
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Wed Apr 18 11:12:11 2012 +0100
>
> drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
My fault, with hindsight comes wisdom,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-04-19 14:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-19 14:45 [PATCH] drm/i915: invalidate render cache on gen2 Daniel Vetter
2012-04-19 14:47 ` Chris Wilson [this message]
2012-04-19 15:13 ` Daniel Vetter
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