From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: use the new masked bit macro some more
Date: Thu, 26 Apr 2012 20:40:21 +0100 [thread overview]
Message-ID: <1335469258_60890@CP5-2952> (raw)
In-Reply-To: <1335468782-19796-1-git-send-email-daniel.vetter@ffwll.ch>
On Thu, 26 Apr 2012 21:33:02 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> if (IS_GEN3(dev)) {
> - u32 tmp = I915_READ(MI_ARB_STATE);
> - if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
> - /* arb state is a masked write, so set bit + bit in mask */
> - tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
> + if (!(I915_READ(MI_ARB_STATE) & MI_ARB_C3_LP_WRITE_ENABLE)) {
> + u32 tmp = _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE);
> I915_WRITE(MI_ARB_STATE, tmp);
Just write the masked bit, the state before is irrelevant.
I can't spot any other shifts that look to be being used as a mask, so
whatever the outcome of the above bikeshedding:
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-04-26 19:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-26 16:24 [PATCH] drm/i915: use the new masked bit macro some more Daniel Vetter
2012-04-26 18:50 ` Chris Wilson
2012-04-26 19:33 ` Daniel Vetter
2012-04-26 19:40 ` Chris Wilson [this message]
2012-04-26 20:02 ` Daniel Vetter
2012-04-27 9:30 ` Daniel Vetter
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