From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: [PATCH 01/25] drm/i915: CXT_SIZE register offsets added
Date: Mon, 4 Jun 2012 14:42:41 -0700 [thread overview]
Message-ID: <1338846185-10571-2-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1338846185-10571-1-git-send-email-ben@bwidawsk.net>
From: Ben Widawsky <bwidawsk@gmail.com>
The GPUs can have different default context layouts, and the sizes could
vary based on platform or BIOS. In order to back the context object with
a properly sized BO, we must read this register in order to find out a
sufficient size.
Thankfully (sarcarm!), the register moves and changes meanings
throughout generations.
CTX and CXT differences are intentional as that is how it is in the
documentation (prior to GEN6 it was CXT).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f45a18..66ed7e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1454,6 +1454,27 @@
*/
#define CCID 0x2180
#define CCID_EN (1<<0)
+#define CXT_SIZE 0x21a0
+#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
+#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
+#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
+#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
+#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
+#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
+ GEN6_CXT_RING_SIZE(cxt_reg) + \
+ GEN6_CXT_RENDER_SIZE(cxt_reg) + \
+ GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
+ GEN6_CXT_PIPELINE_SIZE(cxt_reg))
+#define GEN7_CTX_SIZE 0x21a8
+#define GEN7_CTX_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
+#define GEN7_CTX_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
+#define GEN7_CTX_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
+#define GEN7_CTX_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
+#define GEN7_CTX_TOTAL_SIZE(ctx_reg) (GEN7_CTX_RENDER_SIZE(ctx_reg) + \
+ GEN7_CTX_EXTENDED_SIZE(ctx_reg) + \
+ GEN7_CTX_GT1_SIZE(ctx_reg) + \
+ GEN7_CTX_VFSTATE_SIZE(ctx_reg))
+
/*
* Overlay regs
*/
--
1.7.10.2
next prev parent reply other threads:[~2012-06-04 21:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-04 21:42 [PATCH 00/25] i915 HW context support Ben Widawsky
2012-06-04 21:42 ` Ben Widawsky [this message]
2012-06-04 21:42 ` [PATCH 02/25 v2] drm/i915: preliminary " Ben Widawsky
2012-06-05 12:23 ` Ville Syrjälä
2012-06-05 16:30 ` Ben Widawsky
2012-06-04 21:42 ` [PATCH 03/25 v2] drm/i915: context basic create & destroy Ben Widawsky
2012-06-13 23:27 ` Ben Widawsky
2012-06-04 21:42 ` [PATCH 04/25] drm/i915: add context information to objects Ben Widawsky
2012-06-13 22:01 ` Daniel Vetter
2012-06-13 23:26 ` Ben Widawsky
2012-06-04 21:42 ` [PATCH 05/25] drm/i915: always bind context objects immediately Ben Widawsky
2012-06-04 21:42 ` [PATCH 06/25 v3] drm/i915: context switch implementation Ben Widawsky
2012-06-04 21:42 ` [PATCH 07/25] drm/i915: context trace events Ben Widawsky
2012-06-13 22:23 ` Daniel Vetter
2012-06-13 23:27 ` Ben Widawsky
2012-06-04 21:42 ` [PATCH 08/25] drm/i915: Ivybridge MI_ARB_ON_OFF context w/a Ben Widawsky
2012-06-04 21:42 ` [PATCH 09/25] drm/i915: PIPE_CONTROL_TLB_INVALIDATE Ben Widawsky
2012-06-04 21:42 ` [PATCH 10/25 v2] drm/i915: possibly invalidate TLB before context switch Ben Widawsky
2012-06-04 21:42 ` [PATCH 11/25] drm/i915: use the default context Ben Widawsky
2012-06-04 21:42 ` [PATCH 12/25] drm/i915: add ccid to error state Ben Widawsky
2012-06-04 21:42 ` [PATCH 13/25 v3] drm/i915: switch to default context on idle Ben Widawsky
2012-06-04 21:42 ` [PATCH 14/25 v3] drm/i915/context: create & destroy ioctls Ben Widawsky
2012-06-04 21:42 ` [PATCH 15/25 v2] drm/i915/context: switch contexts with execbuf2 Ben Widawsky
2012-06-04 21:42 ` [PATCH 16/25] drm/i915: reset the GPU on context fini Ben Widawsky
2012-06-04 21:42 ` [PATCH 17/25] intel: wait render placeholder Ben Widawsky
2012-06-04 21:42 ` [PATCH 18/25] intel: Merge updated kernel header Ben Widawsky
2012-06-04 21:42 ` [PATCH 19/25] intel/context: Add drm_intel_context type Ben Widawsky
2012-06-04 21:43 ` [PATCH 20/25] intel/context: new execbuf interface for contexts Ben Widawsky
2012-06-04 21:43 ` [PATCH 21/25] intel: add decoding of MI_SET_CONTEXT Ben Widawsky
2012-06-04 21:43 ` [PATCH 22/25] context: libdrm wrappers Ben Widawsky
2012-06-04 21:43 ` [PATCH 23/25] context: update for new execbuf2 element Ben Widawsky
2012-06-04 21:43 ` [PATCH 24/25] contexts: basic test coverage Ben Widawsky
2012-06-13 23:30 ` Daniel Vetter
2012-06-14 3:13 ` [PATCH] " Ben Widawsky
2012-06-04 21:43 ` [PATCH 25/25] i965: hw context support Ben Widawsky
2012-06-04 23:01 ` Paul Berry
2012-06-04 23:10 ` [Intel-gfx] " Ben Widawsky
2012-06-05 5:53 ` [PATCH 00/25] i915 HW " Dave Airlie
2012-06-05 7:08 ` [Mesa-dev] " Kenneth Graunke
2012-06-05 16:32 ` Ben Widawsky
2012-06-05 23:37 ` Kenneth Graunke
2012-06-07 16:17 ` Ben Widawsky
2012-06-14 16:04 ` Daniel Vetter
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