From: Keith Packard <keithp@keithp.com>
To: intel-gfx@lists.freedesktop.org, Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX
Date: Mon, 13 Aug 2012 21:34:50 -0700 [thread overview]
Message-ID: <1344918891-6283-7-git-send-email-keithp@keithp.com> (raw)
In-Reply-To: <1344918891-6283-1-git-send-email-keithp@keithp.com>
Doesn't make sense to disable in the other order.
Signed-off-by: Keith Packard <keithp@keithp.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b099a17..754f10f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2776,17 +2776,17 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
u32 reg, temp;
/* disable CPU FDI tx and PCH FDI rx */
- reg = FDI_TX_CTL(pipe);
- temp = I915_READ(reg);
- I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
- POSTING_READ(reg);
-
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
temp &= ~(0x7 << 16);
temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+ POSTING_READ(reg);
+ udelay(100);
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
POSTING_READ(reg);
udelay(100);
--
1.7.10.4
next prev parent reply other threads:[~2012-08-14 4:34 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 4:34 [PATCH 0/7] drm/i915: IVB FDI B/C fixes and misc cleanups Keith Packard
2012-08-14 4:34 ` [PATCH 1/7] drm/i915: Allow VGA on CRTC 2 Keith Packard
2012-08-15 22:42 ` Daniel Vetter
2012-08-14 4:34 ` [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge Keith Packard
2012-08-17 14:45 ` [Intel-gfx] " Lespiau, Damien
2012-08-17 15:00 ` Keith Packard
2012-08-17 15:12 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 3/7] drm/i915: Delay between FDI link training tries. Clear FDI_RX_IIR before training Keith Packard
2012-08-17 15:34 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 4/7] drm/i915: Check display_bpc against max_fdi_bpp after display_bpc is set Keith Packard
2012-08-17 14:58 ` Lespiau, Damien
2012-08-14 4:34 ` [PATCH 5/7] drm/i915: Pipe-C only configurations would not get SR Keith Packard
2012-08-17 15:50 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` Keith Packard [this message]
2012-08-17 16:43 ` [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX Lespiau, Damien
2012-08-17 23:10 ` [Intel-gfx] " Keith Packard
2012-08-14 4:34 ` [PATCH 7/7] drm/i915: Merge FDI RX reg writes during training Keith Packard
2012-08-17 17:14 ` [Intel-gfx] " Lespiau, Damien
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