From: Keith Packard <keithp@keithp.com>
To: "Lespiau, Damien" <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX
Date: Fri, 17 Aug 2012 16:10:57 -0700 [thread overview]
Message-ID: <86393lunb2.fsf@miki.keithp.com> (raw)
In-Reply-To: <CAPX-8+_bZNyXL0b8nBkN97sj-KnT_eZXZ-5Hp5R6P-L-D-QAKg@mail.gmail.com>
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"Lespiau, Damien" <damien.lespiau@intel.com> writes:
> I can't see anything in the docs about an order requirement for those.
Right, the docs don't say anything, which is a bit disconcerting.
> Not sure why the other way does not make sense. Somehow disabling TX
> before RX makes some sense to me (TX enabled without a ready RX looks
> weird?, no data should flow as the pipe is shutdown at that point
> anyway). Maybe it just does not matter?
And here I figured disabling RX before TX made more sense -- otherwise
the receiver wouldn't be seeing anything. In other areas of the driver,
we're careful to disable receivers before senders (disable CRTC before
PLL, etc).
> Another detail is that disabling the PLLs seem to have an order in the
> disabling sequence, TX, then RX.
>
> I. Disable CPU FDI Transmitter PLL
> II. Disable PCH FDI Receiver PLL
That ordering doesn't matter as the FDI receiver and transmitter are
both disabled by that point, so they aren't talking at all.
--
keith.packard@intel.com
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next prev parent reply other threads:[~2012-08-17 23:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 4:34 [PATCH 0/7] drm/i915: IVB FDI B/C fixes and misc cleanups Keith Packard
2012-08-14 4:34 ` [PATCH 1/7] drm/i915: Allow VGA on CRTC 2 Keith Packard
2012-08-15 22:42 ` Daniel Vetter
2012-08-14 4:34 ` [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge Keith Packard
2012-08-17 14:45 ` [Intel-gfx] " Lespiau, Damien
2012-08-17 15:00 ` Keith Packard
2012-08-17 15:12 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 3/7] drm/i915: Delay between FDI link training tries. Clear FDI_RX_IIR before training Keith Packard
2012-08-17 15:34 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 4/7] drm/i915: Check display_bpc against max_fdi_bpp after display_bpc is set Keith Packard
2012-08-17 14:58 ` Lespiau, Damien
2012-08-14 4:34 ` [PATCH 5/7] drm/i915: Pipe-C only configurations would not get SR Keith Packard
2012-08-17 15:50 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX Keith Packard
2012-08-17 16:43 ` Lespiau, Damien
2012-08-17 23:10 ` Keith Packard [this message]
2012-08-14 4:34 ` [PATCH 7/7] drm/i915: Merge FDI RX reg writes during training Keith Packard
2012-08-17 17:14 ` [Intel-gfx] " Lespiau, Damien
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