* [PATCH] drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware
@ 2012-12-04 14:36 Jani Nikula
2012-12-04 17:25 ` Paulo Zanoni
0 siblings, 1 reply; 3+ messages in thread
From: Jani Nikula @ 2012-12-04 14:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The BLC_PWM_CTL2 register does not exist before gen4. While at it, do a
slight drive by cleanup of the code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_panel.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c758ad2..bee8cb6 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -130,8 +130,9 @@ static int is_backlight_combination_mode(struct drm_device *dev)
return 0;
}
-static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
+static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
u32 val;
/* Restore the CTL value if it lost, e.g. GPU reset */
@@ -141,21 +142,22 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
dev_priv->regfile.saveBLC_PWM_CTL2 = val;
} else if (val == 0) {
- I915_WRITE(BLC_PWM_PCH_CTL2,
- dev_priv->regfile.saveBLC_PWM_CTL2);
val = dev_priv->regfile.saveBLC_PWM_CTL2;
+ I915_WRITE(BLC_PWM_PCH_CTL2, val);
}
} else {
val = I915_READ(BLC_PWM_CTL);
if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
dev_priv->regfile.saveBLC_PWM_CTL = val;
- dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
+ if (INTEL_INFO(dev)->gen >= 4)
+ dev_priv->regfile.saveBLC_PWM_CTL2 =
+ I915_READ(BLC_PWM_CTL2);
} else if (val == 0) {
- I915_WRITE(BLC_PWM_CTL,
- dev_priv->regfile.saveBLC_PWM_CTL);
- I915_WRITE(BLC_PWM_CTL2,
- dev_priv->regfile.saveBLC_PWM_CTL2);
val = dev_priv->regfile.saveBLC_PWM_CTL;
+ I915_WRITE(BLC_PWM_CTL, val);
+ if (INTEL_INFO(dev)->gen >= 4)
+ I915_WRITE(BLC_PWM_CTL2,
+ dev_priv->regfile.saveBLC_PWM_CTL2);
}
}
@@ -164,10 +166,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
static u32 _intel_panel_get_max_backlight(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
u32 max;
- max = i915_read_blc_pwm_ctl(dev_priv);
+ max = i915_read_blc_pwm_ctl(dev);
if (HAS_PCH_SPLIT(dev)) {
max >>= 16;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware
2012-12-04 14:36 [PATCH] drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware Jani Nikula
@ 2012-12-04 17:25 ` Paulo Zanoni
2012-12-04 21:42 ` Daniel Vetter
0 siblings, 1 reply; 3+ messages in thread
From: Paulo Zanoni @ 2012-12-04 17:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
Hi
2012/12/4 Jani Nikula <jani.nikula@intel.com>:
> The BLC_PWM_CTL2 register does not exist before gen4. While at it, do a
> slight drive by cleanup of the code.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_panel.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index c758ad2..bee8cb6 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -130,8 +130,9 @@ static int is_backlight_combination_mode(struct drm_device *dev)
> return 0;
> }
>
> -static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
> +static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> u32 val;
>
> /* Restore the CTL value if it lost, e.g. GPU reset */
> @@ -141,21 +142,22 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
> if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
> dev_priv->regfile.saveBLC_PWM_CTL2 = val;
> } else if (val == 0) {
> - I915_WRITE(BLC_PWM_PCH_CTL2,
> - dev_priv->regfile.saveBLC_PWM_CTL2);
> val = dev_priv->regfile.saveBLC_PWM_CTL2;
> + I915_WRITE(BLC_PWM_PCH_CTL2, val);
> }
> } else {
> val = I915_READ(BLC_PWM_CTL);
> if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
> dev_priv->regfile.saveBLC_PWM_CTL = val;
> - dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
> + if (INTEL_INFO(dev)->gen >= 4)
> + dev_priv->regfile.saveBLC_PWM_CTL2 =
> + I915_READ(BLC_PWM_CTL2);
> } else if (val == 0) {
> - I915_WRITE(BLC_PWM_CTL,
> - dev_priv->regfile.saveBLC_PWM_CTL);
> - I915_WRITE(BLC_PWM_CTL2,
> - dev_priv->regfile.saveBLC_PWM_CTL2);
> val = dev_priv->regfile.saveBLC_PWM_CTL;
> + I915_WRITE(BLC_PWM_CTL, val);
> + if (INTEL_INFO(dev)->gen >= 4)
> + I915_WRITE(BLC_PWM_CTL2,
> + dev_priv->regfile.saveBLC_PWM_CTL2);
> }
> }
>
> @@ -164,10 +166,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
>
> static u32 _intel_panel_get_max_backlight(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> u32 max;
>
> - max = i915_read_blc_pwm_ctl(dev_priv);
> + max = i915_read_blc_pwm_ctl(dev);
>
> if (HAS_PCH_SPLIT(dev)) {
> max >>= 16;
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware
2012-12-04 17:25 ` Paulo Zanoni
@ 2012-12-04 21:42 ` Daniel Vetter
0 siblings, 0 replies; 3+ messages in thread
From: Daniel Vetter @ 2012-12-04 21:42 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Jani Nikula, intel-gfx
On Tue, Dec 04, 2012 at 03:25:48PM -0200, Paulo Zanoni wrote:
> Hi
>
> 2012/12/4 Jani Nikula <jani.nikula@intel.com>:
> > The BLC_PWM_CTL2 register does not exist before gen4. While at it, do a
> > slight drive by cleanup of the code.
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Picked up for -fixes, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-12-04 21:41 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2012-12-04 14:36 [PATCH] drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware Jani Nikula
2012-12-04 17:25 ` Paulo Zanoni
2012-12-04 21:42 ` Daniel Vetter
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