* [PATCH 1/2] drm/i915: Print the pipe control page GTT address @ 2013-02-12 20:01 ville.syrjala 2013-02-12 20:01 ` [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala 2013-02-12 20:56 ` [PATCH 1/2] drm/i915: Print the pipe control page GTT address Daniel Vetter 0 siblings, 2 replies; 4+ messages in thread From: ville.syrjala @ 2013-02-12 20:01 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> We already print the HWS addresses during init, so do the same for the pipe control page. Reduces guesswork when looking at hex addresses later. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 00525ff..9b8b058 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -467,6 +467,9 @@ init_pipe_control(struct intel_ring_buffer *ring) if (pc->cpu_page == NULL) goto err_unpin; + DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", + ring->name, pc->gtt_offset); + pc->obj = obj; ring->private = pc; return 0; -- 1.7.12.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ 2013-02-12 20:01 [PATCH 1/2] drm/i915: Print the pipe control page GTT address ville.syrjala @ 2013-02-12 20:01 ` ville.syrjala 2013-02-13 0:53 ` Ben Widawsky 2013-02-12 20:56 ` [PATCH 1/2] drm/i915: Print the pipe control page GTT address Daniel Vetter 1 sibling, 1 reply; 4+ messages in thread From: ville.syrjala @ 2013-02-12 20:01 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The bit controlling whether PIPE_CONTROL DW/QW write targets the global GTT or PPGTT moved moved from DW 2 bit 2 to DW 1 bit 24 on IVB. TODO: need to test on IVB actually and make sure things don't explode. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7542cd..69a95c6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -308,6 +308,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) +#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ #define PIPE_CONTROL_CS_STALL (1<<20) #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) #define PIPE_CONTROL_QW_WRITE (1<<14) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9b8b058..f397bd7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -330,8 +330,8 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, return ret; intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); - intel_ring_emit(ring, flags); - intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, flags | PIPE_CONTROL_GLOBAL_GTT_IVB); + intel_ring_emit(ring, scratch_addr); intel_ring_emit(ring, 0); intel_ring_advance(ring); -- 1.7.12.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ 2013-02-12 20:01 ` [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala @ 2013-02-13 0:53 ` Ben Widawsky 0 siblings, 0 replies; 4+ messages in thread From: Ben Widawsky @ 2013-02-13 0:53 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, Feb 12, 2013 at 10:01:39PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The bit controlling whether PIPE_CONTROL DW/QW write targets > the global GTT or PPGTT moved moved from DW 2 bit 2 to > DW 1 bit 24 on IVB. > > TODO: need to test on IVB actually and make sure things don't > explode. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d7542cd..69a95c6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -308,6 +308,7 @@ > #define DISPLAY_PLANE_A (0<<20) > #define DISPLAY_PLANE_B (1<<20) > #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) > +#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ > #define PIPE_CONTROL_CS_STALL (1<<20) > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) > #define PIPE_CONTROL_QW_WRITE (1<<14) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 9b8b058..f397bd7 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -330,8 +330,8 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, > return ret; > > intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > - intel_ring_emit(ring, flags); > - intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); > + intel_ring_emit(ring, flags | PIPE_CONTROL_GLOBAL_GTT_IVB); > + intel_ring_emit(ring, scratch_addr); > intel_ring_emit(ring, 0); > intel_ring_advance(ring); > In the fashion of my favorite maintainer... bikeshed! Can you move the PIPE_CONTROL_GLOBAL_GTT_IVB up to where we set CS_STALL (or really anywhere else). That way we have a consistent way of setting flags, ie. dword2 -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/i915: Print the pipe control page GTT address 2013-02-12 20:01 [PATCH 1/2] drm/i915: Print the pipe control page GTT address ville.syrjala 2013-02-12 20:01 ` [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala @ 2013-02-12 20:56 ` Daniel Vetter 1 sibling, 0 replies; 4+ messages in thread From: Daniel Vetter @ 2013-02-12 20:56 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, Feb 12, 2013 at 10:01:38PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We already print the HWS addresses during init, so do the same for the > pipe control page. Reduces guesswork when looking at hex addresses > later. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Queued for -next, thanks for the patch. I'll hold off on patch 2 until the report from the bomb squad is in ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-02-13 0:52 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-02-12 20:01 [PATCH 1/2] drm/i915: Print the pipe control page GTT address ville.syrjala 2013-02-12 20:01 ` [PATCH 2/2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala 2013-02-13 0:53 ` Ben Widawsky 2013-02-12 20:56 ` [PATCH 1/2] drm/i915: Print the pipe control page GTT address Daniel Vetter
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