* [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT
@ 2013-04-08 18:48 Paulo Zanoni
2013-04-08 18:48 ` [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2 Paulo Zanoni
2013-04-08 21:30 ` [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
0 siblings, 2 replies; 5+ messages in thread
From: Paulo Zanoni @ 2013-04-08 18:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, stable
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Check the VBT to see if the machine has inverted FDI RX polarity on
CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2
registers.
This should fix some machines that were showing black screens on all
outputs.
Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_bios.c | 6 ++++--
drivers/gpu/drm/i915/intel_bios.h | 4 +++-
drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
5 files changed, 16 insertions(+), 6 deletions(-)
This is *not* the patch tested by the bug reporters, but I believe this is
equivalent. I'm also posting this patch on bugzilla right now, so we'll get test
reports for this one too.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69ddfd1..98c095c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -964,6 +964,7 @@ typedef struct drm_i915_private {
unsigned int int_crt_support:1;
unsigned int lvds_use_ssc:1;
unsigned int display_clock_mode:1;
+ unsigned int fdi_rx_polarity_inverted:1;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e4b7fb..759b1b8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3950,7 +3950,7 @@
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
-
+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 194df27..95070b2 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -351,12 +351,14 @@ parse_general_features(struct drm_i915_private *dev_priv,
dev_priv->lvds_ssc_freq =
intel_bios_ssc_frequency(dev, general->ssc_freq);
dev_priv->display_clock_mode = general->display_clock_mode;
- DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n",
+ dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
+ DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
dev_priv->int_tv_support,
dev_priv->int_crt_support,
dev_priv->lvds_use_ssc,
dev_priv->lvds_ssc_freq,
- dev_priv->display_clock_mode);
+ dev_priv->display_clock_mode,
+ dev_priv->fdi_rx_polarity_inverted);
}
}
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 36e57f9..e088d6f 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -127,7 +127,9 @@ struct bdb_general_features {
/* bits 3 */
u8 disable_smooth_vision:1;
u8 single_dvi:1;
- u8 rsvd9:6; /* finish byte */
+ u8 rsvd9:1;
+ u8 fdi_rx_polarity_inverted:1;
+ u8 rsvd10:4; /* finish byte */
/* bits 4 */
u8 legacy_monitor_detect;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17f157a..ce3d892 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3575,6 +3575,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
+ uint32_t val;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -3587,8 +3588,12 @@ static void cpt_init_clock_gating(struct drm_device *dev)
/* The below fixes the weird display corruption, a few pixels shifted
* downward, on (only) LVDS of some HP laptops with IVY.
*/
- for_each_pipe(pipe)
- I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
+ for_each_pipe(pipe) {
+ val = TRANS_CHICKEN2_TIMING_OVERRIDE;
+ if (dev_priv->fdi_rx_polarity_inverted)
+ val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+ I915_WRITE(TRANS_CHICKEN2(pipe), val);
+ }
/* WADP0ClockGatingDisable */
for_each_pipe(pipe) {
I915_WRITE(TRANS_CHICKEN1(pipe),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2
2013-04-08 18:48 [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
@ 2013-04-08 18:48 ` Paulo Zanoni
2013-04-10 15:23 ` Imre Deak
2013-04-08 21:30 ` [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
1 sibling, 1 reply; 5+ messages in thread
From: Paulo Zanoni @ 2013-04-08 18:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits
are being zeroed, but I couldn't find a reason for this, so leave them
as they are for now to avoid regressions.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 759b1b8..f4d6673 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3949,8 +3949,12 @@
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
-#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
+#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
+#define TRANS_CHICKEN2_PBC (1<<30 | 0x1ffffff)
#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ce3d892..e4ead41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3589,9 +3589,14 @@ static void cpt_init_clock_gating(struct drm_device *dev)
* downward, on (only) LVDS of some HP laptops with IVY.
*/
for_each_pipe(pipe) {
- val = TRANS_CHICKEN2_TIMING_OVERRIDE;
+ val = I915_READ(TRANS_CHICKEN2(pipe));
+ val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
if (dev_priv->fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
+ val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
I915_WRITE(TRANS_CHICKEN2(pipe), val);
}
/* WADP0ClockGatingDisable */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT
2013-04-08 18:48 [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
2013-04-08 18:48 ` [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2 Paulo Zanoni
@ 2013-04-08 21:30 ` Paulo Zanoni
1 sibling, 0 replies; 5+ messages in thread
From: Paulo Zanoni @ 2013-04-08 21:30 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Paulo Zanoni, stable
Hi
2013/4/8 Paulo Zanoni <przanoni@gmail.com>:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Check the VBT to see if the machine has inverted FDI RX polarity on
> CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2
> registers.
>
> This should fix some machines that were showing black screens on all
> outputs.
>
> Cc: stable@vger.kernel.org
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_bios.c | 6 ++++--
> drivers/gpu/drm/i915/intel_bios.h | 4 +++-
> drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
> 5 files changed, 16 insertions(+), 6 deletions(-)
>
>
> This is *not* the patch tested by the bug reporters, but I believe this is
> equivalent. I'm also posting this patch on bugzilla right now, so we'll get test
> reports for this one too.
We already have some reporters saying that the new patch works for them too :)
>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69ddfd1..98c095c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -964,6 +964,7 @@ typedef struct drm_i915_private {
> unsigned int int_crt_support:1;
> unsigned int lvds_use_ssc:1;
> unsigned int display_clock_mode:1;
> + unsigned int fdi_rx_polarity_inverted:1;
> int lvds_ssc_freq;
> unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
> struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0e4b7fb..759b1b8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3950,7 +3950,7 @@
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> -
> +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
>
> #define SOUTH_CHICKEN1 0xc2000
> #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 194df27..95070b2 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -351,12 +351,14 @@ parse_general_features(struct drm_i915_private *dev_priv,
> dev_priv->lvds_ssc_freq =
> intel_bios_ssc_frequency(dev, general->ssc_freq);
> dev_priv->display_clock_mode = general->display_clock_mode;
> - DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n",
> + dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
> + DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
> dev_priv->int_tv_support,
> dev_priv->int_crt_support,
> dev_priv->lvds_use_ssc,
> dev_priv->lvds_ssc_freq,
> - dev_priv->display_clock_mode);
> + dev_priv->display_clock_mode,
> + dev_priv->fdi_rx_polarity_inverted);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index 36e57f9..e088d6f 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -127,7 +127,9 @@ struct bdb_general_features {
> /* bits 3 */
> u8 disable_smooth_vision:1;
> u8 single_dvi:1;
> - u8 rsvd9:6; /* finish byte */
> + u8 rsvd9:1;
> + u8 fdi_rx_polarity_inverted:1;
> + u8 rsvd10:4; /* finish byte */
>
> /* bits 4 */
> u8 legacy_monitor_detect;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 17f157a..ce3d892 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3575,6 +3575,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> + uint32_t val;
>
> /*
> * On Ibex Peak and Cougar Point, we need to disable clock
> @@ -3587,8 +3588,12 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> /* The below fixes the weird display corruption, a few pixels shifted
> * downward, on (only) LVDS of some HP laptops with IVY.
> */
> - for_each_pipe(pipe)
> - I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
> + for_each_pipe(pipe) {
> + val = TRANS_CHICKEN2_TIMING_OVERRIDE;
> + if (dev_priv->fdi_rx_polarity_inverted)
> + val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> + I915_WRITE(TRANS_CHICKEN2(pipe), val);
> + }
> /* WADP0ClockGatingDisable */
> for_each_pipe(pipe) {
> I915_WRITE(TRANS_CHICKEN1(pipe),
> --
> 1.7.10.4
>
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2
2013-04-08 18:48 ` [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2 Paulo Zanoni
@ 2013-04-10 15:23 ` Imre Deak
2013-04-16 18:10 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Imre Deak @ 2013-04-10 15:23 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Mon, 2013-04-08 at 15:48 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits
> are being zeroed, but I couldn't find a reason for this, so leave them
> as they are for now to avoid regressions.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
> 2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 759b1b8..f4d6673 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3949,8 +3949,12 @@
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> -#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> +#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
> +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
> +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
> +#define TRANS_CHICKEN2_PBC (1<<30 | 0x1ffffff)
The above _PBC value seems to be redundant. In any case on both patches:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> #define SOUTH_CHICKEN1 0xc2000
> #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ce3d892..e4ead41 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3589,9 +3589,14 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> * downward, on (only) LVDS of some HP laptops with IVY.
> */
> for_each_pipe(pipe) {
> - val = TRANS_CHICKEN2_TIMING_OVERRIDE;
> + val = I915_READ(TRANS_CHICKEN2(pipe));
> + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> + val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> if (dev_priv->fdi_rx_polarity_inverted)
> val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> I915_WRITE(TRANS_CHICKEN2(pipe), val);
> }
> /* WADP0ClockGatingDisable */
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2
2013-04-10 15:23 ` Imre Deak
@ 2013-04-16 18:10 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2013-04-16 18:10 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, Paulo Zanoni
On Wed, Apr 10, 2013 at 06:23:25PM +0300, Imre Deak wrote:
> On Mon, 2013-04-08 at 15:48 -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits
> > are being zeroed, but I couldn't find a reason for this, so leave them
> > as they are for now to avoid regressions.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> > drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
> > 2 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 759b1b8..f4d6673 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3949,8 +3949,12 @@
> > #define _TRANSA_CHICKEN2 0xf0064
> > #define _TRANSB_CHICKEN2 0xf1064
> > #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > -#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> > -#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> > +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> > +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
> > +#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
> > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
> > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
> > +#define TRANS_CHICKEN2_PBC (1<<30 | 0x1ffffff)
>
> The above _PBC value seems to be redundant. In any case on both patches:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Redundant #define deleted and both patches merged, thanks.
-Daniel
>
> >
> > #define SOUTH_CHICKEN1 0xc2000
> > #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ce3d892..e4ead41 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3589,9 +3589,14 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> > * downward, on (only) LVDS of some HP laptops with IVY.
> > */
> > for_each_pipe(pipe) {
> > - val = TRANS_CHICKEN2_TIMING_OVERRIDE;
> > + val = I915_READ(TRANS_CHICKEN2(pipe));
> > + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> > + val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > if (dev_priv->fdi_rx_polarity_inverted)
> > val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> > + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> > + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> > I915_WRITE(TRANS_CHICKEN2(pipe), val);
> > }
> > /* WADP0ClockGatingDisable */
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-04-16 18:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-04-08 18:48 [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
2013-04-08 18:48 ` [PATCH 2/2] drm/i915: preserve the PBC bits of TRANS_CHICKEN2 Paulo Zanoni
2013-04-10 15:23 ` Imre Deak
2013-04-16 18:10 ` Daniel Vetter
2013-04-08 21:30 ` [PATCH 1/2] drm/i915: set CPT FDI RX polarity bits based on VBT Paulo Zanoni
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