From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW
Date: Mon, 8 Apr 2013 23:00:58 +0300 [thread overview]
Message-ID: <1365451258-25493-1-git-send-email-jani.nikula@intel.com> (raw)
Workaround to avoid intermittent aux channel failures, per spec change.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Untested.
---
drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..5fec183 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -344,7 +344,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* Note that PCH attached eDP panels should use a 125MHz input
* clock divider.
*/
- if (is_cpu_edp(intel_dp)) {
+ if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+ /* Workaround for non-ULT HSW */
+ aux_clock_divider = 74;
+ } else if (is_cpu_edp(intel_dp)) {
if (HAS_DDI(dev))
aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
else if (IS_VALLEYVIEW(dev))
--
1.7.10.4
next reply other threads:[~2013-04-08 20:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-08 20:00 Jani Nikula [this message]
2013-04-08 21:03 ` [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW Paulo Zanoni
2013-04-09 5:11 ` [PATCH v2] " Jani Nikula
2013-04-09 14:49 ` Paulo Zanoni
2013-04-09 14:59 ` Daniel Vetter
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