From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v2] drm/i915: use lower aux clock divider on non-ULT HSW
Date: Tue, 9 Apr 2013 16:59:52 +0200 [thread overview]
Message-ID: <20130409145952.GZ2228@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGT_3a9DJGAs=DS+mT=aACvZ-Gs1=K6kSxHrtogL5bk6ww@mail.gmail.com>
On Tue, Apr 09, 2013 at 11:49:45AM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/4/9 Jani Nikula <jani.nikula@intel.com>:
> > Workaround to avoid intermittent aux channel failures, per spec change.
> >
> > v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > ---
> >
> > Untested.
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 482b5e5..f8474d1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> > aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> > else
> > aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> > - } else if (HAS_PCH_SPLIT(dev))
> > + } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>
> There's a space and a tab between "else" and "if", but I guess Daniel
> will fix this :)
Done.
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Queued for -next, thanks for the patch.
-Daniel
>
> > + /* Workaround for non-ULT HSW */
> > + aux_clock_divider = 74;
> > + } else if (HAS_PCH_SPLIT(dev)) {
> > aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> > - else
> > + } else {
> > aux_clock_divider = intel_hrawclk(dev) / 2;
> > + }
> >
> > if (IS_GEN6(dev))
> > precharge = 3;
> > --
> > 1.7.10.4
> >
>
>
>
> --
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-04-09 14:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-08 20:00 [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW Jani Nikula
2013-04-08 21:03 ` Paulo Zanoni
2013-04-09 5:11 ` [PATCH v2] " Jani Nikula
2013-04-09 14:49 ` Paulo Zanoni
2013-04-09 14:59 ` Daniel Vetter [this message]
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