* [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW
@ 2013-04-08 20:00 Jani Nikula
2013-04-08 21:03 ` Paulo Zanoni
0 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2013-04-08 20:00 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Workaround to avoid intermittent aux channel failures, per spec change.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Untested.
---
drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..5fec183 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -344,7 +344,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* Note that PCH attached eDP panels should use a 125MHz input
* clock divider.
*/
- if (is_cpu_edp(intel_dp)) {
+ if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+ /* Workaround for non-ULT HSW */
+ aux_clock_divider = 74;
+ } else if (is_cpu_edp(intel_dp)) {
if (HAS_DDI(dev))
aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
else if (IS_VALLEYVIEW(dev))
--
1.7.10.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW
2013-04-08 20:00 [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW Jani Nikula
@ 2013-04-08 21:03 ` Paulo Zanoni
2013-04-09 5:11 ` [PATCH v2] " Jani Nikula
0 siblings, 1 reply; 5+ messages in thread
From: Paulo Zanoni @ 2013-04-08 21:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: Intel Graphics Development
Hi
2013/4/8 Jani Nikula <jani.nikula@intel.com>:
> Workaround to avoid intermittent aux channel failures, per spec change.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Untested.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 482b5e5..5fec183 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> * Note that PCH attached eDP panels should use a 125MHz input
> * clock divider.
> */
> - if (is_cpu_edp(intel_dp)) {
> + if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> + /* Workaround for non-ULT HSW */
> + aux_clock_divider = 74;
> + } else if (is_cpu_edp(intel_dp)) {
Your patch will affect the CPU DP AUX too, but it should only affect
the PCH DP AUX registers. You should move this to the !is_cpu_edp
case.
> if (HAS_DDI(dev))
> aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
> else if (IS_VALLEYVIEW(dev))
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] drm/i915: use lower aux clock divider on non-ULT HSW
2013-04-08 21:03 ` Paulo Zanoni
@ 2013-04-09 5:11 ` Jani Nikula
2013-04-09 14:49 ` Paulo Zanoni
0 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2013-04-09 5:11 UTC (permalink / raw)
To: intel-gfx, Paulo Zanoni; +Cc: jani.nikula
Workaround to avoid intermittent aux channel failures, per spec change.
v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Untested.
---
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..f8474d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
- } else if (HAS_PCH_SPLIT(dev))
+ } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+ /* Workaround for non-ULT HSW */
+ aux_clock_divider = 74;
+ } else if (HAS_PCH_SPLIT(dev)) {
aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
- else
+ } else {
aux_clock_divider = intel_hrawclk(dev) / 2;
+ }
if (IS_GEN6(dev))
precharge = 3;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: use lower aux clock divider on non-ULT HSW
2013-04-09 5:11 ` [PATCH v2] " Jani Nikula
@ 2013-04-09 14:49 ` Paulo Zanoni
2013-04-09 14:59 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Paulo Zanoni @ 2013-04-09 14:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: Intel Graphics Development
Hi
2013/4/9 Jani Nikula <jani.nikula@intel.com>:
> Workaround to avoid intermittent aux channel failures, per spec change.
>
> v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Untested.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 482b5e5..f8474d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> else
> aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> - } else if (HAS_PCH_SPLIT(dev))
> + } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
There's a space and a tab between "else" and "if", but I guess Daniel
will fix this :)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> + /* Workaround for non-ULT HSW */
> + aux_clock_divider = 74;
> + } else if (HAS_PCH_SPLIT(dev)) {
> aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> - else
> + } else {
> aux_clock_divider = intel_hrawclk(dev) / 2;
> + }
>
> if (IS_GEN6(dev))
> precharge = 3;
> --
> 1.7.10.4
>
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: use lower aux clock divider on non-ULT HSW
2013-04-09 14:49 ` Paulo Zanoni
@ 2013-04-09 14:59 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2013-04-09 14:59 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Jani Nikula, Intel Graphics Development
On Tue, Apr 09, 2013 at 11:49:45AM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/4/9 Jani Nikula <jani.nikula@intel.com>:
> > Workaround to avoid intermittent aux channel failures, per spec change.
> >
> > v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > ---
> >
> > Untested.
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 482b5e5..f8474d1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> > aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> > else
> > aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> > - } else if (HAS_PCH_SPLIT(dev))
> > + } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>
> There's a space and a tab between "else" and "if", but I guess Daniel
> will fix this :)
Done.
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Queued for -next, thanks for the patch.
-Daniel
>
> > + /* Workaround for non-ULT HSW */
> > + aux_clock_divider = 74;
> > + } else if (HAS_PCH_SPLIT(dev)) {
> > aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> > - else
> > + } else {
> > aux_clock_divider = intel_hrawclk(dev) / 2;
> > + }
> >
> > if (IS_GEN6(dev))
> > precharge = 3;
> > --
> > 1.7.10.4
> >
>
>
>
> --
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-04-09 14:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2013-04-08 20:00 [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW Jani Nikula
2013-04-08 21:03 ` Paulo Zanoni
2013-04-09 5:11 ` [PATCH v2] " Jani Nikula
2013-04-09 14:49 ` Paulo Zanoni
2013-04-09 14:59 ` Daniel Vetter
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