[PATCH 1/2] drm/i915: Print ring min freq scaling

[Ben Widawsky <benjamin.widawsky@intel.com>]

This allows us to keep track of the values being set if we want to tweak
this code.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d27eda6..31cf188 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3671,6 +3671,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
 			ring_freq = (gpu_freq * 5 + 3) / 4;
 			ring_freq = max(min_ring_freq, ring_freq);
 			/* leave ia_freq as the default, chosen by cpufreq */
+
+			DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n",
+					 ring_freq * 100, gpu_freq * 50);
 		} else {
 			/* On older processors, there is no separate ring
 			 * clock domain, so in order to boost the bandwidth
@@ -3684,6 +3687,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
 			else
 				ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
 			ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
+
+			DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n",
+					 ia_freq * 100, gpu_freq * 50);
 		}
 
 		sandybridge_pcode_write(dev_priv,
-- 
1.8.4