From: Rodrigo Vivi <rodrigo.vivi@gmail.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 9/9] drm/i915: PF CRC may not work on HSW
Date: Fri, 7 Feb 2014 18:37:07 -0200 [thread overview]
Message-ID: <1391805427-4576-10-git-send-email-rodrigo.vivi@gmail.com> (raw)
In-Reply-To: <1391805427-4576-1-git-send-email-rodrigo.vivi@gmail.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When using pipe A and transcoder EDP w/o panel fitter on
HSW, the PF CRC isn't available as the panel fitter is entirely
bypassed. Check for this and refuse to give out CRCs.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2dc05c3..de020c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2548,7 +2548,30 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
return 0;
}
-static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
+static bool hsw_crc_source_pf_ok(struct drm_device *dev, enum pipe pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ bool ok;
+
+ if (!IS_HASWELL(dev) || pipe != PIPE_A)
+ return true;
+
+ mutex_lock(&crtc->base.mutex);
+
+ /* pipe A -> no panel fitter -> transcoder EDP == no PF CRC */
+ ok = !crtc->active ||
+ crtc->config.cpu_transcoder != TRANSCODER_EDP ||
+ crtc->config.pch_pfit.enabled;
+
+ mutex_unlock(&crtc->base.mutex);
+
+ return ok;
+}
+
+static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
+ enum pipe pipe,
+ enum intel_pipe_crc_source *source,
uint32_t *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
@@ -2562,6 +2585,8 @@ static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
break;
case INTEL_PIPE_CRC_SOURCE_PF:
+ if (!hsw_crc_source_pf_ok(dev, pipe))
+ return -EINVAL;
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
break;
case INTEL_PIPE_CRC_SOURCE_NONE:
@@ -2598,7 +2623,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(&source, &val);
else
- ret = ivb_pipe_crc_ctl_reg(&source, &val);
+ ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
if (ret != 0)
return ret;
--
1.8.3.1
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next prev parent reply other threads:[~2014-02-07 20:37 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-07 20:36 [PATCH 0/9] drm-intel-collector - update Rodrigo Vivi
2014-02-07 20:36 ` [PATCH 1/9] drm/i915: Propagate errors on failed PPGTT Rodrigo Vivi
2014-02-07 20:37 ` [PATCH 2/9] drm/i915: wrap crtc enable/disable Rodrigo Vivi
2014-02-07 20:37 ` [PATCH 3/9] drm/i915: make crtc enable/disable asynchronous Rodrigo Vivi
2014-03-03 23:18 ` Jesse Barnes
2014-02-07 20:37 ` [PATCH 4/9] drm/i915: Propagate PCI read/write errors during vga_set_state() Rodrigo Vivi
2014-02-10 10:35 ` Daniel Vetter
2014-02-07 20:37 ` [PATCH 5/9] drm/i915: Short-circuit no-op vga_set_state() Rodrigo Vivi
2014-02-10 10:36 ` Daniel Vetter
2014-02-07 20:37 ` [PATCH 6/9] drm/i915: Verify address field of PCBR register Rodrigo Vivi
2014-02-07 20:37 ` [PATCH 7/9] drm/i915: Bring UP Power Wells before disabling RC6 Rodrigo Vivi
2014-02-07 20:37 ` [PATCH 8/9] drm/i915: Flush GPU rendering with a lockless wait during a pagefault Rodrigo Vivi
2014-02-10 15:52 ` Damien Lespiau
2014-02-10 17:32 ` Daniel Vetter
2014-02-07 20:37 ` Rodrigo Vivi [this message]
2014-02-10 10:43 ` [PATCH 9/9] drm/i915: PF CRC may not work on HSW Daniel Vetter
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