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* [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
@ 2014-02-12 16:21 Daniel Vetter
  2014-02-12 16:52 ` Ville Syrjälä
  2014-02-12 16:55 ` Daniel Vetter
  0 siblings, 2 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-02-12 16:21 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Just a bit of polish which I hope will help me with massaging some
internal patches to use Imre's reworked pipestat handling:
- Don't check for underrun reporting twice.
- Frob the comments a bit.
- Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
  only have one place which does this, so better to make it explicit.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 25 ++++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_reg.h |  4 ----
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 386a640b7c92..bbd65809742b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1559,25 +1559,40 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
 	spin_lock(&dev_priv->irq_lock);
 	for_each_pipe(pipe) {
 		int reg;
-		u32 mask;
+		u32 mask, iir_bit;
 
-		if (!dev_priv->pipestat_irq_mask[pipe] &&
-		    !__cpu_fifo_underrun_reporting_enabled(dev, pipe))
+		if (!dev_priv->pipestat_irq_mask[pipe])
 			continue;
 
 		reg = PIPESTAT(pipe);
 		pipe_stats[pipe] = I915_READ(reg);
 
 		/*
-		 * Clear the PIPE*STAT regs before the IIR
+		 * pipe_stat bits get signalled even when the interrupt is
+		 * disabled with the mask bits, and some of the status bits do
+		 * not generate interrupts at all (like the underrun bit). Hence
+		 * we need to be careful that we only handle what we want to
+		 * handle.
 		 */
 		mask = PIPESTAT_INT_ENABLE_MASK;
 		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
 			mask |= PIPE_FIFO_UNDERRUN_STATUS;
-		if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe))
+
+		switch (pipe) {
+		case PIPE_A:
+			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
+			break;
+		case PIPE_B:
+			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+			break;
+		}
+		if (iir & iir_bit)
 			mask |= dev_priv->pipestat_irq_mask[pipe];
 		pipe_stats[pipe] &= mask;
 
+		/*
+		 * Clear the PIPE*STAT regs before the IIR
+		 */
 		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
 					PIPESTAT_INT_STATUS_MASK))
 			I915_WRITE(reg, pipe_stats[pipe]);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 645221270c34..8344541bbb93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -997,10 +997,6 @@
 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
-#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)				\
-	((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT :	\
-	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
-
 #define I915_DEBUG_INTERRUPT				(1<<2)
 #define I915_USER_INTERRUPT				(1<<1)
 #define I915_ASLE_INTERRUPT				(1<<0)
-- 
1.8.1.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
  2014-02-12 16:21 [PATCH] drm/i915: Some polish for the new pipestat_irq_handler Daniel Vetter
@ 2014-02-12 16:52 ` Ville Syrjälä
  2014-02-12 17:12   ` Daniel Vetter
  2014-02-12 16:55 ` Daniel Vetter
  1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2014-02-12 16:52 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Feb 12, 2014 at 05:21:06PM +0100, Daniel Vetter wrote:
> Just a bit of polish which I hope will help me with massaging some
> internal patches to use Imre's reworked pipestat handling:
> - Don't check for underrun reporting twice.
> - Frob the comments a bit.
> - Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
>   only have one place which does this, so better to make it explicit.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 25 ++++++++++++++++++++-----
>  drivers/gpu/drm/i915/i915_reg.h |  4 ----
>  2 files changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 386a640b7c92..bbd65809742b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1559,25 +1559,40 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
>  	spin_lock(&dev_priv->irq_lock);
>  	for_each_pipe(pipe) {
>  		int reg;
> -		u32 mask;
> +		u32 mask, iir_bit;
>  
> -		if (!dev_priv->pipestat_irq_mask[pipe] &&
> -		    !__cpu_fifo_underrun_reporting_enabled(dev, pipe))
> +		if (!dev_priv->pipestat_irq_mask[pipe])
>  			continue;

Underrun reporting doesn't have an enable bit, so if we don't check it
here we'd fail to detect underruns when no PIPESTAT interrupts are
enabled. Currently that probably wouldn't happen since we always enable
some display interrupts, but I'd keep the check nonetheless.

>  
>  		reg = PIPESTAT(pipe);
>  		pipe_stats[pipe] = I915_READ(reg);
>  
>  		/*
> -		 * Clear the PIPE*STAT regs before the IIR
> +		 * pipe_stat bits get signalled even when the interrupt is
> +		 * disabled with the mask bits, and some of the status bits do
> +		 * not generate interrupts at all (like the underrun bit). Hence
> +		 * we need to be careful that we only handle what we want to
> +		 * handle.
>  		 */
>  		mask = PIPESTAT_INT_ENABLE_MASK;
>  		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
>  			mask |= PIPE_FIFO_UNDERRUN_STATUS;
> -		if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe))
> +
> +		switch (pipe) {
> +		case PIPE_A:
> +			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
> +			break;
> +		case PIPE_B:
> +			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> +			break;
> +		}
> +		if (iir & iir_bit)
>  			mask |= dev_priv->pipestat_irq_mask[pipe];
>  		pipe_stats[pipe] &= mask;
>  
> +		/*
> +		 * Clear the PIPE*STAT regs before the IIR
> +		 */
>  		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
>  					PIPESTAT_INT_STATUS_MASK))
>  			I915_WRITE(reg, pipe_stats[pipe]);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 645221270c34..8344541bbb93 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -997,10 +997,6 @@
>  #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
>  #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
>  #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
> -#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)				\
> -	((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT :	\
> -	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
> -
>  #define I915_DEBUG_INTERRUPT				(1<<2)
>  #define I915_USER_INTERRUPT				(1<<1)
>  #define I915_ASLE_INTERRUPT				(1<<0)
> -- 
> 1.8.1.4

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
  2014-02-12 16:21 [PATCH] drm/i915: Some polish for the new pipestat_irq_handler Daniel Vetter
  2014-02-12 16:52 ` Ville Syrjälä
@ 2014-02-12 16:55 ` Daniel Vetter
  2014-02-12 17:31   ` Imre Deak
  1 sibling, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2014-02-12 16:55 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Just a bit of polish which I hope will help me with massaging some
internal patches to use Imre's reworked pipestat handling:
- Don't check for underrun reporting or enable pipestat interrupts
  twice.
- Frob the comments a bit.
- Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
  only have one place which does this, so better to make it explicit.

v2: Ville noticed that I've broken the logic a bit with trying to
avoid checking whether we're interested in a given pipe twice. push
the PIPESTAT read down after we've computed the mask of interesting
bits first to avoid that duplication properly.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 36 +++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/i915_reg.h |  4 ----
 2 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 386a640b7c92..a45ed67407bd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1559,25 +1559,39 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
 	spin_lock(&dev_priv->irq_lock);
 	for_each_pipe(pipe) {
 		int reg;
-		u32 mask;
-
-		if (!dev_priv->pipestat_irq_mask[pipe] &&
-		    !__cpu_fifo_underrun_reporting_enabled(dev, pipe))
-			continue;
-
-		reg = PIPESTAT(pipe);
-		pipe_stats[pipe] = I915_READ(reg);
+		u32 mask, iir_bit;
 
 		/*
-		 * Clear the PIPE*STAT regs before the IIR
+		 * PIPESTAT bits get signalled even when the interrupt is
+		 * disabled with the mask bits, and some of the status bits do
+		 * not generate interrupts at all (like the underrun bit). Hence
+		 * we need to be careful that we only handle what we want to
+		 * handle.
 		 */
 		mask = PIPESTAT_INT_ENABLE_MASK;
 		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
 			mask |= PIPE_FIFO_UNDERRUN_STATUS;
-		if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe))
+
+		switch (pipe) {
+		case PIPE_A:
+			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
+			break;
+		case PIPE_B:
+			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+			break;
+		}
+		if (iir & iir_bit)
 			mask |= dev_priv->pipestat_irq_mask[pipe];
-		pipe_stats[pipe] &= mask;
 
+		if (!mask)
+			continue;
+
+		reg = PIPESTAT(pipe);
+		pipe_stats[pipe] = I915_READ(reg) & mask;
+
+		/*
+		 * Clear the PIPE*STAT regs before the IIR
+		 */
 		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
 					PIPESTAT_INT_STATUS_MASK))
 			I915_WRITE(reg, pipe_stats[pipe]);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 645221270c34..8344541bbb93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -997,10 +997,6 @@
 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
-#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)				\
-	((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT :	\
-	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
-
 #define I915_DEBUG_INTERRUPT				(1<<2)
 #define I915_USER_INTERRUPT				(1<<1)
 #define I915_ASLE_INTERRUPT				(1<<0)
-- 
1.8.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
  2014-02-12 16:52 ` Ville Syrjälä
@ 2014-02-12 17:12   ` Daniel Vetter
  0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-02-12 17:12 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Intel Graphics Development

On Wed, Feb 12, 2014 at 5:52 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>>  drivers/gpu/drm/i915/i915_irq.c | 25 ++++++++++++++++++++-----
>>  drivers/gpu/drm/i915/i915_reg.h |  4 ----
>>  2 files changed, 20 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 386a640b7c92..bbd65809742b 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1559,25 +1559,40 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
>>       spin_lock(&dev_priv->irq_lock);
>>       for_each_pipe(pipe) {
>>               int reg;
>> -             u32 mask;
>> +             u32 mask, iir_bit;
>>
>> -             if (!dev_priv->pipestat_irq_mask[pipe] &&
>> -                 !__cpu_fifo_underrun_reporting_enabled(dev, pipe))
>> +             if (!dev_priv->pipestat_irq_mask[pipe])
>>                       continue;
>
> Underrun reporting doesn't have an enable bit, so if we don't check it
> here we'd fail to detect underruns when no PIPESTAT interrupts are
> enabled. Currently that probably wouldn't happen since we always enable
> some display interrupts, but I'd keep the check nonetheless.

Oh right, I've misunderstood the code. Still I'm not too happy about
the duplication of logic we have here with two places computing
whether we're interested in the pipestat bits for this pipe.

I'll respin a bit.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
  2014-02-12 16:55 ` Daniel Vetter
@ 2014-02-12 17:31   ` Imre Deak
  2014-02-12 20:28     ` Daniel Vetter
  0 siblings, 1 reply; 6+ messages in thread
From: Imre Deak @ 2014-02-12 17:31 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development


[-- Attachment #1.1: Type: text/plain, Size: 3665 bytes --]

On Wed, 2014-02-12 at 17:55 +0100, Daniel Vetter wrote:
> Just a bit of polish which I hope will help me with massaging some
> internal patches to use Imre's reworked pipestat handling:
> - Don't check for underrun reporting or enable pipestat interrupts
>   twice.
> - Frob the comments a bit.
> - Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
>   only have one place which does this, so better to make it explicit.
> 
> v2: Ville noticed that I've broken the logic a bit with trying to
> avoid checking whether we're interested in a given pipe twice. push
> the PIPESTAT read down after we've computed the mask of interesting
> bits first to avoid that duplication properly.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Looks simpler, so:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 36 +++++++++++++++++++++++++-----------
>  drivers/gpu/drm/i915/i915_reg.h |  4 ----
>  2 files changed, 25 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 386a640b7c92..a45ed67407bd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1559,25 +1559,39 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
>  	spin_lock(&dev_priv->irq_lock);
>  	for_each_pipe(pipe) {
>  		int reg;
> -		u32 mask;
> -
> -		if (!dev_priv->pipestat_irq_mask[pipe] &&
> -		    !__cpu_fifo_underrun_reporting_enabled(dev, pipe))
> -			continue;
> -
> -		reg = PIPESTAT(pipe);
> -		pipe_stats[pipe] = I915_READ(reg);
> +		u32 mask, iir_bit;
>  
>  		/*
> -		 * Clear the PIPE*STAT regs before the IIR
> +		 * PIPESTAT bits get signalled even when the interrupt is
> +		 * disabled with the mask bits, and some of the status bits do
> +		 * not generate interrupts at all (like the underrun bit). Hence
> +		 * we need to be careful that we only handle what we want to
> +		 * handle.
>  		 */
>  		mask = PIPESTAT_INT_ENABLE_MASK;
>  		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
>  			mask |= PIPE_FIFO_UNDERRUN_STATUS;
> -		if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe))
> +
> +		switch (pipe) {
> +		case PIPE_A:
> +			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
> +			break;
> +		case PIPE_B:
> +			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> +			break;
> +		}
> +		if (iir & iir_bit)
>  			mask |= dev_priv->pipestat_irq_mask[pipe];
> -		pipe_stats[pipe] &= mask;
>  
> +		if (!mask)
> +			continue;
> +
> +		reg = PIPESTAT(pipe);
> +		pipe_stats[pipe] = I915_READ(reg) & mask;
> +
> +		/*
> +		 * Clear the PIPE*STAT regs before the IIR
> +		 */
>  		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
>  					PIPESTAT_INT_STATUS_MASK))
>  			I915_WRITE(reg, pipe_stats[pipe]);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 645221270c34..8344541bbb93 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -997,10 +997,6 @@
>  #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
>  #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
>  #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
> -#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)				\
> -	((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT :	\
> -	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
> -
>  #define I915_DEBUG_INTERRUPT				(1<<2)
>  #define I915_USER_INTERRUPT				(1<<1)
>  #define I915_ASLE_INTERRUPT				(1<<0)


[-- Attachment #1.2: This is a digitally signed message part --]
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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Some polish for the new pipestat_irq_handler
  2014-02-12 17:31   ` Imre Deak
@ 2014-02-12 20:28     ` Daniel Vetter
  0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-02-12 20:28 UTC (permalink / raw)
  To: Imre Deak; +Cc: Daniel Vetter, Intel Graphics Development

On Wed, Feb 12, 2014 at 07:31:16PM +0200, Imre Deak wrote:
> On Wed, 2014-02-12 at 17:55 +0100, Daniel Vetter wrote:
> > Just a bit of polish which I hope will help me with massaging some
> > internal patches to use Imre's reworked pipestat handling:
> > - Don't check for underrun reporting or enable pipestat interrupts
> >   twice.
> > - Frob the comments a bit.
> > - Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We
> >   only have one place which does this, so better to make it explicit.
> > 
> > v2: Ville noticed that I've broken the logic a bit with trying to
> > avoid checking whether we're interested in a given pipe twice. push
> > the PIPESTAT read down after we've computed the mask of interesting
> > bits first to avoid that duplication properly.
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Looks simpler, so:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-02-12 20:28 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-02-12 16:21 [PATCH] drm/i915: Some polish for the new pipestat_irq_handler Daniel Vetter
2014-02-12 16:52 ` Ville Syrjälä
2014-02-12 17:12   ` Daniel Vetter
2014-02-12 16:55 ` Daniel Vetter
2014-02-12 17:31   ` Imre Deak
2014-02-12 20:28     ` Daniel Vetter

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