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From: Sinclair Yeh <sinclair.yeh@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] Fix GPU Hang on BYT
Date: Fri, 14 Feb 2014 14:13:29 -0800	[thread overview]
Message-ID: <1392416009-27050-1-git-send-email-sinclair.yeh@intel.com> (raw)

On certain OpenGL benchmark applications, setting this bit results in
frequent GPU hangs.  On BYT-M/I, the hangs go away by not setting this
bit.
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6b877a..3ba037e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5004,9 +5004,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
 				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
 
-	/* WaDisableL3CacheAging:vlv */
-	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
-
 	/* WaForceL3Serialization:vlv */
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
 		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
-- 
1.8.1.4

             reply	other threads:[~2014-02-14 22:14 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-14 22:13 Sinclair Yeh [this message]
2014-02-19 21:09 ` [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on BYT Sinclair Yeh
2014-02-20 16:18   ` Jesse Barnes
2014-03-04 15:47     ` Daniel Vetter

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