Re: [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on BYT

[Daniel Vetter <daniel@ffwll.ch>]

On Thu, Feb 20, 2014 at 08:18:39AM -0800, Jesse Barnes wrote:
> On Wed, 19 Feb 2014 13:09:31 -0800
> Sinclair Yeh <sinclair.yeh@intel.com> wrote:
> 
> > V2:  edit the commit message to contain more info
> > The W/A spreadsheet says this is still required, but the b-spec says
> > it's not for BYT-T.  So the documentation is not clear.  However,
> > our experience with the other SKUs of BYT-I/M on Android and Linux
> > suggests that setting this bit actually causes GPU hang for certain
> > OGL benchmark applications.
> > 
> > Removing this bit completely resolves the GPU hangs.

Your sob is missing. Please see the developer's certificate of origin so
that you're aware of what you actually sign off on. Since you work for the
same company I've snuck this in ;-)

> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a6b877a..3ba037e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5004,9 +5004,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >  		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
> >  				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >  
> > -	/* WaDisableL3CacheAging:vlv */
> > -	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> > -
> >  	/* WaForceL3Serialization:vlv */
> >  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> >  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> 
> I don't think we have good docs on this, but since it works empirically:
> 
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch