From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 1/2] drm/i915: PPGTT Cacheability Override
Date: Fri, 5 Jun 2015 15:58:22 -0700 [thread overview]
Message-ID: <1433545103-11618-1-git-send-email-rodrigo.vivi@intel.com> (raw)
Override Cacheability to WB in LLC/eLLC - Aged 3 1000
for better performance.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d091fec..b0fd5ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6186,7 +6186,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
ilk_init_lp_watermarks(dev);
/* WaSwitchSolVfFArbitrationPriority:bdw */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL |
+ ECOCHK_PPGTT_WB_HSW);
/* WaPsrDPAMaskVBlankInSRD:bdw */
I915_WRITE(CHICKEN_PAR1_1,
--
2.1.0
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next reply other threads:[~2015-06-05 22:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-05 22:58 Rodrigo Vivi [this message]
2015-06-05 22:58 ` [PATCH 2/2] drm/i915/bdw: WaGttCachingOffByDefault: bdw Rodrigo Vivi
2015-06-06 13:21 ` shuang.he
2015-06-08 19:20 ` Damien Lespiau
2015-06-09 9:20 ` Chris Wilson
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